ADA2200

ADA2200 (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 24

Technical content

and Configurable Analog Filter Data Sheet ADA2200

FEATURES

Demodulates signal input bandwidths to 30 kHz Programmable filter enables variable bandwidths Filter tracks input carrier frequency Programmable reference clock frequency Flexible system interface Single-ended/differential signal inputs and outputs Rail-to-rail outputs directly drive analog-to-digital converters (ADCs) Phase detection sensitivity of 9.3m°θREL rms Configurable with 3-wire and 4-wire serial port interface (SPI) or seamless boot from I2C EEPROMs Very low power operation 395 μA at fCLKIN = 500 kHz Single supply: 2.7 V to 3.6 V Specified temperature range: −40°C to +85°C 16-lead TSSOP package

APPLICATIONS

Sensor signal conditioning Lock-in amplifiers Phase detectors Precision tunable filters Signal recovery Control systems FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The ADA2200 is a sampled analog technology1 synchronous demodulator for signal conditioning in industrial, medical, and communications applications. The ADA2200 is an analog input, sampled analog output device. The signal processing is performed entirely in the analog domain by charge sharing among capacitors, which eliminates the effects of quantization noise and rounding errors. The ADA2200 includes an analog domain, low-pass decimation filter, a programmable infinite impulse response (IIR) filter, and a mixer. This combination of features reduces ADC sample rates and lowers the downstream digital signal processing requirements. The ADA2200 acts as a precision filter when the demodulation function is disabled. The filter has a programmable bandwidth and tunable center frequency. The filter characteristics are highly stable over temperature, supply, and process variation. Single-ended and differential signal interfaces are possible on both input and output terminals, simplifying the connection to other components of the signal chain. The low power consumption and rail-to-rail operation is ideal for battery-powered and low voltage systems. The ADA2200 can be programmed over its SPI-compatible serial port or can automatically boot from the EEPROM through its I 2C interface. On-chip clock generation produces a mixing signal with a programmable frequency and phase. In addition, the ADA2200 synchronization output signal eases interfacing to other sampled systems, such as data converters and multiplexers. The ADA2200 is available in a 16-lead TSSOP package. Its performance is specified over the industrial temperature range of −40°C to +85°C. Note that throughout this data sheet, multifunction pins, such as SCLK/SCL, are referred to either by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant. 1 Patent pending. INP INN OUTP OUTN VOCM SCLK/SCL SDIO/SDA CS/A0 RCLK/SDO VDD LPF

8 PROGRAM

÷2n+1÷2m ÷8 90°fSOfSI fM XOUT CLKIN SYNCO GND RST BOOT ADA2200 12295-001 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

REVISION HISTORY

8/14—Revision 0: Initial Version Rev. 0 | Page 2 of 24

VDD = 3.3 V, VOCM = VDD/2, fCLKIN = fSI = 500 kHz, default register configuration, differential input/output, RL = 1 MΩ to GND, TA = 25°C, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit SYNCHRONOUS DEMODULATION Measurements are cycle mean values,1 4 V p-p differential, fIN = 7.8125 kHz Conversion Gain1 1.02 1.055 1.09 V/V rms Average Temperature Drift 5 ppm/°C Output Offset, Shorted Inputs −39 +39 mV Average Temperature Drift 6.5 μV/°C Power Supply Sensitivity Change in output over change in VDD 0.5 mV/V Measurement Noise Input signal at 83°θREL1 240 μV rms Phase Delay (°θDELAY)1 Input signal relative to RCLK 83 °θREL Average Temperature Drift 70 μ°θREL/°C Phase Measurement Noise Input signal at 83°θREL 9.3 m°θREL rms Shorted Input Noise 0.1 Hz to 10 Hz 300 μV p-p Common-Mode Rejection2 0 kHz to 1 kHz offset from fMOD 75 dB Demodulation Signal Bandwidth fCLKIN = 1 MHz 30 kHz INPUT CHARACTERISTICS Input Voltage Range INP or INN to GND 0.3 VDD − 0.3 V Common-Mode Input Voltage Range 4 V p-p differential input VOCM − 0.2 VOCM + 0.2 V Single-Ended Input Voltage Range Reference Input VOCM − 0.2 VOCM + 0.2 V Signal Input VOCM − 1.0 VOCM + 1.0 V Input Impedance3 INP to INN 80 kΩ Input Signal Bandwidth (−3 dB) Input sample and hold circuit 4 MHz OUTPUT CHARACTERISTICS Each output, RL = 10 kΩ to GND Output Voltage Range 0.3 VDD − 0.3 V Short-Circuit Current OUTP or OUTN to GND 15 mA Common-Mode Output (VOCM) Voltage 1.63 1.65 1.67 V Average Temperature Drift 9 μV/°C Output Settling Time, to 0.1% of Final Value

3.7 V output step, RLOAD = 10 kΩ||10 pF,

fCLKIN = 125 kHz 15 μs DEFAULT FILTER CHARACTERISTICS Mixing disabled, VIN = 4 V p-p differential Center Frequency (fC) fC = fSO/8 7.8125 kHz Quality Factor (Q) fC/(filter 3 dB bandwidth) 1.9 Hz/ΔHz Pass Band Gain fIN = 7.8125 kHz 1.05 V/V TOTAL HARMONIC DISTORTION (THD) Filter configuration = LPF at fNYQ/6, fIN =

850 Hz, VIN = 4 V p-p differential input

Second Through Fifth Harmonics −80 dBc CLOCKING CHARACTERISTICS CLKIN Frequency Range (fCLKIN) TA = −40°C to +85°C CLKIN DIV[2:0] = 256 2.56 20 MHz CLKIN DIV[2:0] = 64 0.64 20 MHz CLKIN DIV[2:0] = 16 0.16 16 MHz CLKIN DIV[2:0] = 1 0.01 1 MHz Maximum CLKIN Frequency While booting from EEPROM 12.8 MHz Rev. 0 | Page 3 of 24

1 See the Terminology section. 3 The input impedance is equal to a 4 pF capacitor switched at fCLKIN. Therefore, the input impedance = 1012/(2πfCLKIN × 4). VDD = 2.7 V to 3.6 V, default register configuration, TA = −40 to +85°C, unless otherwise noted. Table 2. SPI Timing

Table 5. Parameter Rating Supply Voltage 3.9 V Output Short-Circuit Current Duration Indefinite Maximum Voltage at Any Input VDD + 0.3 V Minimum Voltage at Any Input GND − 0.3 V Operational Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Package Glass Transition Temperature 150°C ESD Ratings Human Body Model (HBM) 1000 V Device Model (FICDM) 500 V Machine Model (MM) 50 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for a device in a natural convection environment, soldered on a 4-layer JEDEC printed circuit board (PCB). Table 6. Package θJA θJC Unit 16-Lead TSSOP 100 14.8 °C/W ESD CAUTION Rev. 0 | Page 7 of 24

Figure 7. Pin Configuration Table 7. Pin Function Descriptions 2 SYNCO Synchronization Signal Output. 3 CS/A0 Serial Interface Chip Select Input/Boot EEPROM Address 0 Input. 4 BOOT Boot from EEPROM Control Input. 6 INP Noninverting Signal Input. 7 INN Inverting Signal Input. 8 VOCM Common-Mode Voltage Output. 11 OUTP Noninverting Output. 12 VDD Positive Supply Input. 13 RCLK/SDO Reference Clock Output/Serial Interface Data Output (in 4-Wire SPI Mode). 14 SDIO/SDA Bidirectional Serial Data (Input Only in 4-Wire SPI Mode)/I2C Bidirectional Data. 15 SCLK/SCL Serial Interface Clock Input/I2C Clock Output. 16 XOUT Crystal Driver Output. Place a crystal between this pin and CLKIN, or leave this pin disconnected.

RELATIVE PHASE (Degrees) 12295-109 –0.20 –0.15 –0.10 –0.05 0.05 0.10 0 10 20 30 40 50 60 SETTLING ERROR (%) TIME (µs) 12295-110 –10 –270 –240 –210 –180 –150 –120 –90 –60 –30 0 30 60 90 MAGNITUDE ERROR (mV) RELATIVE PHASE (Degrees) 12295-114 MAGNITUDE ERROR MAGNITUDE ERROR, OFFSET REMOVED –200 –150 –100 –50 100 150 200 0 109 8 7 6 5 4 3 2 1 OUTPUT NOISE (µV) TIME (Seconds) 12295-112 100 10k 1 100k10k1k10010 NOISE SPECTRAL DENSITY (nV/√Hz) FREQUENCY (Hz) 12295-113 CLKIN = 500kHz –1.0 –0.8 –0.6 –0.4 –0.2 0.2 0.4 0.6 0.8 1.0 –270 –240 –210 –180 –150 –120 –90 –60 –30 0 30 60 90 PHASE MEASUREMENT ERROR (Degrees) RELATIVE PHASE (Degrees) 12295-111 PHASE ERROR PHASE ERROR, OFFSET REMOVED

constant, the LPF can be used to measure amplitude. square wave output from the ADA2200 RCLK output directly. holding the output constant for ½ the sample output periods. this function, see the Applications Information section. driver. Figure 19 shows a detailed block diagram of the ADA2200. Figure 19. ADA2200 Architecture filter produces one filtered sample for every eight input samples. and are indistinguishable from the low frequency input signal. order low-pass filter is usually sufficient for the antialiasing filter. Figure 20. Decimation Filter Frequency Response sample rate or 1/32nd of the decimator input sample rate. Figure 21. Decimation Filter Transfer Function, fSI = 800 kHz

INPUT AND OUTPUT AMPLIFIERS Single-Ended Configurations If a single-ended input configuration is desired, the input signal must have a common-mode voltage near midsupply. Decouple the other inputs to the common-mode voltage of the input signal. Note that differences between the common-mode levels between the INP and INN inputs result in an offset voltage inside the device. Even though the BPF removes the offset, minimize the offset to avoid reducing the available signal swing internal to the device. For single-ended outputs, either OUTP or OUTN can be used. Leave the unused output floating. Differential Configurations Using the ADA2200 in differential mode utilizes the full dynamic range of the device and provides the best noise performance and common-mode rejection. Rev. 0 | Page 15 of 24

the amplitude and relative phase of the signal applied at it inputs. output variations can be attributed to the modulated parameter. is constant, the ADA2200 performs phase demodulation. ADA2200 with a reconstruction filter. demodulation process can be removed by digital filtering. same gain and measurement accuracy, but with a sign inversion. phase sensitivity of 36.6 mV/°θREL. the in-phase (I) and quadrature (Q) components of the signal. Figure 25. Rectangular and Polar Representation of a Signal component, set the PHASE90 bit to 1.

22 QIA +=

clock, it is likely that a reconstruction filter is required. trade-off between the noise and demodulation bandwidth. attenuation of the demodulated signal of interest. components that must be attenuated. images are inherently rejected by the ADC sampling process. 125 kHz, producing an aggregate output sample rate of 1 MHz. Figure 26. ADA2200 in an 8-Channel Simultaneous Sampling Application frequency of the on-chip IIR filter. excitation signal to the sensor. and the ADC referred to the ADA2200 inputs. Figure 27. Lock-In Amplifier Application output for five consecutive output sample periods.

8 CHANNELS

the configuration from a serial EEPROM. read/write access to all registers that configure the ADA2200. pins for input and output (SDIO and SDO). A communication cycle with the ADA2200 has two phases. the starting register address for the first byte of the data transfer. used to write the instruction byte into the device. serial port timing to the initial state of the instruction cycle. instruction bits of the current I/O operation. upon writing to the last bit of each transfer byte. The instruction byte contains the information shown in Table 9. Table 9. Serial Port Instruction Byte indicates a read operation, and Logic 0 indicates a write operation. the device based on the LSB first bit (Register 0x0000, Bit 6). An active low input starts and gates a communication cycle. pin low throughout the entire communication cycle. default is Logic 0, configuring the SDIO/SDA pin as unidirectional. (Register 0x002A, Bit 3) high activates the RCLK signal. (Register 0x0000, Bit 6). The default is MSB first (LSB first = 0). for each data byte of the multibyte communication cycle. for each data byte of the multibyte communication cycle. performed in a multibyte register access.

Table 10. Device Configuration Register Map1 Table 11. Device Configuration Register Descriptions configuration registers return to their default values. 1 = SDIO operates as an input only. The SDO signal is active.

(Hex) Bits Bit Name Description Default1 Filter Strobe 0x0010 [7:0] Load coefficients[1:0] When toggled from 0 to 1, the filter coefficients in configuration Register 0x0011 through Register 0x0027 are loaded into the IIR filter. Filter Configuration 0x0011 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC022 0x0012 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x0013 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x1D2 0x0014 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xD72 0x0015 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC02 0x0016 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x0017 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC02 0x0018 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x0019 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x1D2 0x001A [7:0] Coefficient[7:0] Programmable filter coefficients. 0x972 0x001B [7:0] Coefficient[7:0] Programmable filter coefficients. 0x7E2 0x001C [7:0] Coefficient[7:0] Programmable filter coefficients. 0x882 0x001D [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC02 0x001E [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x001F [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC02 0x0020 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x0021 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC02 0x0022 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F2 0x0023 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x002 0x0024 [7:0] Coefficient[7:0] Programmable filter coefficients. 0xE02 0x0025 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x232 0x0026 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x022 0x0027 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x242 Analog Pin Configuration 0x0028 1 INP gain 1 = only the INP input signal is sampled. An additional 6 dB of gain is applied to the signal path.

0 Clock source select 0 = device is configured to generate a clock if a crystal or

resonator is placed between the XOUT and CLKIN pins. 1 = device is configured to accept a CMOS level clock on the CLKIN pin. The internal XOUT driver is disabled. Sync Control 0x0029 5 SYNCO output enable 1 = enables the SYNCO output pad driver. 1 4 SYNCO invert 1 = inverts the SYNCO signal. 0 [3:0] SYNCO edge select These bits select one of 16 different edge locations for the SYNCO pulse relative to the output sample window. See Figure 24 for details. 1101 Demod Control 0x002A 6 PHASE90 1 = delays the phase between the RCLK output and the strobe controlling the mixing signal. See Figure 23 for details.

4 Mixer enable 1 = the last sample that is taken while RCLK is active remains held

while RCLK is inactive. 3 RCLK select 0 = sends the SDO signal to the output driver of Pin 13. 1 1 = sends the RCLK signal to the output driver of Pin 13. [2:0] VOCM select 000 = set the VOCM pin to VDD/2. Low power mode. 000 001 = use the external reference to drive VOCM. 010 = set the VOCM pin to VDD/2. Fast settling mode. 101 = set the VOCM pin to 1.2 V. Rev. 0 | Page 22 of 24

01 = the frequency of RCLK is fSO/4. 10 = the frequency of RCLK is fSO/8. are preserved. This does not initiate a boot from the EEPROM. 0 = core reset is deasserted. on the data it reads from the EEPROM.

1 Checksum passed 1 = calculated checksum matches the checksum byte read from

0 Boot from EEPROM

cycles after the boot is initiated to check for boot completion. 2 The filter coefficients listed are the default values programmed into the filter on reset. The value read back from the registers is 0x00. Figure 33. Detailed Block Diagram

Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP] I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). registered trademarks are the property of their respective owners.