AD9953YSVZ-REEL7

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400 MSPS, 14-Bit, 1.8 V CMOS Direct Digital Synthesizer Data Sheet AD9953 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2004–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

400 MSPS internal clock speed

Phase noise ≤ –120 dBc/Hz at 1 kHz offset (DAC output) Excellent dynamic performance >80 dB SFDR at 160 MHz (±100 kHz offset) A OUT Serial input/output (I/O) control

1.8 V power supply

Software and hardware controlled power-down 48-lead TQFP/EP package PLL REFCLK multiplier (4× to 20×) Internal oscillator, can be driven by a single crystal Phase modulation capability Multichip synchronization

APPLICATIONS

Agile VHF/UHF LO frequency synthesis FM chirp source for radar and scanning systems Nonlinear-shaped PSK/FSK modulator Test and measurement equipment FUNCTIONAL BLOCK DIAGRAM 1024  32 STATIC RAM COS(X) CONTROL REGISTERS OSCILLATOR/BUFFER SYNC ENABLE I/O UPDATE DAC_RSET DDS CORE PHASE OFFSET PHASE ACCUMULATOR Z–1 Z–1 IOUT IOUT OSK PWRDWNCTL REFCLK REFCLK CRYSTAL OUT I/O PORT PS<1:0> RAM DATA <31:18> RAM DATA FREQUENCY TUNING WORD RAM DATA DDS CLOCK DDS CLOCK PHASE ACCUMULATOR RESET DAC MUX SYSTEM CLOCK SYSTEM CLOCK SYNC_IN PHASE OFFSET WORD SYNC_CLK RESET TIMING AND CONTROL LOGIC 4–20 CLOCK MULTIPLIER ÷ 4 AD9953 141432 RAM ADDRESS RAM CONTROL 19 14 M U X M U X M U X 03357-0-001 Figure 1.

Rev. B | Page 2 of 32 TABLE OF CONTENTS

REVISION HISTORY

1/2017—Rev. A to Rev. B 5/2009—Rev. 0 to Rev. A 1/2004—Revision 0: Initial Version

Rev. B | Page 3 of 32 GENERAL DESCRIPTION The AD9953 is a direct digital synthesizer (DDS) featuring a 14-bit DAC operating up to 400 MSPS. The AD9953 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 MHz. The AD9953 includes an integrated 1024 × 32 static RAM to support flexible frequency sweep capability in several modes. The AD9953 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). The frequency tuning and control words are loaded into the AD9953 via a serial I/O port. The AD9953 is specified to operate over the extended industrial temperature range of –40°C to +105°C.

Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, RSET = 3.92 kΩ, External Reference Clock Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.

1 MHz to 10 MHz Analog Out 25°C 73 dBc

10 MHz to 40 MHz Analog Out 25°C 67 dBc

40 MHz to 80 MHz Analog Out 25°C 62 dBc

80 MHz to 120 MHz Analog Out 25°C 58 dBc

120 MHz to 160 MHz Analog Out 25°C 52 dBc

40 MHz Analog Out (±1 MHz) 25°C 87 dBc

40 MHz Analog Out (±250 kHz) 25°C 89 dBc

40 MHz Analog Out (±50 kHz) 25°C 91 dBc

40 MHz Analog Out (±10 kHz) 25°C 93 dBc

80 MHz Analog Out (±1 MHz) 25°C 85 dBc

80 MHz Analog Out (±250 kHz) 25°C 87 dBc

80 MHz Analog Out (±50 kHz) 25°C 89 dBc

80 MHz Analog Out (±10 kHz) 25°C 91 dBc

120 MHz Analog Out (±1 MHz) 25°C 83 dBc

120 MHz Analog Out (±250 kHz) 25°C 85 dBc

120 MHz Analog Out (±50 kHz) 25°C 87 dBc

120 MHz Analog Out (±10 kHz) 25°C 89 dBc

160 MHz Analog Out (±1 MHz) 25°C 81 dBc

160 MHz Analog Out (±250 kHz) 25°C 83 dBc

160 MHz Analog Out (±50 kHz) 25°C 85 dBc

160 MHz Analog Out (±10 kHz) 25°C 87 dBc

Rev. B | Page 5 of 32 Parameter Temp Min Typ Max Unit TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency FULL 25 Mbps Minimum Clock Pulse Width Low FULL 7 ns Minimum Clock Pulse Width High FULL 7 ns Maximum Clock Rise/Fall Time FULL 2 ns Minimum Data Setup Time DVDD_I/O = 3.3 V FULL 3 ns Minimum Data Setup Time DVDD_I/O = 1.8 V FULL 5 ns Minimum Data Hold Time FULL 0 ns Maximum Data Valid Time FULL 25 ns Wake-Up Time2 FULL 1 ms Minimum Reset Pulse Width High FULL 5 SYSCLK Cycles3 I/O UPDATE (PS0/PS1) to SYNC_CLK Setup Time DVDD_I/O = 3.3 V FULL 4 ns I/O UPDATE (PS0/PS1) to SYNC_CLK Setup Time DVDD_I/O = 1.8 V FULL 6 ns I/O UPDATE (PS0/PS1), SYNC_CLK Hold Time FULL 0 ns Latency I/O UPDATE (PS0/PS1) to Frequency Change Prop Delay 25°C 24 SYSCLK Cycles I/O UPDATE (PS0/PS1) to Phase Offset Change Prop Delay 25°C 24 SYSCLK Cycles I/O UPDATE (PS0/PS1) to Amplitude Change Prop Delay 25°C 16 SYSCLK Cycles CMOS LOGIC INPUTS Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 1.25 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 0.6 V Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 2.2 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 0.8 V Logic 1 Current 25°C 3 12 µA Logic 0 Current 25°C 12 µA Input Capacitance 25°C 2 pF CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V Logic 1 Voltage 25°C 1.35 V Logic 0 Voltage 25°C 0.4 V CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V Logic 1 Voltage 25°C 2.8 V Logic 0 Voltage 25°C 0.4 V POWER CONSUMPTION (AVDD = DVDD = 1.8 V) Single-Tone Mode 25°C 162 171 mW Rapid Power-Down Mode 25°C 150 160 mW Full-Sleep Mode 25°C 20 27 mW SYNCHRONIZATION FUNCTION4 Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V) 25°C 62.5 MHz Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V) 25°C 100 MHz SYNC_CLK Alignment Resolution5 25°C ±1 SYSCLK Cycles 1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise performance of the device. 2 Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions of the AD9953 section). The longest time required is for the reference clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values are used. 3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency, the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK frequency is the same as the external reference clock frequency. 4 SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set. 5 This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock edges are aligned, the synchronization function should not increase the skew between the two edges.

Figure 2. Equivalent Input and Output Circuits

Figure 3. 48-Lead TQFP/EP

Table 3. 48-Lead TQFP/EP must be set up and held around the SYNC_CLK output signal. 2, 34 DVDD I Digital Power Supply Pins (1.8 V). 3, 33, 42 DGND I Digital Power Ground Pins. AVDD I Analog Power Supply Pins (1.8 V). AGND I Analog Power Ground Pins. ended mode, REFCLK should be decoupled to AVDD with a 0.1 µF capacitor. 10 CRYSTAL OUT O Output of the Oscillator Section. oscillator section is bypassed. 20 IOUT O Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND. 21 IOUT O DAC Output. Should be biased through a resistor to AVDD, not AGND. 23 DACBP I DAC Biasline Decoupling Pin. A 0.1 μF capacitor to AGND is recommended. 35 PWRDWNCTL I Input Pin Used as an External Power-Down Control (see Table 10 for details). as described in the I/O port register map. returned low. If unused, ground this pin; do not allow this pin to float. operated as a 2-wire serial port, this pin is unused and can be left unconnected. 39 CS I This pin functions as an active low chip select that allows multiple devices to share the I/O bus. 40 SCLK I This pin functions as the serial data clock for I/O operations. 41 SDIO I/O When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input only. When operated as a 2-wire serial port, this pin is the bidirectional serial data pin. 43 DVDD_I/O I Digital Power Supply (for I/O Cells Only, 3.3 V). 45 SYNC_CLK O Clock Output Pin that Serves as a Synchronizer for External Hardware.

46 OSK I Input Pin Used to Control the Direction of the Shaped On-Off Keying Function when Programmed

to the I/O registers (sends an internal I/O UPDATE). be attached to AGND in any board layout.

below with fS defined as the frequency of SYSCLK. but the buffer memory for this bit is cleared (Logic 0). clear until the first I/O UPDATE is issued. The PLL allows multiplication of the REFCLK frequency. oscillator is buffered before it is delivered to the rest of the chip. CFR2<9> disables the oscillator output buffer. Table 4. Clock Input Modes of Operation

Rev. B | Page 13 of 32 DAC Output The AD9953 incorporates an integrated 14-bit current output DAC. Unlike most DACs, this output is referenced to AVDD, not AGND. Two complementary outputs provide a combined full-scale output current (IOUT). Differential outputs reduce the amount of common-mode noise that might be present at the DAC output, offering the advantage of an increased signal-to-noise ratio. The full-scale current is controlled by an external resistor (RSET) connected between the DAC_RSET pin and the DAC ground (AGND_DAC). The full-scale current is proportional to the resistor value as follows: OUTSET IR /19.39= The maximum full-scale output current of the combined DAC outputs is 15 mA, but limiting the output to 10 mA provides the best spurious-free dynamic range (SFDR) performance. The DAC output compliance range is AVDD + 0.5 V to AVDD – 0 . 5 V. Voltages developed beyond this range will cause excessive DAC distortion and could potentially damage the DAC output circuitry. Proper attention should be paid to the load termination to keep the output voltage within this compliance range. Serial IO Port The AD9953 serial port is a flexible, synchronous serial communications port that allows easy interface to many industry- standard microcontrollers and microprocessors. The serial I/O port is compatible with most synchronous transfer formats, including both the Motorola 6905/11 SPI® and Intel® 8051 SSR protocols. The interface allows read/write access to all registers that configure the AD9953. MSB first or LSB first transfer formats are supported. The AD9953’ s serial interface port can be configured as a single pin I/O (SDIO), which allows a 2-wire interface or two unidirectional pins for in/out (SDIO/SDO), which in turn enables a 3-wire interface. Two optional pins, IOSYNC and CS, enable greater flexibility for system design in the AD9953. Register Map and Descriptions The register map is listed in Table 5.

Table 5. Register Map

Rev. B | Page 15 of 32 Register Name (Serial Address) Bit Range (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 Default Value OR Profile RAM Segment Control Word No. 0 (RSCW0) (0x07) <7:0> RAM Segment 0 Mode Control <2:0> No Dwell Active RAM Segment 0 Beginning Address <9:6> PS0 = 0 PS1 = 0 <15:8> RAM Segment 0 Beginning Address <5:0> RAM Segment 0 Final Address <9:8> PS0 = 0 PS1 = 0 <23:16> RAM Segment 0 Final Address <7:0> PS0 = 0 PS1 = 0 <31:24> RAM Segment 0 Address Ramp Rate <15:8> PS0 = 0 PS1 = 0 <39:32> RAM Segment 0 Address Ramp Rate <7:0> PS0 = 0 PS1 = 0 RAM Segment Control Word No. 1 (RSCW1) (0x08) <7:0> RAM Segment 1 Mode Control <2:0> No Dwell Active RAM Segment 1 Beginning Address <9:6> PS0 = 1 PS1 = 0 <15:8> RAM Segment 1 Beginning Address <5:0> RAM Segment 1 Final Address <9:8> PS0 = 1 PS1 = 0 <23:16> RAM Segment 1 Final Address <7:0> PS0 = 1 PS1 = 0 <31:24> RAM Segment 1 Address Ramp Rate <15:8> PS0 = 1 PS1 = 0 <39:32> RAM Segment 1 Address Ramp Rate <7:0> PS0 = 1 PS1 = 0 RAM Segment Control Word No. 2 (RSCW2) (0x09) <7:0> RAM Segment 2 Mode Control <2:0> No Dwell Active RAM Segment 2 Beginning Address <9:6> PS0 = 0 PS1 = 1 <15:8> RAM Segment 2 Beginning Address <5:0> RAM Segment 2 Final Address <9:8> PS0 = 0 PS1 = 1 <23:16> RAM Segment 2 Final Address <7:0> PS0 = 0 PS1 = 1 <31:24> RAM Segment 2 Address Ramp Rate <15:8> PS0 = 0 PS1 = 1 <39:32> RAM Segment 2 Address Ramp Rate <7:0> PS0 = 0 PS1 = 1 RAM Segment Control Word No. 3 (RSCW3) (0x0A) <7:0> RAM Segment 3 Mode Control <2:0> No Dwell Active RAM Segment 3 Beginning Address <9:6> PS0 = 1 PS1 = 1 <15:8> RAM Segment 3 Beginning Address <5:0> RAM Segment 3 Final Address <9:8> PS0 = 1 PS1 = 1 <23:16> RAM Segment 3 Final Address <7:0> PS0 = 1 PS1 = 1 <31:24> RAM Segment 3 Address Ramp Rate <15:8> PS0 = 1 PS1 = 1 <39:32> RAM Segment 3 Address Ramp Rate <7:0> PS0 = 1 PS1 = 1 RAM (0x0B) RAM [1023:0] <31:0> (Read Instructions: Write Out RAM Register Data)

Rev. B | Page 16 of 32 Control Register Bit Descriptions Control Function Register. No. 1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9953. The functionality of each bit is below. CFR1<31>: RAM Enable Bit CFR1<31> = 0 (default). The RAM is powered down to conserve power. Single-tone mode of operation is active. CFR1<31> = 1. If CFR1<31> is active, the RAM is enabled for operation. Access control for normal operation is controlled via the mode control bits of the RSCW for the current profile. CFR1<30>: RAM Destination Bit CFR1<30> = 0 (default). If CFR1<31> is active, a Logic 0 on the RAM destination bit (CFR1<30> = 0) configures the AD9953 such that the RAM output drives the phase accumulator (i.e., the frequency tuning word). If CFR1<31> is inactive, CFR1<30> is a Don’t Care. CFR1<30> = 1. If CFR1<31> is active, a Logic 1 on the RAM destination bit (CFR1<30> = 1) configures the AD9953 such that the RAM output drives the phase-offset adder (i.e., sets the phase offset of the DDS core). CFR1<29:27>: Not Used CFR1<26>: Amplitude Ramp Rate Load Control Bit CFR1<26> = 0 (default). The amplitude ramp rate timer is loaded only upon timeout (timer == 1) and is not loaded due to an I/O UPDATE input signal. CFR1<26> = 1. The amplitude ramp rate timer is loaded upon timeout (timer == 1) or at the time of an I/O UPDATE input signal. CFR1<25>: Shaped On-Off Keying Enable Bit CFR1<25> = 0 (default). Shaped on-off keying is bypassed. CFR1<25> = 1. Shaped on-off keying is enabled. When enabled, CFR1<24> controls the mode of operation for this function. CFR1<24>: Auto Shaped On-Off Keying Enable Bit (Only Valid when CFR1<25> Is Active High) CFR1<24> = 0 (default). When CFR1<25> is active, a Logic 0 on CFR1<24> enables the manual shaped on-off keying operation. Each amplitude sample sent to the DAC is multiplied by the amplitude scale factor. See the Shaped On-Off Keying section for details. CFR1<24> = 1. When CFR1<25> is active, a Logic 1 on CFR1<24> enables the auto shaped on-off keying operation. Toggling the OSK pin high will cause the output scalar to ramp up from zero scale to the amplitude scale factor at a rate deter- mined by the amplitude ramp rate. Toggling the OSK pin low will cause the output to ramp down from the amplitude scale factor to zero scale at the amplitude ramp rate. See the Shaped On-Off Keying section for details. CFR1<23>: Automatic Synchronization Enable Bit CFR1<23> = 0 (default). The automatic synchronization feature of multiple AD9953s is inactive. CFR1<23> = 1. The automatic synchronization feature of multiple AD9953s is active. The device will synchronize its internal synchronization clock (SYNC_CLK) to align to the signal present on the SYNC_IN input. See the Synchronizing Multiple AD9953s section for details. CFR1<22>: Software Manual Synchronization of Multiple AD9953s CFR1<22> = 0 (default). The manual synchronization feature is inactive. CFR1<22> = 1. The software controlled manual synchroniza- tion feature is executed. The SYNC_CLK rising edge is advanced by one SYNC_CLK cycle and this bit is cleared. To advance the rising edge multiple times, this bit needs to be set for each advance. See the Synchronizing Multiple AD9953s section for details. CFR1<21:14>: Not Used CFR1<13>: Auto-Clear Phase Accumulator Bit CFR1<13> = 0 (default). The current state of the phase accumula- tor remains unchanged when the frequency tuning word is applied. CFR1<13> = 1. This bit automatically synchronously clears (loads 0s into) the phase accumulator for one cycle upon reception of an I/O UPDATE signal. CFR1<12>: Sine/Cosine Select Bit CFR1<12> = 0 (default). The angle-to-amplitude conversion logic employs a COSINE function. CFR1<12> = 1. The angle-to-amplitude conversion logic employs a SINE function. CFR1<11>: Not Used CFR1<10>: Clear Phase Accumulator CFR1<10> = 0 (default). The phase accumulator functions as normal. CFR1<10> = 1. The phase accumulator memory elements are cleared and held clear until this bit is cleared.

Rev. B | Page 17 of 32 CFR1<9>: SDIO Input Only CFR1<9> = 0 (default). The SDIO pin has bidirectional operation (2-wire serial programming mode). CFR1<9> = 1. The serial data I/O pin (SDIO) is configured as an input only pin (3-wire serial programming mode). CFR1<8>: LSB First CFR1<8> = 0 (default). MSB first format is active. CFR1<8> = 1. The serial interface accepts serial data in LSB first format. CFR1<7>: Digital Power-Down Bit CFR1<7> = 0 (default). All digital functions and clocks are active. CFR1<7> = 1. All non-IO digital functionality is suspended, lowering the power significantly. CFR1<6>: Not Used CFR1<5>: DAC Power-Down Bit CFR1<5> = 0 (default). The DAC is enabled for operation. CFR1<5> = 1. The DAC is disabled and is in its lowest power dissipation state. CFR1<4>: Clock Input Power-Down Bit CFR1<4> = 0 (default). The clock input circuitry is enabled for operation. CFR1<4> = 1. The clock input circuitry is disabled and the device is in its lowest power dissipation state. CFR1<3>: External Power-Down Mode CFR1<3> = 0 (default). The external power-down mode selected is the rapid recovery power-down mode. In this mode, when the PWRDWNCTL input pin is high, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered down. CFR1<3> = 1. The external power-down mode selected is the full power-down mode. In this mode, when the PWRDWNCTL input pin is high, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up. CFR1<2>: Not Used CFR1<1>: SYNC_CLK Disable Bit CFR1<1> = 0 (default). The SYNC_CLK pin is active. CFR1<1> = 1. The SYNC_CLK pin assumes a static Logic 0 state to keep noise generated by the digital circuitry at a minimum. However, the synchronization circuitry remains active (internally) to maintain normal device timing. CFR1<0>: Not Used, Leave at 0 Control Function Register No. 2 (CFR2) The CFR2 is used to control the various functions, features, and modes of the AD9953, primarily related to the analog sections of the chip. CFR2<23:12>: Not Used CFR2<11>: High Speed Sync Enable Bit CFR2<11> = 0 (default). The high speed sync enhancement is off. CFR2<11> = 1. The high speed sync enhancement is on. This bit should be set when attempting to use the auto- synchronization feature for SYNC_CLK inputs beyond 50 MHz, (200 MSPS SYSCLK). See the Synchronizing Multiple AD9953s section for details. CFR2<10>: Hardware Manual Sync Enable Bit CFR2<10> = 0 (default). The hardware manual sync function is off. CFR2<10> = 1. The hardware manual sync function is enabled. While this bit is set, a rising edge on the SYNC_IN pin will cause the device to advance the SYNC_CLK rising edge by one REFCLK cycle. Unlike the software manual sync enable bit, this bit does not self clear. Once the hardware manual sync mode is enabled, it will stay enabled until this bit is cleared. See the Synchronizing Multiple AD9953s section for details. CFR2<9>: CRYSTAL OUT Enable Bit CFR2<9> = 0 (default). The CRYSTAL OUT pin is inactive. CFR2<9> = 1. The CRYSTAL OUT pin is active. When active, the crystal oscillator circuitry output drives the CRYSTAL OUT pin, which can be connected to other devices to produce a reference frequency. The oscillator will respond to crystals in the range of 20 MHz to 30 MHz. CFR2<8>: Not Used CFR2<7:3>: Reference Clock Multiplier Control Bits This 5-bit word controls the multiplier value out of the clock- multiplier (PLL) block. Valid values are decimal 4 to 20 (0x04 to 0x14). Values entered outside this range will bypass the clock multiplier. See the Phase-Locked Loop (PLL) section for details. CFR2<2>: VCO Range Control Bit This bit is used to control the range setting on the VCO. When CFR2<2> == 0 (default), the VCO operates in a range of 100 MHz to 250 MHz. When CFR2<2> == 1, the VCO operates in a range of 250 MHz to 400 MHz.

Rev. B | Page 18 of 32 CFR2<1:0>: Charge Pump Current Control Bits These bits are used to control the current setting on the charge pump. The default setting, CFR2<1:0>, sets the charge pump current to the default value of 75 µA. For each bit added (01, 10, 11), 25 µA of current is added to the charge pump current: 100 µA, 125 µA, and 150 µA. Other Register Descriptions Amplitude Scale Factor (ASF) The ASF register stores the 2-bit auto ramp rate speed value and the 14-bit amplitude scale factor used in the output shaped keying (OSK) operation. In auto OSK operation, ASF <15:14> tells the OSK block how many amplitude steps to take for each increment or decrement. For ASF<15:14> = {00, 01, 10, 11}, the increment/decrement is set to {1, 2, 4, 8}, respectively. ASF <13:0> sets the maximum value achievable by the OSK internal multiplier. In manual OSK mode, ASF<15:14> has no effect. ASF <13:0> provides the output scale factor directly. If the OSK enable bit is cleared, CFR1<25> = 0, this register has no effect on device operation. Amplitude Ramp Rate (ARR) The ARR register stores the 8-bit amplitude ramp rate used in the auto OSK mode. This register programs the rate at which the amplitude scale factor counter increments or decrements. If the OSK is set to manual mode, or if OSK enable is cleared, this register has no effect on device operation. Fre qu enc y Tun ing Wor d 0 (F TW0) The frequency tuning word is a 32-bit register that controls the rate of accumulation in the phase accumulator of the DDS core. Its specific role is dependent on the device mode of operation. Phase Offset Word (POW) The phase offset word is a 14-bit register that stores a phase offset value. This offset value is added to the output of the phase accumulator to offset the current phase of the output signal. The exact value of phase offset is given by the following formula: °×  =Φ 360214 POW RAM Segment Control Words (RSCW0, RSCW1, RSCW2, and RSCW3) When the linear sweep enable bit CFR1<21> is clear, Registers 0x07, 0x08, 0x09, and 0x0A act as the RAM segment control words for each of the RAM segments. Each of the RAM segment control words is comprised of a RAM segment address ramp rate, a final address value, a beginning address value, a RAM segment mode control, and a no-dwell bit. RAM Segment Address Ramp Rate, RSCW<39:24> For RAM modes that step through address values, such as ramping, this 16-bit word defines the number of SYNC_CLK cycles the RAM controller dwells at each address. A value of 0 is invalid. Any other value from 1 to 65535 may be used. RAM Segment Final Address RSCW<9:8>, RSCW<23:16> This discontinuous 10-bit sequence defines the final address value for the given RAM segment. The order in which the bits are listed is the order in which the bits must be written. RSCW<23>, even though during the write operation is more significant than RSCW<9>, is only the third MSB of the final address value. RSCW<9>, even though it comes later in the RSCW than RSCW<23>, is the MSB of the final address value. RAM Segment Beginning Address RSCW<3:0>, <15:10> This discontinuous 10-bit sequence defines the final address value for the given RAM segment. The order in which the bits are listed is the order in which the bits must be written. RSCW<15>, even though during the write operation is more significant than RSCW<3>, is only the fifth MSB of the final address value. RSCW<3>, even though it comes later in the RSCW than RSCW<15>, is the MSB of the final address value. RAM Segment Mode Control RSCW<7:5> This 3-bit sequence determines the RAM segment’s mode of operation. There are only five possible RAM modes, so only values of 0 to 5 are valid. See Table 6 to determine the bit combination for various RAM modes. RAM Segment No-Dwell Bit RSCW<4> This bit sets the no-dwell feature of sweeping profiles. In profiles that sweep from a defined beginning to a defined end, the RAM controller can either dwell at the final address until the next profile is selected or, when this bit is set, the RAM controller will return to the beginning address and dwell there until the next profile is selected. RAM The AD9953 incorporates a 1024 × 32 block of SRAM. The RAM is a bidirectional single port. Both read and write operations from and to the RAM are valid, but they cannot occur simultaneously. Write operations from the serial I/O port have precedence, and if an attempt to write to RAM is made during a read operation, the read operation will be halted. The RAM is controlled in multiple ways, dictated by the modes of operation described in the RAM Segment Control Word <7:5> as well as data in the control function register. Read/write control for the RAM will be described for each mode supported. When the RAM enable bit (CFR1<31>) is set, the RAM output optionally drives the input to the phase accumulator or the phase offset adder, depending on the state of the RAM destina- tion bit (CFR1<30>). If CFR1<30> is a Logic 1, the RAM output is connected to the phase offset adder and supplies the phase offset control word(s) for the device. When CFR1<30> is Logic 0 (default condition), the RAM output is connected to the

Rev. B | Page 19 of 32 input of the phase accumulator and supplies the frequency tuning word(s) for the device. When the RAM output drives the phase accumulator, the phase offset word (POW , Address 0x05) drives the phase-offset adder. Similarly, when the RAM output drives the phase offset adder, the frequency tuning word (FTW , Address 0x04) drives the phase accumulator. When CFR1<31> is Logic 0, the RAM is inactive unless being written to via the serial port. The power-up state of the AD9953 is the single-tone mode, in which the RAM enable bit is inactive. The RAM is segmented into four unique slices controlled by the Profile<1:0> input pins. All RAM writes/reads, unless otherwise specified, are controlled by the Profile<1:0> input pins and the respective RAM segment control word. The RAM can be written to during normal operation, but any I/O operation that commands the RAM to be written immediately suspends read operation from the RAM, causing the current mode of operation to be nonfunctional. This excludes single-tone mode, as the RAM is not read in this mode. Writing the RAM is accomplished as follows. After configuring the desired RAM segment control words, the desired RAM segment must be selected via the profile select pins PS<1:0>. During the instruction byte, write the address for the RAM, 0x0B. The serial port and RAM controller will work in conjunction to determine the width of the profile and the serial port will accept the defined number of 32-bit words sequentially from the beginning address to the ending address. Consider the following example:

• The RAM Segment Control Word 1 lists the beginning RAM address at 256 and the ending address at 511.
• PS0 = 1 and PS1 = 0.
• The instruction byte is 10001001. The RAM controller would configure the serial port to expect 256 32-bit words. The first 32 bits would be parsed as a word and sent to RAM Address 256. The next 32 bits would be parsed and sent to 257, and so forth, all the way through until the 256 word was sent (grand total of 8,192 data bits in this operation). MODES OF OPERATION Single-Tone Mode In single-tone mode, the DDS core uses a single tuning word. Whatever value is stored in FTW0 is supplied to the phase accumulator. This value can only be changed manually, which is done by writing a new value to FTW0 and by issuing an I/O UPDATE. Phase adjustment is possible through the phase offset register. RAM Controlled Modes of Operation Direct Switch Mode Direct switch mode enables FSK or PSK modulation. The AD9953 is programmed for direct switch mode by writing the RAM enable bit true and programming the RAM segment mode control bits of each desired profile to Logic 000(b). This mode simply reads the RAM contents at the RAM segment beginning address for the current profile. No address ramping is enabled in direct switch mode. To perform 4-tone FSK, the user programs each RAM segment control word for direct switch mode and a unique beginning address value. In addition, the RAM enable bit is written true, which enables the RAM, and the RAM destination bit is written false, setting the RAM output to be the frequency tuning word. The Profile<1:0> inputs are the 4-tone FSK data inputs. When the profile is changed, the frequency tuning word stored in the new profile is loaded into the phase accumulator and is used to increment the currently stored value in a phase continuous fashion. The phase offset word drives the phase-offset adder. Two-tone FSK is accomplished by using only one profile pin for data. Programming the AD9953 for PSK modulation is similar to FSK except the RAM destination bit is set to a Logic 1, enabling the RAM output to drive the phase offset adder. The FTW0 drives the input to the phase accumulator. Toggling the profile pins changes (modulates) the current phase value. The upper 14 bits of the RAM drive the phase adder (<31:18>). Bits <17:0> of the RAM output are unused when the RAM destination bit is set. The no-dwell bit is a Don’t Care in direct switch mode. Ramp-Up Mode Ramp-up mode, in conjunction with the segmented RAM capability, allows up to four different sweep profiles to be programmed into the AD9953. The AD9953 is programmed for ramp-up mode by writing the RAM enable bit true and programming the RAM mode control bits of each profile to be used to Logic 001(b). As in all modes that enable the memory, the RAM destination bit controls whether the RAM output drives the phase accumulator or the phase offset adder. Upon starting a sweep (via an I/O UPDATE or change in profile bits), the RAM address generator loads the RAM segment beginning address bits of the current RSCW , driving the RAM output from this address, and the ramp rate timer loads the RAM segment address ramp rate bits. When the ramp rate timer finishes a cycle, the RAM address generator increments to the next address and the timer reloads the ramp rate bits and begins a new countdown cycle. This sequence continues until the RAM address generator has incremented to an address equal to the RAM segment final address bits of the current RSCW .

Rev. B | Page 20 of 32 If the no-dwell bit is clear when the RAM address generator equals the final address, the generator stops incrementing as the terminal frequency has been reached. The sweep is complete and does not restart until an I/O UPDATE or change in profile is detected to enable another sweep from the beginning to the final RAM address as described above. If the no-dwell bit is set when the RAM address generator equals the final address, after the next ramp rate timer cycle the phase accumulator is cleared. The phase accumulator remains cleared until another sweep is initiated via an I/O UPDATE input or change in profile. Another application for ramp-up mode is nonsymmetrical FSK modulation. With the RAM configured for two segments, using the Profile<0> bit as the data input allows nonsymmetrical ramped FSK. Bidirectional Ramp Mode Bidirectional ramp mode allows the AD9953 to offer a symme- trical sweep between two frequencies using the Profile<0> signal as the control input. The AD9953 is programmed for bidirectional ramp mode by writing the RAM enable bit true and the RAM mode control bits of RSCW0 to Logic 010(b). In bidirectional ramp mode, the Profile<1> input is ignored and the Profile<0> input is the ramp direction indicator. In this mode, the memory is not segmented and uses only a single beginning and final address. The address registers that affect the control of the RAM are located in the RSCW associated with Profile 0. Upon entering this mode (via an I/O UPDATE or changing Profile<0>), the RAM address generator loads the RAM seg- ment beginning address bits of RSCW0 and the ramp rate timer loads the RAM segment address ramp rate bits. The RAM drives data from the beginning address, and the ramp rate timer begins to count down to 1. While operating in this mode, tog- gling the Profile<0> pin does not cause the device to generate an internal I/O UPDATE. When the Profile<0> pin is acting as the ramp direction indicator, any transfer of data from the I/O buffers to the internal registers can only be initiated by a rising edge on the I/O UPDATE pin. RAM address control now is a function of the Profile<0> input. When the Profile<0> bit is a Logic 1, the RAM address genera- tor increments to the next address when the ramp rate timer completes a cycle (and reloads to start the timer again). As in the ramp-up mode, this sequence continues until the RAM address generator has incremented to an address equal to the final address as long as the Profile<0> input remains high. If the Profile<0> input goes low, the RAM address generator imme- diately decrements and the ramp rate timer is reloaded. The RAM address generator will continue to decrement at the ramp rate period until the RAM address is equal to the beginning address as long as the Profile<0> input remains low. The sequence of ramping up and down is controlled via the Profile<0> input signal for as long as the part is programmed into this mode. The no-dwell bit is a Don’t Care in this mode as is all data in the RAM segment control words associated with Profiles 1, 2, and 3. Only the information in the RAM segment control word for Profile 0 is used to control the RAM in the bidirectional ramp mode. Continuous Bidirectional Ramp Mode Continuous bidirectional ramp mode allows the AD9953 to offer an automatic symmetrical sweep between two frequencies. The AD9953 is programmed for continuous bidirectional ramp mode by writing the RAM enable bit true and the RAM mode control bits of each profile to be used to Logic 011(b). Upon entering this mode (via an I/O UPDATE or changing Profile<1:0>), the RAM address generator loads the RAM segment beginning address bits of the current RSCW and the ramp rate timer loads the RAM segment address ramp rate bits. The RAM drives data from the beginning address, and the ramp rate timer begins to count down to 1. When the ramp rate timer completes a cycle, the RAM address generator increments to the next address, and the timer reloads the ramp rate bits and continues counting down. This sequence continues until the RAM address generator has incremented to an address equal to the RAM segment final address bits of the current RSCW . Upon reaching this terminal address, the RAM address generator will decrement in value at the ramp rate until it reaches the RAM segment beginning address. Upon reaching the beginning address, the entire sequence repeats. The entire sequence repeats for as long as the part is programmed for this mode. The no-dwell bit is a Don’t Care in this mode. In general, this mode is identical in control to the bidirectional ramp mode except the ramp up and down is automatic (no external control via the Profile<0> input) and switching profiles is valid. Once in this mode, the address generator ramps from the beginning address to the final address, then back to the beginning address at the rate programmed into the ramp rate register. This mode enables generation of an automatic saw tooth sweep characteristic. Continuous Recirculate Mode Continuous recirculate mode allows the AD9953 to offer an automatic, continuous unidirectional sweep between two frequencies. The AD9953 is programmed for continuous recirculate mode by writing the RAM enable bit true and the RAM mode control bits of each profile to be used to Logic 100(b). Upon entering this mode (via an I/O UPDATE or changing Profile<1:0>), the RAM address generator loads the RAM segment beginning address bits of the current RSCW and the ramp rate timer loads the RAM segment address ramp rate bits. The RAM drives data from the beginning address, and the ramp rate timer begins to count down to 1. When the ramp rate timer completes a cycle, the RAM address generator increments to the

mode. The no-dwell bit is a Don’t Care in this mode.

1. The user must ensure that the beginning address is lower
2. Changing profiles or issuing an I/O UPDATE automatically

terminates the current sweep and starts the next sweep.

1. Setting the RAM destination bit true such that the RAM

sweep operation is also available. Table 6. RAM Modes of Operation

000 Direct Switch No Sweeping, Profiles

001 Ramp Up Sweeping, Profiles Valid,

010 Bidirectional

011 Continuous

100 Continuous

Table 7. When any of the CFR1<29:27> bits are active, the is no internal profile control for linear sweeping operations. memory contents for the current profile. Table 7. Internal Profile Control

000 Internal Control Inactive

001 Internal Control Active, Single Burst, Activate

010 Internal Control Active, Single Burst, Activate

011 Internal Control Active, Single Burst, Activate

100 Internal Control Active, Continuous, Activate

101 Internal Control Active, Continuous, Activate

110 Internal Control Active, Continuous, Activate

111 Invalid

sequence is over and the composite sweep has completed. Issuing another I/O UPDATE restarts the burst process.

provides the user with two different methods of phase control. rate at which phase modulation can be performed. phase accumulator is allowed to operate. impact of short, abrupt bursts of data. Auto and manual shaped on-off keying modes are supported. scale factor value into the amplitude scale factor (ASF) register. by clearing the OSK enable bit (CFR1<25> = 0). condition is shaped on-off keying disabled (CFR1<25> = 0). Figure 20 shows the block diagram of the OSK circuitry. multiplies the DDS core output by 16383 (decimal). factor per the ASF<15:14> bits. Table 8. Auto-Scale Factor Internal Step Size

value of the ASFR every time the counter reaches 1 (decimal). The first method of loading is by changing the OSK input pin. (CFR1<26>) is set and an I/O UPDATE is issued. Figure 20. On-Off Shaped Keying Block Diagram

CFR1<25> to a Logic 1 and writing CFR1<24> to a Logic 0. content of the ASFR becomes the scale factor for the data path. an I/O UPDATE timing cycle and synchronization.

1. The I/O UPDATE signal is edge detected to generate a
2. The I/O UPDATE pin is set up and held around the rising

Figure 21. I/O Synchronization Block Diagram

THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B. Figure 22. I/O Synchronization Timing Diagram The AD9953 allows easy synchronization of multiple AD9953s. be set to 3.3 V for all devices that are to be synchronized. AVDD and DVDD should be left at 1.8 V . SYNC_IN input, which is the SYNC_CLK of the master device. enable bit should be set (CFR2<11> = 1). multiple times, this bit will need to be set multiple times. cycle until this enable bit is cleared (CFR2<10> = 0). should be connected to the REFCLK input of the other AD9953. to using it to drive any loads.

Rev. B | Page 27 of 32 INSTRUCTION BYTE The instruction byte contains the following information: Table 9. MSB D6 D5 D4 D3 D2 D1 LSB R/W X X A4 A3 A2 A1 A0 R/W—Bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. Logic High indicates read operation. Logic 0 indicates a write operation. X, X—Bits 6 and 5 of the instruction byte are Don’t Care. A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. SERIAL INTERFACE PORT PIN DESCRIPTION SCLK—Serial Clock. The serial clock pin is used to synchronize data to and from the AD9953 and to run the internal state machines. SCLK maximum frequency is 25 MHz. CSB—Chip Select Bar. CSB is active low input that allows more than one device on the same serial communications line. The SDO and SDIO pins will go to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until CS is reactivated low. Chip select can be tied low in systems that maintain control of SCLK. SDIO—Serial Data I/O. Data is always written into the AD9953 on this pin. However, this pin can be used as a bidirectional data line. Bit 9 of Register Address 0x00 controls the configuration of this pin. The default is Logic 0, which configures the SDIO pin as bidirectional. SDO—Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9953 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. IOSYNC—It synchronizes the I/O port state machines without affecting the addressable register’s contents. An active high input on the IOSYNC pin causes the current communication cycle to abort. After IOSYNC returns low (Logic 0), another communication cycle may begin, starting with the instruction byte write. MSB/LSB TRANSFERS The AD9953 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the Control Register 0x00 <8> bit. The default value of Control Register 0x00 <8> is low (MSB first). When Control Register 0x00 <8> is set high, the AD9953 serial port is in LSB first format. The instruction byte must be written in the format indicated by Control Register 0x00 <8>. If the AD9953 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. For MSB first operation, the serial port controller will generate the most significant byte (of the specified register) address first followed by the next lesser significant byte addresses until the I/O operation is complete. All data written to (read from) the AD9953 must be (will be) in MSB first order. If the LSB mode is active, the serial port controller will generate the least signifi- cant byte address first followed by the next greater significant byte addresses until the I/O operation is complete. All data written to (read from) the AD9953 must be (will be) in LSB first order. Example Operation To write the amplitude scale factor register in MSB first format, apply an instruction byte of 0x02 [serial address is 00010(b)]. From this instruction, the internal controller will know to use the first byte as the most significant byte. The first two bits will be recorded as the auto ramp rate speed control bits, and the next six bits will be the most significant bits of the amplitude scale factor. The second byte will be applied as the eight less significant bits of the amplitude scale factor ASF<7:0>. To write the amplitude scale factor register in LSB first format, assuming the control register has already been set for LSB first format, apply an instruction byte of 0x40. From this instruction, the internal controller will know to use the first byte as the least significant byte of the amplitude scale factor ASF<0:7>. The second byte will be split into the first six bits ASF<8:13> and the last two will provide the auto ramp rate speed control bits ARRSC<0:1>. Power-Down Functions of the AD9953 The AD9953 supports an externally controlled or hardware power-down feature as well as the more common software programmable power-down bits found in previous ADI DDS products. The software control power-down allows the DAC, PLL, input clock circuitry, and digital logic to be individually powered down via unique control bits (CFR1<7:4>). With the exception of CFR1<6>, these bits are not active when the externally controlled power-down pin (PWRDWNCTL) is high. External power-down control is supported on the AD9953 via the PWRDWNCTL input pin. When the PWRDWNCTL input pin is high, the AD9953 will enter a power-down mode based on the CFR1<3> bit. When the PWRDWNCTL input pin is low, the external power-down control is inactive.

high, the AD9953 is put into a fast recovery power-down mode. clock input circuitry is not powered down. pin is high, the AD9953 is put into the full power-down mode. the active or power-up mode. Table 10. Power-Down Control Functions

0.50 BSC

0.08 MAX

Figure 30. 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

Rev. B | Page 31 of 32 NOTES

Rev. B | Page 32 of 32 NOTES ©2004–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03374-0-1/17(B)