AD9951YSVZ

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 28

Technical content

400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer AD9951 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.

FEATURES

400 MSPS internal clock speed

Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output) Excellent dynamic performance >80 dB SFDR @ 160 MHz (±100 kHz offset) A OUT Serial I/O control

1.8 V power supply

Software and hardware controlled power-down 48-lead TQFP/EP package Support for 5 V input levels on most digital inputs PLL REFCLK multiplier (4× to 20×) Internal oscillator, can be driven by a single crystal Phase modulation capability Multichip synchronization

APPLICATIONS

Agile LO frequency synthesis Programmable clock generators Test and measurement equipment Acousto-optic device drivers FUNCTIONAL BLOCK DIAGRAM COS(X) CONTROL REGISTERS OSCILLATOR/BUFFER SYNC ENABLE I/O UPDATE DAC_RSET DDS CORE PHASE OFFSET PHASE ACCUMULATOR Z–1 Z–1 IOUT IOUT OSK PWRDWNCTL REFCLK REFCLK CRYSTAL OUT I/O PORT DDS CLOCK FREQUENCY TUNING WORD CLEAR PHASE ACCUMULATOR AMPLITUDE SCALE FACTOR DAC SYSTEM CLOCK SYSTEM CLOCK SYNC_IN SYNC_CLK RESET TIMING AND CONTROL LOGIC 4× TO 20× CLOCK MULTIPLIER ÷ 4 AD9951 32 14 19 14 M U X M U X 03359-001 Figure 1.

Rev. A | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

5/09—Rev. 0 to Rev. A 11/03—Revision 0: Initial Version

Rev. A | Page 3 of 28 GENERAL DESCRIPTION The AD9951 is a direct digital synthesizer (DDS) featuring a 14-bit DAC operating up to 400 MSPS. The AD9951 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 MHz. The AD9951 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). The frequency tuning and control words are loaded into the AD9951 via a serial I/O port. The AD9951 is specified to operate over the extended industrial temperature range of –40°C to +105°C.

Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, RSET = 3.92 kΩ, External Reference Clock Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.

1 MHz to 10 MHz Analog Out 25°C 73 dBc

10 MHz to 40 MHz Analog Out 25°C 67 dBc

40 MHz to 80 MHz Analog Out 25°C 62 dBc

80 MHz to 120 MHz Analog Out 25°C 58 dBc

120 MHz to 160 MHz Analog Out 25°C 52 dBc

40 MHz Analog Out (±1 MHz) 25°C 87 dBc

40 MHz Analog Out (±250 kHz) 25°C 89 dBc

40 MHz Analog Out (±50 kHz) 25°C 91 dBc

40 MHz Analog Out (±10 kHz) 25°C 93 dBc

80 MHz Analog Out (±1 MHz) 25°C 85 dBc

80 MHz Analog Out (±250 kHz) 25°C 87 dBc

80 MHz Analog Out (±50 kHz) 25°C 89 dBc

80 MHz Analog Out (±10 kHz) 25°C 91 dBc

120 MHz Analog Out (±1 MHz) 25°C 83 dBc

120 MHz Analog Out (±250 kHz) 25°C 85 dBc

120 MHz Analog Out (±50 kHz) 25°C 87 dBc

120 MHz Analog Out (±10 kHz) 25°C 89 dBc

160 MHz Analog Out (±1 MHz) 25°C 81 dBc

160 MHz Analog Out (±250 kHz) 25°C 83 dBc

160 MHz Analog Out (±50 kHz) 25°C 85 dBc

160 MHz Analog Out (±10 kHz) 25°C 87 dBc

Rev. A | Page 5 of 28 Parameter Temp Min Typ Max Unit TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency FULL 25 Mbps Minimum Clock Pulse Width Low FULL 7 ns Minimum Clock Pulse Width High FULL 7 ns Maximum Clock Rise/Fall Time FULL 2 ns Minimum Data Setup Time DVDD_I/O = 3.3 V FULL 3 ns Minimum Data Setup Time DVDD_I/O = 1.8 V FULL 5 ns Minimum Data Hold Time FULL 0 ns Maximum Data Valid Time FULL 25 ns Wake-Up Time2 FULL 1 ms Minimum Reset Pulse Width High FULL 5 SYSCLK Cycles3 I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V FULL 4 ns I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V FULL 6 ns I/O UPDATE, SYNC_CLK Hold Time FULL 0 ns Latency I/O UPDATE to Frequency Change Prop Delay 25°C 24 SYSCLK Cycles I/O UPDATE to Phase Offset Change Prop Delay 25°C 24 SYSCLK Cycles I/O UPDATE to Amplitude Change Prop Delay 25°C 16 SYSCLK Cycles CMOS LOGIC INPUTS Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 1.25 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 0.6 V Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 2.2 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 0.8 V Logic 1 Current 25°C 3 12 µA Logic 0 Current 25°C 12 µA Input Capacitance 25°C 2 pF CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V Logic 1 Voltage 25°C 1.35 V Logic 0 Voltage 25°C 0.4 V CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V Logic 1 Voltage 25°C 2.8 V Logic 0 Voltage 25°C 0.4 V POWER CONSUMPTION (AVDD = DVDD = 1.8 V) Single-Tone Mode 25°C 162 171 mW Rapid Power-Down Mode 25°C 150 160 mW Full-Sleep Mode 25°C 20 27 mW SYNCHRONIZATION FUNCTION4 Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V) 25°C 62.5 MHz Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V) 25°C 100 MHz SYNC_CLK Alignment Resolution5 25°C ±1 SYSCLK Cycles 1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise performance of the device. 2 Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions of the AD9951 section). The longest time required is for the reference clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values are used. 3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency, the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK frequency is the same as the external reference clock frequency. 4 SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set. 5 This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock edges are aligned, the synchronization function should not increase the skew between the two edges.

Figure 2. Equivalent Input and Output Circuits

1. THE EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE

MUST BE ATTACHED TO ANALOG GROUND. Figure 3. 48-Lead TQFP/EP

Table 3. Pin Function Descriptions—48-Lead TQFP/EP must be set up and held around the SYNC_CLK output signal. 2, 34 DVDD I Digital Power Supply Pins (1.8 V). DGND I Digital Power Ground Pins. AVDD I Analog Power Supply Pins (1.8 V). AGND I Analog Power Ground Pins. ended mode, REFCLKB should be decoupled to AVDD with a 0.1 µF capacitor. 10 CRYSTAL OUT O Output of the Oscillator Section. oscillator section is bypassed. 20 IOUT O Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND. 21 IOUT O DAC Output. Should be biased through a resistor to AVDD, not AGND. 23 DACBP I DAC Band Gap Decoupling Pin. A 0.1 μF capacitor to AGND is recommended. 35 PWRDWNCTL I Input Pin Used as an External Power-Down Control (see Table 8 for details). as described in the I/O port register map. returned low. If unused, ground this pin; do not allow this pin to float. operated as a 2-wire serial port, this pin is unused and can be left unconnected. 39 CS I This pin functions as an active low chip select that allows multiple devices to share the I/O bus. 40 SCLK I This pin functions as the serial data clock for I/O operations. 41 SDIO I/O When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input, only. When operated as a 2-wire serial port, this pin is the bidirectional serial data pin. 43 DVDD_I/O I Digital Power Supply (for I/O Cells Only, 3.3 V). 45 SYNC_CLK O Clock Output Pin that Serves as a Synchronizer for External Hardware.

46 OSK I Input Pin Used to Control the Direction of the Shaped On-Off Keying Function when Programmed

be attached to AGND in any board layout.

Rev. A | Page 12 of 28 THEORY OF OPERATION COMPONENT BLOCKS DDS Core The output frequency (fO) of the DDS is a function of the frequency of the system clock (SYSCLK), the value of the frequency tuning word (FTW), and the capacity of the accumulator (232, in this case). The exact relationship is given below with fS defined as the frequency of SYSCLK.   3132 202 /   FTWwithf FTW fSO    1 – 222 / – 1 323132    FTWwithFTWf fS O The value at the output of the phase accumulator is translated to an amplitude value via the COS(x) functional block and routed to the DAC. In certain applications, it is desirable to force the output signal to zero phase. Simply setting the FTW to 0 does not accomplish this; it only results in the DDS core holding its current phase value. Thus, a control bit is required to force the phase accumulator output to zero. At power-up, the clear phase accumulator bit is set to Logic 1, but the buffer memory for this bit is cleared (Logic 0). Therefore, upon power-up, the phase accumulator will remain clear until the first I/O UPDATE is issued. Phase-Locked Loop (PLL) The PLL allows multiplication of the REFCLK frequency. Control of the PLL is accomplished by programming the 5-bit REFCLK multiplier portion of Control Function Register No. 2, Bits <7:3>. When programmed for values ranging from 0x04 to 0x14 (4 decimal to 20 decimal), the PLL multiplies the REFCLK input frequency by the corresponding decimal value. However, the maximum output frequency of the PLL is restricted to 400 MHz. Whenever the PLL value is changed, the user should be aware that time must be allocated to allow the PLL to lock (approximately 1 ms). The PLL is bypassed by programming a value outside the range of 4 to 20 (decimal). When bypassed, the PLL is shut down to conserve power. Clock Input The AD9951 supports various clock methodologies. Support for differential or single-ended input clocks and enabling of an on-chip oscillator and/or a phase-locked loop (PLL) multiplier are all controlled via user programmable bits. The AD9951 may be configured in one of six operating modes to generate the system clock. The modes are configured using the CLKMODESELECT pin, CFR1<4>, and CFR2<7:3>. Connecting the external pin CLKMODESELECT to Logic High enables the on-chip crystal oscillator circuit. With the on-chip oscillator enabled, users of the AD9951 connect an external crystal to the REFCLK and REFCLKB inputs to produce a low frequency reference clock in the range of 20 MHz to 30 MHz. The signal generated by the oscillator is buffered before it is delivered to the rest of the chip. This buffered signal is available via the CRYSTAL OUT pin. Bit CFR1<4> can be used to enable or disable the buffer, turning on or off the system clock. The oscillator itself is not powered down in order to avoid long startup times associated with turning on a crystal oscillator. Writing CFR2<9> to Logic High enables the crystal oscillator output buffer. Logic Low at CFR2<9> disables the oscillator output buffer. Connecting CLKMODESELECT to Logic Low disables the on-chip oscillator and the oscillator output buffer. With the oscillator disabled, an external oscillator must provide the REFCLK and/or REFCLKB signals. For differential operation, these pins are driven with complementary signals. For single- ended operation, a 0.1 μF capacitor should be connected between the unused pin and the analog power supply. With the capacitor in place, the clock input pin bias voltage is 1.35 V . In addition, the PLL may be used to multiply the reference frequency by an integer value in the range of 4 to 20. Table 4 summarizes the clock modes of operation. Note that the PLL multiplier is controlled via the CFR2<7:3> bits, independent of the CFR1<4> bit. Table 4.Clock Input Modes of Operation CFR1<4> CLKMODESELECT CFR2<7:3> Oscillator Enabled? System Clock Frequency Range (MHz) Low High 3 < M < 21 Yes FCLK = FOSC × M 80 < F CLK < 400 Low High M < 4 or M > 20 Yes FCLK = FOSC 20 < F CLK < 30 Low Low 3 < M < 21 No FCLK = FOSC × M 80 < F CLK < 400 Low Low M < 4 or M > 20 No FCLK = FOSC 10 < F CLK < 400 High X X No FCLK = 0 N/A

Rev. A | Page 13 of 28 DAC Output The AD9951 incorporates an integrated 14-bit current output DAC. Unlike most DACs, this output is referenced to AVDD, not AGND. Two complementary outputs provide a combined full-scale output current (IOUT). Differential outputs reduce the amount of common-mode noise that might be present at the DAC output, offering the advantage of an increased signal-to-noise ratio. The full-scale current is controlled by an external resistor (RSET) connected between the DAC_RSET pin and the DAC ground (AGND_DAC). The full-scale current is proportional to the resistor value as follows: OUTSET IR / 19 . 39= The maximum full-scale output current of the combined DAC outputs is 15 mA, but limiting the output to 10 mA provides the best spurious-free dynamic range (SFDR) performance. The DAC output compliance range is AVDD + 0.5 V to AVDD – 0 . 5 V. Voltages developed beyond this range will cause excessive DAC distortion and could potentially damage the DAC output circuitry. Proper attention should be paid to the load termination to keep the output voltage within this compliance range. Serial IO Port The AD9951 serial port is a flexible, synchronous serial communications port that allows easy interface to many industry- standard microcontrollers and microprocessors. The serial I/O port is compatible with most synchronous transfer formats, including both the Motorola 6905/11 SPI® and Intel® 8051 SSR protocols. The interface allows read/write access to all registers that configure the AD9951. MSB first or LSB first transfer formats are supported. The AD9951’ s serial interface port can be configured as a single pin I/O (SDIO), which allows a 2-wire interface or two unidirectional pins for in/out (SDIO/SDO), which in turn enables a 3-wire interface. Two optional pins, IOSYNC and CS Register Map and Descriptions , enable greater flexibility for system design in the AD9951. The register map is listed in Table 5.

Table 5. Register Map

Rev. A | Page 15 of 28 Control Register Bit Descriptions Control Function Register No. 1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9951. The functionality of each bit is detailed below. CFR1<31:27>: Not Used CFR1<26>: Amplitude Ramp Rate Load Control Bit CFR1<26> = 0 (default). The amplitude ramp rate timer is loaded only upon timeout (timer == 1) and is not loaded due to an I/O UPDATE input signal. CFR1<26> = 1. The amplitude ramp rate timer is loaded upon timeout (timer == 1) or at the time of an I/O UPDATE input signal. CFR1<25>: Shaped On-Off Keying Enable Bit CFR1<25> = 0 (default). Shaped on-off keying is bypassed. CFR1<25> = 1. Shaped on-off keying is enabled. When enabled, CFR1<24> controls the mode of operation for this function. CFR1<24>: Auto Shaped On-Off Keying Enable Bit (Only Valid when CFR1<25> Is Active High) CFR1<24> = 0 (default). When CFR1<25> is active, a Logic 0 on CFR1<24> enables the manual shaped on-off keying operation. Each amplitude sample sent to the DAC is multiplied by the amplitude scale factor. See the Shaped On-Off Keying section for details. CFR1<24> = 1. When CFR1<25> is active, a Logic 1 on CFR1<24> enables the auto shaped on-off keying operation. Toggling the OSK pin high will cause the output scalar to ramp up from zero scale to the amplitude scale factor at a rate determined by the amplitude ramp rate. Toggling the OSK pin low will cause the output to ramp down from the amplitude scale factor to zero scale at the amplitude ramp rate. See the Shaped On-Off Keying section for details. CFR1<23>: Automatic Synchronization Enable Bit CFR1<23> = 0 (default). The automatic synchronization feature of multiple AD9951s is inactive. CFR1<23> = 1. The automatic synchronization feature of multiple AD9951s is active. The device will synchronize its internal synchronization clock (SYNC_CLK) to align to the signal present on the SYNC_IN input. See the Synchronizing Multiple AD9951s section for details. CFR1<22>: Software Manual Synchronization of Multiple AD9951 CFR1<22> = 0 (default). The manual synchronization feature is inactive. CFR1<22> = 1. The software controlled manual synchroniza- tion feature is executed. The SYNC_CLK rising edge is advanced by one SYNC_CLK cycle and this bit is cleared. To advance the rising edge multiple times, this bit needs to be set for each advance. See the Synchronizing Multiple AD9951s section for details. CFR1<21:14>: Not Used CFR1<13>: Auto-Clear Phase Accumulator Bit CFR1<13> = 0 (default), the current state of the phase accumulator remains unchanged when the frequency tuning word is applied. CFR1<13> = 1. This bit automatically synchronously clears (loads 0s into) the phase accumulator for one cycle upon reception of an I/O UPDATE signal. CFR1<12>: Sine/Cosine Select Bit CFR1<12> = 0 (default). The angle-to-amplitude conversion logic employs a COSINE function. CFR1<12> = 1. The angle-to-amplitude conversion logic employs a SINE function. CFR1<11>: Not Used CFR1<10>: Clear Phase Accumulator CFR1<10> = 0 (default). The phase accumulator functions as normal. CFR1<10> = 1. The phase accumulator memory elements are cleared and held clear until this bit is cleared. CFR1<9>: SDIO Input Only CFR1<9> = 0 (default). The SDIO pin has bidirectional operation (2-wire serial programming mode). CFR1<9> = 1. The serial data I/O pin (SDIO) is configured as an input only pin (3-wire serial programming mode). CFR1<8>: LSB First CFR1<8> = 0 (default). MSB first format is active. CFR1<8> = 1. The serial interface accepts serial data in LSB first format. CFR1<7>: Digital Power-Down Bit CFR1<7> = 0 (default). All digital functions and clocks are active. CFR1<7> = 1. All non-IO digital functionality is suspended, lowering the power significantly.

Rev. A | Page 16 of 28 CFR1<6>: Not Used CFR1<5>: DAC Power-Down Bit CFR1<5> = 0 (default). The DAC is enabled for operation. CFR1<5> = 1. The DAC is disabled and is in its lowest power dissipation state. CFR1<4>: Clock Input Power-Down Bit CFR1<4> = 0 (default). The clock input circuitry is enabled for operation. CFR1<4> = 1. The clock input circuitry is disabled and the device is in its lowest power dissipation state. CFR1<3>: External Power-Down Mode CFR1<3> = 0 (default). The external power-down mode selected is the rapid recovery power-down mode. In this mode, when the PWRDWNCTL input pin is high, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered down. CFR1<3> = 1. The external power-down mode selected is the full power-down mode. In this mode, when the PWRDWNCTL input pin is high, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up. CFR1<2>: Not Used CFR1<1>: SYNC_CLK Disable Bit CFR1<1> = 0 (default). The SYNC_CLK pin is active. CFR1<1> = 1. The SYNC_CLK pin assumes a static Logic 0 state to keep noise generated by the digital circuitry at a minimum. However, the synchronization circuitry remains active (internally) to maintain normal device timing. CFR1<0>: Not Used, Leave at 0 Control Function Register No. 2 (CFR2) The CFR2 is used to control the various functions, features, and modes of the AD9951, primarily related to the analog sections of the chip. CFR2<23:12>: Not Used CFR2<11>: High Speed Sync Enable Bit CFR2<11> = 0 (default). The high speed sync enhancement is off. CFR2<11> = 1. The high speed sync enhancement is on. This bit should be set when attempting to use the auto-synchronization feature for SYNC_CLK inputs beyond 50 MHz, (200 MSPS SYSCLK). See the Synchronizing Multiple AD9951s section for details. CFR2<10>: Hardware Manual Sync Enable Bit CFR2<10> = 0 (default). The hardware manual sync function is off. CFR2<10> = 1. The hardware manual sync function is enabled. While this bit is set, a rising edge on the SYNC_IN pin will cause the device to advance the SYNC_CLK rising edge by one REFCLK cycle. Unlike the software manual sync enable bit, this bit does not self-clear. Once the hardware manual sync mode is enabled, it will stay enabled until this bit is cleared. See the Synchronizing Multiple AD9951s section for details. CFR2<9>: CRYSTAL OUT Enable Bit CFR2<9> = 0 (default). The CRYSTAL OUT pin is inactive. CFR2<9> = 1. The CRYSTAL OUT pin is active. When active, the crystal oscillator circuitry output drives the CRYSTAL OUT pin, which can be connected to other devices to produce a reference frequency. The oscillator will respond to crystals in the range of 20 MHz to 30 MHz. CFR2<8>: Not Used CFR2<7:3>: Reference Clock Multiplier Control Bits This 5-bit word controls the multiplier value out of the clock- multiplier (PLL) block. Valid values are decimal 4 to 20 (0x04 to 0x14). Values entered outside this range will bypass the clock multiplier. See the Phase-Locked Loop (PLL) section for details. CFR2<2>: VCO Range Control Bit This bit is used to control the range setting on the VCO. When CFR2<2> == 0 (default), the VCO operates in a range of 100 MHz to 250 MHz. When CFR2<2> == 1, the VCO operates in a range of 250 MHz to 400 MHz. CFR2<1:0>: Charge Pump Current Control Bits These bits are used to control the current setting on the charge pump. The default setting, CFR2<1:0>, sets the charge pump current to the default value of 75 μA. For each bit added (01, 10, 11), 25 μA of current is added to the charge pump current: 100 μA, 125 μA, and 150 μA.

Rev. A | Page 17 of 28 Other Register Descriptions Amplitude Scale Factor (ASF) The ASF register stores the 2-bit auto ramp rate speed value and the 14-bit amplitude scale factor used in the output shaped keying (OSK) operation. In auto OSK operation, ASF <15:14> tells the OSK block how many amplitude steps to take for each increment or decrement. ASF<13:0> sets the maximum value achievable by the OSK internal multiplier. In manual OSK mode, ASF<15:14> has no effect. ASF <13:0> provide the output scale factor directly. If the OSK enable bit is cleared, CFR1<25> = 0, this register has no effect on device operation. Amplitude Ramp Rate (ARR) The ARR register stores the 8-bit amplitude ramp rate used in the auto OSK mode. This register programs the rate at which the amplitude scale factor counter increments or decrements. If the OSK is set to manual mode, or if OSK enable is cleared, this register has no effect on device operation. Frequency Tuning Word 0 (FTW0) The frequency tuning word is a 32-bit register that controls the rate of accumulation in the phase accumulator of the DDS core. Its specific role is dependent on the device mode of operation. Phase Offset Word (POW) The phase offset word is a 14-bit register that stores a phase offset value. This offset value is added to the output of the phase accumulator to offset the current phase of the output signal. The exact value of phase offset is given by the following formula:      360214 POW MODES OF OPERATION Single-Tone Mode In single-tone mode, the DDS core uses a single tuning word. Whatever value is stored in FTW0 is supplied to the phase accumulator. This value can only be changed manually, which is done by writing a new value to FTW0 and by issuing an I/O UPDATE. Phase adjustment is possible through the phase offset register. PROGRAMMING AD9951 FEATURES Phase Offset Control A 14-bit phase offset (θ) may be added to the output of the phase accumulator by means of the control registers. This feature provides the user with two different methods of phase control. The first method is a static phase adjustment, where a fixed phase offset is loaded into the appropriate phase offset register and left unchanged. The result is that the output signal is offset by a constant angle relative to the nominal signal. This allows the user to phase align the DDS output with some external signal, if necessary. The second method of phase control is where the user regularly updates the phase offset register via the I/O port. By properly modifying the phase offset as a function of time, the user can implement a phase modulated output signal. However, both the speed of the I/O port and the frequency of SYSCLK limit the rate at which phase modulation can be performed. The AD9951 allows for a programmable continuous zeroing of the phase accumulator as well as a clear and release or auto- matic zeroing function. Each feature is individually controlled via the CFR1 bits. CFR1<13> is the automatic clear phase accumulator bit. CFR1<10> clears the phase accumulator and holds the value to zero. Continuous Clear Bit The continuous clear bit is simply a static control signal that, when active high, holds the phase accumulator at zero for the entire time the bit is active. When the bit goes low, inactive, the phase accumulator is allowed to operate. Clear and Release Function When set, the auto-clear phase accumulator clears and releases the phase accumulator upon receiving an I/O UPDATE. The automatic clearing function is repeated for every subsequent I/O UPDATE until the appropriate auto-clear control bit is cleared. Shaped On-Off Keying The shaped on-off keying function of the AD9951 allows the user to control the ramp-up and ramp-down time of an on-off emission from the DAC. This function is used in burst transmis- sions of digital data to reduce the adverse spectral impact of short, abrupt bursts of data. Auto and manual shaped on-off keying modes are supported. The auto mode generates a linear scale factor at a rate deter- mined by the amplitude ramp rate (ARR) register controlled by an external pin (OSK). Manual mode allows the user to directly control the output amplitude by writing the scale factor value into the amplitude scale factor (ASF) register. The shaped on-off keying function may be bypassed (disabled) by clearing the OSK enable bit (CFR1<25> = 0). The modes are controlled by two bits located in the most signifi- cant byte of the control function register (CFR). CFR1<25> is the shaped on-off keying enable bit. When CFR1<25> is set, the output scaling function is enabled and CFR1<25> bypasses the function. CFR1<24> is the internal shaped on-off keying active bit. When CFR1<24> is set, internal shaped on-off keying mode is active; CFR1<24> is cleared, external shaped on-off keying mode is active. CFR1<24> is a Don’t Care if the shaped on-off keying enable bit (CFR1<25>) is cleared. The power up condition is shaped on-off keying disabled (CFR1<25> = 0). Figure 18 shows the block diagram of the OSK circuitry.

multiplies the DDS core output by 16383 (decimal). factor per the ASF<15:14> bits. Table 6. Auto-Scale Factor Internal Step Size value of the ASFR every time the counter reaches 1 (decimal). rate timer, which then proceeds to count down as normal. (CFR1<26>) is set and an I/O UPDATE is issued. Figure 18. On-Off Shaped Keying, Block Diagram

CFR1<25> to a Logic 1 and writing CFR1<24> to a Logic 0. content of the ASFR becomes the scale factor for the data path. an I/O UPDATE timing cycle and synchronization.

1. The I/O UPDATE signal is edge detected to generate a
2. The I/O UPDATE pin is set up and held around the rising

Figure 19. I/O Synchronization Block Diagram

THE DEVICE REGISTERS AN I/ O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B. Figure 20. I/O Synchronization Timing Diagram should be set to 3.3 V for all devices that are to be synchronized. AVDD and DVDD should be left at 1.8 V . SYNC_IN input, which is the SYNC_CLK of the master device. enable bit should be set (CFR2<11> = 1). multiple times, this bit will need to be set multiple times. SYSCLK cycle until this enable bit is cleared (CFR2<10> = 0). should be connected to the REFCLK input of the other AD9951. to using it to drive any loads.

Rev. A | Page 22 of 28 INSTRUCTION BYTE The instruction byte contains the following information: Table 7. MSB D6 D5 D4 D3 D2 D1 LSB R/Wb X X A4 A3 A2 A1 A0 R/Wb—Bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. Logic High indicates read operation. Logic 0 indicates a write operation. X, X—Bits 6 and 5 of the instruction byte are Don’t Care. A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. SERIAL INTERFACE PORT PIN DESCRIPTION SCLK—Serial Clock. The serial clock pin is used to synchronize data to and from the AD9951 and to run the internal state machines. SCLK maximum frequency is 25 MHz. CSB—Chip Select Bar. CSB is active low input that allows more than one device on the same serial communications line. The SDO and SDIO pins will go to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until CS is reactivated low. Chip select can be tied low in systems that maintain control of SCLK. SDIO — Serial Data I/O. Data is always written into the AD9951 on this pin. However, this pin can be used as a bidirectional data line. Bit 9 of Register Address 0x00 controls the configuration of this pin. The default is Logic 0, which configures the SDIO pin as bidirectional. SDO—Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9951 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. IOSYNC—It synchronizes the I/O port state machines without affecting the addressable register’s contents. An active high input on the IOSYNC pin causes the current communication cycle to abort. After IOSYNC returns low (Logic 0), another communication cycle may begin, starting with the instruction byte write. MSB/LSB TRANSFERS The AD9951 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the Control Register 0x00 <8> bit. The default value of Control Register 0x00 <8> is low (MSB first). When Control Register 0x00 <8> is set high, the AD9951 serial port is in LSB first format. The instruction byte must be written in the format indicated by Control Register 0x00 <8>. If the AD9951 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. For MSB first operation, the serial port controller will generate the most significant byte (of the specified register) address first followed by the next lesser significant byte addresses until the I/O operation is complete. All data written to (read from) the AD9951 must be (will be) in MSB first order. If the LSB mode is active, the serial port controller will generate the least signifi- cant byte address first followed by the next greater significant byte addresses until the I/O operation is complete. All data written to (read from) the AD9951 must be (will be) in LSB first order. Example Operation To write the amplitude scale factor register in MSB first format, apply an instruction byte of 0x02 (serial address is 00010(b)). From this instruction, the internal controller will generate an internal byte address of 0x07 (see the register map) for the first data byte written and an internal address of 0x08 for the next byte written. Since the amplitude scale factor register is two bytes wide, this ends the communication cycle. To write the amplitude scale factor register in LSB first format, apply an instruction byte of 0x40. From this instruction, the internal controller will generate an internal byte address of 0x08 (see the register map) for the first data byte written and an internal address of 0x07for the next byte written. Since the amplitude scale factor register is two bytes wide, this ends the communication cycle. Power-Down Functions of the AD9951 The AD9951 supports an externally controlled or hardware power-down feature as well as the more common software programmable power-down bits found in previous ADI DDS products. The software control power-down allows the DAC, PLL, input clock circuitry, and digital logic to be individually powered down via unique control bits (CFR1<7:4>). With the exception of CFR1<6>, these bits are not active when the externally controlled power-down pin (PWRDWNCTL) is high. External power-down control is supported on the AD9951 via the PWRDWNCTL input pin. When the PWRDWNCTL input pin is high, the AD9951 will enter a power-down mode based on the CFR1<3> bit. When the PWRDWNCTL input pin is low, the external power-down control is inactive.

high, the AD9951 is put into a fast recovery power-down mode. clock input circuitry is NOT powered down. pin is high, the AD9951 is put into the full power-down mode. the active or powered up mode. 10 µF) further away from the actual supply source works best. Table 8. Power-Down Control Functions

0.50 BSC

0.08 MAX

Figure 28. 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

Rev. A | Page 26 of 28 NOTES

Rev. A | Page 27 of 28 NOTES

Rev. A | Page 28 of 28 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03359-0-5/09(A)