AD9948 AD | Alldatasheet
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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD9948 10-Bit CCD Signal Processor with Precision Timing™ Core FUNCTIONAL BLOCK DIAGRAM CLAMP DOUTCCDIN REFT REFB INTERNAL REGISTERS 6dB TO 42dB SYNC GENERATOR SDATASCKSL HBLK VGA AD9948 PRECISION TIMING CORE 10-BIT ADC VREF INTERNAL CLOCKS PxGACDS HORIZONTAL DRIVERS4 RG H1–H4 HD VD CLI CLP/PBLK 0dB TO 18dB
FEATURES
Correlated Double Sampler (CDS) 0 dB to 18 dB Pixel Gain Amplifier ( PxGA® ) 6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA) 10-Bit 25 MSPS A/D Converter Black Level Clamp with Variable Level Control Complete On-Chip Timing Driver Precision Timing Core with 800 ps Resolution On-Chip 3 V Horizontal and RG Drivers 40-Lead LFCSP Package
APPLICATIONS
High Speed Digital Imaging Applications GENERAL DESCRIPTION The AD9948 is a highly integrated CCD signal processor for digital still camera applications. Specified at pixel rates of up to
25 MHz, the AD9948 consists of a complete analog front end
with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with 800 ps resolution. The analog front end includes black level clamping, CDS, PxGA, VGA, and a 25 MHz 10-bit A/D converter. The timing driver provides the high speed CCD clock drivers for RG and H1–H4. Operation is programmed using a 3-wire serial interface. Packaged in a space-saving 40-lead LFCSP package, the AD9948 is specified over an operating temperature range of –20°C to +85 °C.
REV. 0–2– AD9948–SPECIFICATIONS DIGITAL SPECIFICATIONS Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage V IH 2.1 V Low Level Input Voltage V IL 0.6 V High Level Input Current I IH 10 µA Low Level Input Current I IL 10 µA Input Capacitance C IN 10 pF LOGIC OUTPUTS High Level Output Voltage, I OH = 2 mA V OH 2.2 V Low Level Output Voltage, I OL = 2 mA V OL 0.5 V CLI INPUT High Level Input Voltage (TCVDD/2 + 0.5 V) V IH–CLI 1.85 V Low Level Input Voltage V IL–CLI 0.85 V RG AND H-DRIVER OUTPUTS High Level Output Voltage (RGVDD – 0.5 V and HVDD – 0.5 V) V OH 2.2 V Low Level Output Voltage V OL 0.5 V Maximum Output Current (Programmable) 30 mA Maximum Load Capacitance 100 pF Specifications subject to change without notice. GENERAL SPECIFICATIONS Parameter Min Typ Max Unit TEMPERATURE RANGE Operating –20 +85 °C Storage –65 +150 °C MAXIMUM CLOCK RATE 25 MHz POWER SUPPLY VOLTAGE AVDD, TCVDD (AFE, Timing Core) 2.7 3.0 3.6 V HVDD (H1–H4 Drivers) 2.7 3.0 3.6 V RGVDD (RG Driver) 2.7 3.0 3.6 V DRVDD (D0–D9 Drivers) 2.7 3.0 3.6 V DVDD (All Other Digital) 2.7 3.0 3.6 V POWER DISSIPATION
25 MHz, HVDD = RGVDD = 3 V, 100 pF H1–H4 Loading * 220 mW
*The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power C HVDD Pixel Frequency HVDD Number of H Outputs UsedLOAD=×× ×× −() ( ) Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation. Specifications subject to change without notice. (TMIN to TMAX, AVDD = DVDD = DRVDD = HVDD = RGVDD = 2.7 V, CL = 20 pF, unless otherwise noted.)
REV. 0 AD9948 –3– ANALOG SPECIFICATIONS Parameter Min Typ Max Unit Notes CDS Gain 0 dB Allowable CCD Reset Transient * 500 mV Max Input Range before Saturation * 1.0 V p-p Max CCD Black Pixel Amplitude * ±50 mV PIXEL GAIN AMPLIFIER (PxGA) Gain Control Resolution 256 Steps Gain Monotonicity Min Gain 0 dB Max Gain 18 dB VARIABLE GAIN AMPLIFIER (VGA) Max Input Range 1.0 V p-p Max Output Range 2.0 V p-p Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range Min Gain (VGA Code 0) 6 dB Max Gain (VGA Code 1023) 42 dB BLACK LEVEL CLAMP Clamp Level Resolution 256 Steps Clamp Level Measured at ADC output Min Clamp Level (0) 0 LSB Max Clamp Level (255) 63.75 LSB A/D CONVERTER Resolution 10 Bits Differential Nonlinearity (DNL) –1.0 ±0.5 +1.0 LSB No Missing Codes Guaranteed Full-Scale Input Voltage 2.0 V VOLTAGE REFERENCE Reference Top Voltage (REFT) 2.0 V Reference Bottom Voltage (REFB) 1.0 V SYSTEM PERFORMANCE Specifications include entire signal chain VGA Gain Accuracy Min Gain (Code 0) 5.0 5.5 6.0 dB Max Gain (Code 1023) 40.5 41.5 42.5 dB Peak Nonlinearity, 500 mV Input Signal 0.2 % 12 dB gain applied Total Output Noise 0.25 LSB rms AC grounded input, 6 dB gain applied Power Supply Rejection (PSR) 50 dB Measured with step change on supply *Input signal characteristics defined as follows: 50mV MAX OPTICAL BLACK PIXEL 500mV TYP RESET TRANSIENT 1V MAX INPUT SIGNAL RANGE Specifications subject to change without notice. (TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 25 MHz, Typical Timing Specifications, unless otherwise noted.)
REV. 0–4– AD9948 TIMING SPECIFICATIONS Parameter Symbol Min Typ Max Unit MASTER CLOCK (CLI) (See Figure 4) CLI Clock Period t CLI 40 ns CLI High/Low Pulsewidth t ADC 16 20 24 ns Delay from CLI to Internal Pixel Period Position t CLIDLY 6n s CLPOB Pulsewidth (Programmable) * tCOB 22 0 Pixels SAMPLE CLOCKS (See Figure 6) SHP Rising Edge to SHD Rising Edge t S1 17 20 ns DATA OUTPUTS (See Figures 7a and 7b) Output Delay From Programmed Edge t OD 6n s Pipeline Delay 11 Cycles SERIAL INTERFACE Maximum SCK Frequency f SCLK 10 MHz SL to SCK Setup Time t LS 10 ns SCK to SL Hold Time t LH 10 ns SDATA Valid to SCK Rising Edge Setup t DS 10 ns SCK Falling Edge to SDATA Valid Hold t DH 10 ns SCK Falling Edge to SDATA Valid Read t DV 10 ns *Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp refe rence. Specifications subject to change without notice. (CL = 20 pF, fCLI = 25 MHz, Serial Timing in Figure 3, unless otherwise noted.) ABSOLUTE MAXIMUM RATINGS * With Parameter Respect To Min Max Unit AVDD, TCVDD AVSS –0.3 +3.9 V HVDD, RGVDD HVSS, RGVSS –0.3 +3.9 V DVDD, DRVDD DVSS, DRVSS –0.3 +3.9 V Any VSS Any VSS –0.3 +0.3 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V CLPOB/PBLK, HBLK DVSS –0.3 DVDD + 0.3 V SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V RG RGVSS –0.3 RGVDD + 0.3 V H1–H4 HVSS –0.3 HVDD + 0.3 V REFT, REFB, CCDIN AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 °C Lead Temperature (10 sec) 300 °C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9948 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Temperature Package Package Model Range Description Option AD9948KCP –20 °C to +85°C LFCSP CP-40 AD9948KCPRL –20 °C to +85°C LFCSP CP-40 AD9948KCPZ* –20°C to +85°C LFCSP CP-40 AD9948KCPZRL* –20°C to +85°C LFCSP CP-40 *This is a lead free product. THERMAL CHARACTERISTICS Thermal Resistance 40-Lead LFCSP Package /H9258JA = 27°C/W* */H9258JA is measured using a 4-layer PCB with the exposed paddle soldered to the board.
REV. 0 AD9948 –5– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type * Description 2–4 D0–D2 DO Data Outputs (D0 is LSB)
5 DRVSS P Digital Driver Ground
6 DRVDD P Digital Driver Supply
7–13 D3–D9 DO Data Outputs (D9 is MSB)
14 H1 DO CCD Horizontal Clock 1
15 H2 DO CCD Horizontal Clock 2
16 HVSS P H1–H4 Driver Ground
17 HVDD P H1–H4 Driver Supply
18 H3 DO CCD Horizontal Clock 3
19 H4 DO CCD Horizontal Clock 4
20 RGVSS P RG Driver Ground
21 RG DO CCD Reset Gate Clock
22 RGVDD P RG Driver Supply
23 TCVSS P Analog Ground for Timing Core
24 TCVDD P Analog Supply for Timing Core
25 CLI DI Master Clock Input
26 AVDD P Analog Supply for AFE
27 CCDIN AI Analog Input for CCD Signal (Connect through Series 0.1 µF Capacitor)
28 AVSS P Analog Ground for AFE
29 REFT AO Reference Top Decoupling (Decouple with 1.0 µF to AVSS) 30 REFB AO Reference Bottom Decoupling (Decouple with 1.0 µF to AVSS)
31 SL DI 3-Wire Serial Load
32 SDI DI 3-Wire Serial Data Input
33 SCK DI 3-Wire Serial Clock
34 VD DI Vertical Sync Pulse
35 HD DI Horizontal Sync Pulse
36 DVSS P Digital Ground
37 DVDD P Digital Supply
38 HBLK DI Optional HBLK Input
39 CLP/PBLK DO CLPOB or PBLK Output
1, 40 NC Not Internally Connected *Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power. PIN CONFIGURATION TOP VIEW AD9948 PIN 1 IDENTIFIER
30 REFB
29 REFT
28 AVSS
27 CCDIN
26 AVDD
25 CLI
24 TCVDD
23 TCVSS
22 RGVDD
(LSB) D0 2 D1 3 D2 4 DRVSS 5 DRVDD 6 D3 7 D4 8 D5 9 D6 10 40 NC
39 CLP/PBLK
38 HBLK
37 DVDD
36 DVSS
33 SCK
32 SDI
(MSB) D9 13 H1 14 H2 15 HVSS 16 HVDD 17 H3 18 H4 19 RGVSS 20
REV. 0–6– AD9948 EQUIVALENT CIRCUITS R AVDD AVSS AVSS Circuit 1. CCDIN (Pin 27) AVDD AVSS 330/H9024 CLI 25k/H9024 1.4V Circuit 2. CLI (Pin 25) DVSS DRVDD DVSS DRVSS DATA THREE- STATE DOUT Circuit 3. Data Outputs D0–D9 (Pins 2–4, 7–13) DVDD DVSS 330/H9024 Circuit 4. Digital Inputs (Pins 31–35, 38) HVDD or RGVDD HVSS or RGVSS DATA ENABLE OUTPUT Circuit 5. H1–H4 and RG (Pins 14, 15, 18, 19, 21) TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit resolution indicates that all 1024 codes, respectively, must be present over all operating conditions. Peak Nonlinearity Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9948 from a true straight line. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level 1 LSB and 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appro- priately gained up to fill the ADC’s full-scale range. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB, and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 12 n LSB (ADC full scale/ codes)= where n is the bit resolution of the ADC. For the AD9948, 1L SB is approximately 1.95 mV. Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.
REV. 0 Typical Performance Characteristics–AD9948 –7– –1.0 0 1000400200 600 800 –0.5 0.5 1.0 ADC OUTPUT CODE DNL (LSB) TPC 1. Typical DNL VGA GAIN CODE (LSB) 0 1000400 OUTPUT NOISE (LSB) 200 2.5 600 800 5.0 7.5 TPC 2. Output Noise vs. VGA Gain SAMPLE RA TE (MHz) 250 200 100 2510 POWER DISSIP A TION (mW) 150 175 225 VDD = 3.3V 125 275 VDD = 3.0V VDD = 2.7V TPC 3. Power Curves
REV. 0–10– AD9948 Table II. AFE Register Map Data Bit Default Address Content Value Name Description 00 [11:0] 4 OPRMODE AFE Operation Modes. (See Table VIII.) 01 [9:0] 0 VGAGAIN VGA Gain. 02 [7:0] 80 CLAMP LEVEL Optical Black Clamp Level. 03 [11:0] 4 CTLMODE AFE Control Modes. (See Table IX.) 04 [17:0] 0 PxGA GAIN01 PxGA Gain Registers for Color 0 [8:0] and Color 1 [17:9]. 05 [17:0] 0 PxGA GAIN23 PxGA Gain Registers for Color 2 [8:0] and Color 3 [17:9]. Table III. Miscellaneous Register Map Data Bit Default Address Content Value Name Description 10 [0] 0 SW_RST Software Reset. 1 = Reset all registers to default, then self-clear back to 0. 11 [0] 0 OUT_CONTROL Output Control. 0 = Make all dc outputs inactive. 12 [0] 0 TGCORE_RSTB Timing Core Reset Bar. 0 = Reset TG core. 1 = Resume operation. 13 [11:0] 0 UPDATE Serial Update. Sets the line (HD) within the field to update serial data. 14 [0] 0 PREVENTUPDATE Prevents the update of the VD-Updated Registers. 1 = Prevent update. 15 [0] 0 VDHDEDGE VD/HD Active Edge. 0 = Falling edge triggered. 1 = Rising edge triggered. 16 [1:0] 0 FIELDVAL Field Value Sync. 0 = Next Field 0. 1 = Next Field 1. 2/3 = Next Field 2. 17 [0] 0 HBLKRETIME Retime HBLK to Internal H1 Clock. Preferred setting is 1. Setting to 1 will add one cycle delay to HBLK toggle positions. 18 [1:0] 0 CLPBLKOUT CLP/BLK Pin Output Select. 0 = CLPOB. 1 = PBLK. 2 = HBLK. 3 = Low. 19 [0] 1 CLPBLKEN Enable CLP/BLK Output. 1 = Enable. 1A [0] 0 TEST MODE Internal Test Mode. Should always be set low.
REV. 0 AD9948 –11– Table IV. CLPOB Register Map Data Bit Default Address Content Value (Hex) Name Description 20 [3:0] F CLPOBPOL Start Polarities for CLPOB Sequences 0, 1, 2, and 3. 21 [23:0] FFFFFF CLPOBTOG_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 22 [23:0] FFFFFF CLPOBTOG_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 23 [23:0] FFFFFF CLPOBTOG_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 24 [23:0] FFFFFF CLPOBTOG_3 Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 0 CLPOBSCP0 CLPOB Sequence-Change-Position 0 (Hard-Coded to 0). 25 [7:0] 0 CLPOBSPTR CLPOB Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6]. 26 [11:0] FFF CLPOBSCP1 CLPOB Sequence-Change-Position 1. 27 [11:0] FFF CLPOBSCP2 CLPOB Sequence-Change-Position 2. 28 [11:0] FFF CLPOBSCP3 CLPOB Sequence-Change-Position 3. Table V. PBLK Register Map Data Bit Default Address Content Value (Hex) Name Description 30 [3:0] F PBLKPOL Start Polarities for PBLK Sequences 0, 1, 2, and 3. 31 [23:0] FFFFFF PBLKTOG_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 32 [23:0] FFFFFF PBLKTOG_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 33 [23:0] FFFFFF PBLKTOG_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 34 [23:0] FFFFFF PBLKTOG_3 Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 0 PBLKSCP0 PBLK Sequence-Change-Position 0 (Hard-Coded to 0). 35 [7:0] 0 PBLKSPTR PBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6]. 36 [11:0] FFF PBLKSCP1 PBLK Sequence-Change-Position 1. 37 [11:0] FFF PBLKSCP2 PBLK Sequence-Change-Position 2. 38 [11:0] FFF PBLKSCP3 PBLK Sequence-Change-Position 3.
REV. 0–12– AD9948 Table VI. HBLK Register Map Data Bit Default Address Content Value (Hex) Name Description 40 [0] 0 HBLKDIR HBLK Internal/External. 0 = Internal. 1 = External. 41 [0] 0 HBLKPOL HBLK External Active Polarity. 0 = Active Low. 1 = Active High. 42 [0] 1 HBLKEXTMASK HBLK External Masking Polarity. 0 = Mask H1 Low. 1 = Mask H1High. 43 [3:0] F HBLKMASK HBLK Internal Masking Polarity. 0 = Mask H1 Low. 1 = Mask H1 High. 44 [23:0] FFFFFF HBLKTOG12_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 45 [23:0] FFFFFF HBLKTOG34_0 Sequence 0. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. 46 [23:0] FFFFFF HBLKTOG56_0 Sequence 0. Toggle Position 5 [11:0] and Toggle Position 6 [23:12]. 47 [23:0] FFFFFF HBLKTOG12_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 48 [23:0] FFFFFF HBLKTOG34_1 Sequence 1. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. 49 [23:0] FFFFFF HBLKTOG56_1 Sequence 1. Toggle Position 5 [11:0] and Toggle Position 6 [23:12]. 4A [23:0] FFFFFF HBLKTOG12_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 4B [23:0] FFFFFF HBLKTOG34_2 Sequence 2. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. 4C [23:0] FFFFFF HBLKTOG56_2 Sequence 2. Toggle Position 5 [11:0] and Toggle Position 6 [23:12]. 4D [23:0] FFFFFF HBLKTOG12_3 Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12]. 4E [23:0] FFFFFF HBLKTOG34_3 Sequence 3. Toggle Position 3 [11:0] and Toggle Position 4 [23:12]. 4F [23:0] FFFFFF HBLKTOG56_3 Sequence 3. Toggle Position 5 [11:0] and Toggle Position 6 [23:12]. 0 HBLKSCP0 HBLK Sequence-Change-Position 0 (Hard-coded to 0). 50 [7:0] 0 HBLKSPTR HBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6]. 51 [11:0] FFF HBLKSCP1 HBLK Sequence-Change-Position 1. 52 [11:0] FFF HBLKSCP2 HBLK Sequence-Change-Position 2. 53 [11:0] FFF HBLKSCP3 HBLK Sequence-Change-Position 3. Table VII. H1–H2, RG, SHP, SHD Register Map Data Bit Default Address Content Value Name Description 60 [12:0] 01001 H1CONTROL H1 Signal Control. Polarity [0] (0 = Inversion, 1 = No Inversion). H1 Positive Edge Location [6:1]. H1 Negative Edge Location [12:7]. 61 [12:0] 00801 RGCONTROL RG Signal Control. Polarity [0] (0 = Inversion, 1 = No Inversion). RG Positive Edge Location [6:1]. RG Negative Edge Location [12:7]. 62 [14:0] 0 DRVCONTROL Drive Strength Control for H1 [2:0], H2 [5:3], H3 [8:6], H4 [11:9], and RG [14:12]. Drive Current Values: 0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA, 63 [11:0] 00024 SAMPCONTROL SHP/SHD Sample Control. SHP Sampling Location [5:0]. SHD Sampling Location [11:6]. 64 [5:0] 0 DOUTPHASE DOUT Phase Control.
REV. 0 AD9948 –13– Table VIII. AFE Operation Register Detail Data Bit Default Address Content Value Name Description 00 [1:0] 0 PWRDOWN 0 = Normal Operation. 1 = Reference Standby. 2/3 = Total Power-Down. [2] 1 CLPENABLE 0 = Disable OB Clamp. 1 = Enable OB Clamp. [3] 0 CLPSPEED 0 = Select Normal OB Clamp Settling. 1 = Select Fast OB Clamp Settling. [4] 0 FASTUPDATE 0 = Ignore VGA Update. 1 = Very Fast Clamping when VGA Is Updated. [5] 0 PBLK_LVL DOUT Value during PBLK. 0 = Blank to Zero. 1 = Blank to Clamp Level. [7:6] 0 TEST MODE Test Operation Only. Set to zero. [8] 0 DCBYP 0 = Enable DC Restore Circuit. 1 = Bypass DC Restore Circuit during PBLK. [9] 0 TESTMODE Test Operation Only. Set to zero. [11:10] 0 CDSGAIN Adjustment of CDS Gain. 0 = 0 dB. 01= –2 dB. 10 = –4 dB. 11 = 0 dB. Table IX. AFE Control Register Detail Data Bit Default Address Content Value Name Description 04 [1:0] 0 COLORSTEER 0 = Off. 1 = Progressive. 2 = Interlaced. 3 = Three Field. [2] 1 PXGAENABLE 0 = Disable PxGA. 1 = Enable PxGA. [3] 0 DOUTDISABLE 0 = Data Outputs Are Driven. 1 = Data Outputs Are Three-Stated. [4] 0 DOUTLATCH 0 = Latch Data Outputs with DOUT Phase. 1 = Output Latch Transparent. [5] 0 GRAYENCODE 0 = Binary Encode Data Outputs. 1= Gray Encode Data Outputs.
divides the master clock period into 48 steps or edge positions. the Applications Information section. and falling edges, and may be inverted using the polarity control. the high speed timing registers and their parameters. corresponding edge locations.
- PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
- THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6 ns TYP).
1 PIXEL
Figure 4. High Speed Clock Resolution From CLI Master Clock Input
- H1/H3 RISING EDGE POSITION
- H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3)
Figure 5. High Speed Clock Programmable Locations Polarity 1b High/Low Polarity Control for H1/H3 and RG (0 = No Inversion, 1 = Inversion). Positive Edge 6b 0–47 Edge Location Positive Edge Location for H1/H3 and RG. Negative Edge 6b 0–47 Edge Location Negative Edge Location for H1/H3 and RG. Sample Location 6b 0–47 Sample Location Sampling Location for SHP and SHD. Drive Control 3b 0–7 Current Steps Drive Current for H1–H4 and RG Outputs, 0–7 Steps of 4.1 mA Each. DOUT Phase 6b 0–47 Edge Location Phase Location of Data Outputs with Respect to Pixel Period.
features on-chip output drivers for the RG and H1–H4 outputs. As shown in Figure 6, the H2/H4 outputs are inverses of H1/H3. voltage is not programmable. for the digital data output is shown in Figure 7b. Figure 6. H-Clock Inverse Phase Relationship
- DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
- WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
1 PIXEL PERIOD
DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
Figure 14. Recommended Power-Up Sequence
- Turn on the power supplies for the AD9948.
- Apply the master clock input, CLI, VD, and HD.
- Although the AD9948 contains an on-chip power-on reset, a
self-clearing and will automatically be reset back to 0.
- The Precision Timing core must be reset by writing a 0 to the
- Write a 1 to the PREVENTUPDATE register (Address x014).
This will prevent the updating of the serial register data.
- Write to the desired registers to configure high speed timing
- Write a 1 to the OUT_CONTROL register (Address x011).
- Write a 0 to the PREVENTUPDATE register (Address x014).
including OUT_CONTROL, which enables all clock outputs.
Figure 21. Recommended Circuit Configuration Figure 21. Achieving good image quality from the AD9948 should be as direct as possible from the AD9948 to the CCD. ing the pad to the ground plane.
3 V supply may be used for DRVDD, but this supply pin should
chip. A separate ground for DRVSS is not recommended. input (CCDIN) capacitor should also be located close to the pin.
pixels in the front and 48 in the back. order to stabilize the clamp loop of the AD9948.
28 DUMMY PIXELS
48 OB PIXELS4 OB PIXELS
10 VERTICAL OB LINES
2 VERTICAL OB LINES
Figure 24. Example CCD Configuration Figure 25. Horizontal Sequence during Vertical Blanking
REV. 0 C03752–0–5/03(0) –28– AD9948 OUTLINE DIMENSIONS 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm /H11547 6 mm Body (CP-40) Dimensions shown in millimeters BOTTOM VIEW 4.25 3.70 SQ 1.75 TOP VIEW 6.00 BSC SQ PIN 1 INDICATOR 5.75 BSC SQ 12/H11543 MAX 0.30 0.23 0.18
0.20 REF
1.00 0.90 0.80
0.05 MAX
0.02 NOM
0.08
0.80 MAX
0.65 NOM
4.50 REF 0.50 0.40 0.30 0.50 BSC PIN 1 INDICATOR
0.60 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2