AD9943 AD | Alldatasheet
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Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors AD9943/AD9944 Rev. B Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
25 MSPS correlated double sampler (CDS)
6 dB to 40 dB 10-bit variable gain amplifier (VGA) Low noise optical black clamp circuit Preblanking function 10-bit (AD9943), 12-bit (AD9944) 25 MSPS A/D converter No missing codes guaranteed 3-wire serial digital interface
3 V single-supply operation
Space-saving 32-lead 5 mm × 5 mm LFCSP package
APPLICATIONS
Portable CCD imaging devices CCTV cameras GENERAL DESCRIPTION The AD9943/AD9944 are complete analog signal processors for CCD applications. They feature a 25 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The signal chain for the AD9943/AD9944 consists of a correlated double sampler (CDS), a digitally controlled variable gain amplifier (VGA), and a black level clamp. The AD9943 offers 10-bit ADC resolution, while the AD9944 contains a true 12-bit ADC. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input clock polarity, and power-down modes. The AD9943/AD9944 operate from a single 3 V power supply, typically dissipate 79 mW, and are packaged in space-saving 32-lead LFCSP packages. FUNCTIONAL BLOCK DIAGRAM DATACLKSHDSHP BAND GAP REFERENCE DOUTCCDIN PBLKREFT REFB INTERNAL TIMING 6dB–40dB AVDD DVDD DVSS AVSS DRVDD DRVSS DIGITAL INTERFACE SDATASCKSL CLPOB CDS VGA CLP AD9943/AD9944 CONTROL REGISTERS 10-/12-BIT ADC 02905-B-001 Figure 1. Functional Block Diagram
Rev. B | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
5/04—Data Sheet Changed from Rev. A to Rev. B 5/03—Data Sheet changed from Rev. 0 to Rev. A
Rev. B | Page 3 of 20 AD9943/AD9944 SPECIFICATIONS GENERAL SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V , fSAMP = 25 MHz, unless otherwise noted. Table 1. Parameter Min Typ Max Unit TEMPERATURE RANGE Operating −20 +85 °C Storage −65 +150 °C POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver 2.7 3.6 V POWER CONSUMPTION Normal Operation 79 mW Power-Down Mode 150 µW MAXIMUM CLOCK RATE 25 MHz DIGITAL SPECIFICATIONS DRVDD = DVDD = 2.7 V , CL = 20 pF, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage VIH 2.1 V Low Level Input Voltage VIL 0.6 V High Level Input Current IIH 10 µA Low Level Input Current IIL 10 µA Input Capacitance CIN 10 pF LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA VOH 2.2 V Low Level Output Voltage, IOL = 2 mA VOL 0.5 V
Rev. B | Page 4 of 20 AD9943 SYSTEM SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Conditions CDS Maximum Input Range before Saturation1 1.0 V p-p Allowable CCD Reset Transient1 500 mV See input waveform in footnote. Maximum CCD Black Pixel Amplitude1 100 mV VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range Minimum Gain 5.3 dB See Figure 13 for VGA gain curve. Maximum Gain 40 41.5 dB See Variable Gain Amplifier section for VGA gain equation. BLACK LEVEL CLAMP Clamp Level Resolution 256 Steps Clamp Level Measured at ADC output. Minimum Clamp Level 0 LSB Maximum Clamp Level 63.75 LSB A/D CONVERTER Resolution 10 Bits Differential Nonlinearity (DNL) ±0.3 LSB No Missing Codes Guaranteed Data Output Coding Straight binary Full-Scale Input Voltage 2.0 V VOLTAGE REFERENCE Reference Top Voltage (REFT) 2.0 V Reference Bottom Voltage (REFB) 1.0 V SYSTEM PERFORMANCE Specifications include entire signal chain. Gain Range Low Gain (VGA Code = 0) 5.3 dB Maximum Gain (VGA Code = 1023) 40 41.5 dB Gain Accuracy ±1 dB Peak Nonlinearity 500 mV Input Signal 0.1 % 12 dB gain applied. Total Output Noise 0.3 LSB rms AC grounded input, 6 dB gain applied. Power Supply Rejection (PSR) 50 dB Measured with step change on supply.
1 Input signal characteristics defined as follows:
Rev. B | Page 5 of 20 AD9944 SYSTEM SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted. Table 4. Parameter Min Typ Max Unit Conditions CDS Maximum Input Range before Saturation1 1.0 V p-p Allowable CCD Reset Transient1 500 mV See input waveform in footnote. Maximum CCD Black Pixel Amplitude1 100 mV VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range Minimum Gain 5.3 dB See Figure 13 for VGA gain curve. Maximum Gain 40 41.5 dB See Variable Gain Amplifier section for VGA gain equation. BLACK LEVEL CLAMP Clamp Level Resolution 256 Steps Clamp Level Measured at ADC output. Minimum Clamp Level 0 LSB Maximum Clamp Level 255 LSB A/D CONVERTER Resolution 12 Bits Differential Nonlinearity (DNL) ±0.4 LSB No Missing Codes Guaranteed Data Output Coding Straight binary Full-Scale Input Voltage 2.0 V VOLTAGE REFERENCE Reference Top Voltage (REFT) 2.0 V Reference Bottom Voltage (REFB) 1.0 V SYSTEM PERFORMANCE Specifications include entire signal chain. Gain Range Low Gain (VGA Code = 0) 5.3 dB Maximum Gain (VGA Code = 1023) 40 41.5 dB Gain Accuracy ±1 dB Peak Nonlinearity 500 mV Input Signal 0.1 % 12 dB gain applied. Total Output Noise 0.9 LSB rms AC grounded input, 6 dB gain applied. Power Supply Rejection (PSR) 50 dB Measured with step change on supply.
Rev. B | Page 6 of 20 TIMING SPECIFICATIONS CL = 20 pF, fSAMP = 25 MHz. See CCD-mode timing in Figure 14 and Figure 15, and serial timing in Figure 10 and Figure 11. Table 5. Parameter Symbol Min Typ Max Unit SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period tCONV 40 ns DATACLK High/Low Pulse Width tADC 16 20 ns SHP Pulse Width tSHP 10 ns SHD Pulse Width tSHD 10 ns CLPOB Pulse Width1 tCOB 2 20 Pixels SHP Rising Edge to SHD Falling Edge tS1 10 ns SHP Rising Edge to SHD Rising Edge tS2 16 20 ns Internal Clock Delay tID 3.0 ns DATA OUTPUTS Output Delay tOD 9.5 ns Pipeline Delay 9 Cycles SERIAL INTERFACE Maximum SCK Frequency fSCLK 10 MHz SL to SCK Setup Time tLS 10 ns SCK to SL Hold Time tLH 10 ns SDATA Valid to SCK Rising Edge Setup tDS 10 ns SCK Falling Edge to SDATA Valid Hold tDH 10 ns 1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Rev. B | Page 7 of 20 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter (With Respect To) Min Max Unit AVDD (AVSS) −0.3 +3.9 V DVDD (DVSS) −0.3 +3.9 V DRVDD (DRVSS) −0.3 +3.9 V Digital Outputs (DRVSS) −0.3 DRVDD + 0.3 V SHP, SHD, DATACLK (DVSS) −0.3 DVDD + 0.3 V CLPOB, PBLK (DVSS) −0.3 DVDD + 0.3 V SCK, SL, SDATA DVSS (AVSS) −0.3 DVDD + 0.3 V REFT, REFB, CCDIN −0.3 AVDD + 0.3 V Junction Temperature 150 °C Lead Temperature (10 sec) 300 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS The thermal resistance of a 32-Lead LFCSP package (with the exposed bottom pad soldered to the board GND) is θJA = 27.7°C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
24 REFB
23 REFT
22 CCDIN
21 AVSS
20 AVDD
19 SHD
18 SHP
17 CLPOB
27 SCK
26 SDATA
Figure 2. AD9943 Pin Configuration Table 7. AD9943 Pin Function Descriptions 1 to 10 D0 to D9 DO Digital Data Outputs. 11 DRVDD P Digital Output Driver Supply. 12 DRVSS P Digital Output Driver Ground. 14 DATACLK DI Digital Data Output Latch Clock. 15 DVSS P Digital Supply Ground. 16 PBLK DI Preblanking Clock Input. 17 CLPOB DI Black Level Clamp Clock Input. 18 SHP DI CDS Sampling Clock for CCD Reference Level. 19 SHD DI CDS Sampling Clock for CCD Data Level. 22 CCDIN AI Analog Input for CCD Signal. 23 REFT AO A/D Converter Top Reference Voltage Decoupling. 24 REFB AO A/D Converter Bottom Reference Voltage Decoupling. 25 SL DI Serial Digital Interface Load Pulse. 26 SDATA DI Serial Digital Interface Data Input. 27 SCK DI Serial Digital Interface Clock Input. 28 to 30 NC NC Internally pulled down. Float or connect to GND. 31 to 32 NC NC Internally not nonnected. 1 Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
Figure 3. AD9944 Pin Configuration Table 8. AD9944 Pin Function Descriptions 1 to 10 D2 to D11 DO Digital Data Outputs. 11 DRVDD P Digital Output Driver Supply. 12 DRVSS P Digital Output Driver Ground. 14 DATACLK DI Digital Data Output Latch Clock. 15 DVSS P Digital Supply Ground. 16 PBLK DI Preblanking Clock Input. 17 CLPOB DI Black Level Clamp Clock Input. 18 SHP DI CDS Sampling Clock for CCD Reference Level. 19 SHD DI CDS Sampling Clock for CCD Data Level. 22 CCDIN AI Analog Input for CCD Signal. 23 REFT AO A/D Converter Top Reference Voltage Decoupling. 24 REFB AO A/D Converter Bottom Reference Voltage Decoupling. 25 SL DI Serial Digital Interface Load Pulse. 26 SDATA DI Serial Digital Interface Data Input. 27 SCK DI Serial Digital Interface Clock Input. 28 to 30 NC NC Internally pulled down. Float or connect to GND. 31 D0 DO Digital Data Output. 32 D1 DO Digital Data Output. 1 Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
Rev. B | Page 10 of 20 TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore every code must have a finite width. No missing codes guaranteed to 10-bit resolution indicates that all 1024 codes, respectively, must be present over all operating conditions. Peak Nonlinearity Peak nonlinearity, a full-signal chain specification, refers to the peak deviation of the output of the AD9943/AD9944 from a true straight line. The point used as zero scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC’s full-scale range. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship () codesScaleFullADC N2LSB1 = where N is the bit resolution of the ADC. For example, 1 LSB of the AD9943 is 1.95 mV. Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. This represents a very high frequency disturbance on the AD9943/AD9944’s power supply. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage. Internal Delay for SHP/SHD The internal delay (also called aperture delay) is the time delay that occurs from the time a sampling edge is applied to the AD9943/AD9944 until the actual sample of the input signal is held. Both SHP and SHD sample the input signal during the transition from low to high, so the internal delay is measured from each clock’s rising edge to the instant the actual internal sample is taken.
Rev. B | Page 13 of 20 INTERNAL REGISTER MAP All register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (AD9943 = 32 LSB clamp level, and AD9944 = 128 LSB clamp level). Table 9. Address Bits Register Name A2 A1 A0 Data Bits Function Operation 0 0 0 D0 Software Reset (0 = normal operation, 1 = reset all registers to default). D2, D1 Power-Down Modes (00 = normal power, 01 = standby, 10 = total shutdown). D3 OB Clamp Disable (0 = clamp on, 1 = clamp off). D5, D4 Test Mode. Should always be set to 00. D6 PBLK Blanking Level (0 = blank output to zero, 1 = blank to ob clamp level). D8, D7 Test Mode 1. Should always be set to 00. D11 to D9 Test Mode 2. Should always be set to 000. Control 0 0 1 D0 SHP/SHD Input Polarity (0 = active low, 1 = active high). D1 DATACLK Input Polarity (0 = active low, 1 = active high). D2 CLPOB Input Polarity (0 = active low, 1 = active high). D3 PBLK Input Polarity (0 = active low, 1 = active high). D4 Three-State Data Outputs (0 = outputs active, 1 = outputs three-stated). D5 Data Output Latching (0 = latched by DATACLK, 1 = latch is transparent). D6 Data Output Coding (0 = binary output, 1 = gray code output). D11 to D7 Test Mode. Should always be set to 00000. Clamp Level 0 1 0 D7 to D0 OB Clamp Level (AD9943: 0 = 0 LSB, 255 = 63.75 LSB, AD9944: 0 = 0 LSB, 255 = 255 LSB). VGA Gain 0 1 1 D9 to D0 VGA Gain (0 = 6 dB, 1023 = 40 dB).
VGA gain curve is shown in Figure 13. Figure 13. VGA Gain Curve
Figure 16. System Applications Diagram
5 CLOCK
Figure 17. AD9943 Recommended Circuit Configuration for CCD Mode
Figure 18. AD9944 Recommended Circuit Configuration for CCD Mode internal registers and perform internal calibration procedures. normal clock signals and serial write operations may occur. reset operation is completed. separate digital driver supply may be used for DRVDD (Pin 11). output pins may also help reduce noise.
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.80 SEATING
3.50 REF
0.60 MAX
0.25 MIN
Figure 19. 32-Lead Lead Frame Chip Scale Package [LFCSP] registered tra demarks are the prop erty of their respective owners .