AD9929

AD9929 CCD Signal Processor with Precision Timing™ Generator Data Sheet (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 64

Technical content

Precision Timing™ Generator AD9929 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

36 MSPS correlated double sampler (CDS)

12-bit 36 MHz A/D converter On-chip vertical driver for CCD image sensor On-chip horizontal driver for CCD image sensor 6 dB to 40 dB variable gain amplifier (VGA) Black level clamp with variable level control Complete on-chip timing generator Precision Timing core with 0.58 ns resolution 2-phase H-clock modes 4-phase vertical transfer clocks Electronic and mechanical shutter modes On-chip sync generator with external sync option 64-lead, plastic ball, 9 × 9 grid array Pb-free package APPLICATION Digital still cameras Digital video camcorders PRODUCT DESCRIPTION The AD9929 is a highly integrated CCD signal processor for digital still camera and digital video camera applications. It includes a complete analog front end with A/D conversion, combined with a full-function, programmable timing generator. The AD9929 also includes horizontal and vertical clock drivers, which allow direct connection to the CCD image sensor. The AD9929 is specified at pixel rates of up to 36 MHz. The analog front end includes black level clamping, a CDS, a VGA, and a 12-bit A/D converter. The timing generator provides all the necessary CCD clocks: RG-clock, H-clocks, V-clocks, sensor gate pulses, a substrate clock, and a substrate bias pulse. Oper- ation is programmed using a 3-wire serial interface. The AD9929 is packaged in a 64-lead CSPBGA. It is specified over an operating temperature range of −25°C to +85°C. FUNCTIONAL BLOCK DIAGRAM AD9929 CDS VGA CLAMP DCLK1 FD/DCLK2 MSHUT STROBE CLI DOUT VREF 6dB TO 40dB VERTICAL DRIVERS RG H1, H2 V1, V2, V3, V4 REFT REFB PRECISION TIMING GENERATOR SYNC GENERATOR INTERNAL CLOCKS SUBCK HD VD SYNC INTERNAL REGISTERS SL SCKS DI VSUB CCDIN 04593-0-001 HORIZONTAL DRIVERS ADC Figure 1.

Rev. A | Page 2 of 64 TABLE OF CONTENTS Applications Where the CLI Clock Frequency Changes

REVISION HISTORY

2/04—Data Sheet Changed from Rev. 0 to Rev. A 1/04—Revision 0: Initial Version

Rev. A | Page 3 of 64 SPECIFICATIONS Table 1. Parameter Min Typ Max Unit TEMPERATURE RANGE Operating −25 +85 °C Storage −65 +150 °C POWER SUPPLY VOLTAGE AVDD (AFE Analog Supply) 2.7 3.0 3.6 V TCVDD (Timing Core Analog Supply) 2.7 3.0 3.6 V RGVDD (RG Driver) 2.7 3.0 3.6 V HVDD (H1 to H2 Drivers) 2.7 3.0 3.6 V DRVDD (Data Output Drivers) 2.7 3.0 3.6 V DVDD (Digital) 2.7 3.0 3.6 V VERTICAL DRIVER SUPPLY VOLTAGE VDD (Vertical Driver Input Logic Supply) 2.7 3.0 3.6 V VH1, VH2 (Vertical Driver High Supply) 11.5 15.0 16.0 V VM1, VM2 (Vertical Driver Mid Supply) −1.0 0.0 1.0 V VL (Vertical Driver Low Supply for 3 Level and 2 Level) −9.0 −7.5 −5.0 V AFETG POWER DISSIPATION

36 MHz, Typ Supply Levels, 100 pF H1 to H2 Loading 180 mW

Power from HVDD Only1 36 mW Power-down Mode (AFE and Digital in Standby Operation) 1 mW VERTICAL DRIVER POWER DISSIPATION2 (6000 pF V1 to V4 Loading, 1000 pF SUBCK Loading) Power from VDD <1.0 mW Power from VH1 23.0 mW Power from VH2 15.0 mW Power from VL 42.0 mW MAXIMUM CLOCK RATE (CLI) AD9929 36 MHz

1 The total power dissipated by the HVDD supply may be approximated by using the equation:

Total HVDD Power = [CLOAD × HVDD × Pixel Frequency] × HVDD × Number of H-Outputs Used. Actual HVDD power may be slightly different than the calculated value because of the stray capacitance inherent in the PCB layout/routing. 2 Vertical driver loads used when characterizing power consumption. Note: actual power depends on the V1 to V4 timing and number of SUBCKs. 04593-0-002 V1, V2, V3, V4 6000 pF SUBCK 1000 pF 500mV TYP RESET TRANSIENT 100mV MAX OPTICAL BLACK PIXEL 1V MAX INPUT SIGNAL RANGE INPUT SIGNAL CHARACTERISTICS DEFINED AS FOLLOWS:

Table 3. AVDD = 3.0 V, fCLI = 36 MHz, TMIN to TMAX, unless otherwise noted. Allowable CCD Reset Transient 500 mV See input signal characteristics in Table 1. Clamp Level LSB LSB measured at ADC output. SYSTEM PERFORMANCE Includes entire signal chain. Peak Nonlinearity, 500 mV Input Signal 0.1 % 12 dB gain applied. Total Output Noise 0.3 LSB rms AC grounded input, 6 dB gain applied. Power Supply Rejection (PSR) 40 dB Measured with step change on supply.

Table 4. CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted. 1 Parameter is programmable. Table 5. V1 to V4 load = no load, SUBCK load = no load, VDD = 3.0 V, VL = −7.5 V, VH1 = VH2 = +15.0 V, VM1 = VM2 = GND, fCLI = 36 MHz, unless otherwise noted.

Rev. A | Page 6 of 64 Parameter Symbol Min Typ Max Unit V2 and V4 Outputs (See Figure 43) Delay Times VL to VM2 t PLM2 100 ns VM2 to VL t PML2 50 ns Rise Times VL to VM2 t R3 500 ns Fall Times VM2 to VL t F3 500 ns Output Currents V2 or V2 @ VL =−7.25 V 10.0 mA V2 or V4 @ VM2 = −0.25 V −5.0 mA SUBCK Output (See Figure 44) Delay Times VL to VH2 t PLH 100 ns VH2 to VL t PHL 50 ns Rise Times VL to VH2 t R4 90 ns Fall Times VH2 to VL t F4 90 ns Output Currents SUBCK @ VL = −7.25 V 5.4 mA SUBCK @ VH2 = 14.75 V −4.0 mA

Rev. A | Page 7 of 64 TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. “No missing codes guaranteed to 12-bit resolution” indicates that all 4096 codes, respectively, must be present over all operating conditions. Peak Nonlinearity Peak nonlinearity, a full signal-chain specification, refers to the peak deviation of the output of the AD9929 from a true straight line. The point used as zero scale occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 and 1/2 LSB beyond the last code transition. The deviation is mea- sured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appro- priately gained up to fill the ADC’s full-scale range. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSBs, and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship

1 LSB = (ADC full scale/2

N codes) when N is the bit resolution of the ADC. For the AD9929, 1 LSB is 0.5 mV . Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.

Rev. A | Page 8 of 64 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter With Respect To Min Max Unit VDD VDVSS VDVSS − 0.3 VDVSS + 4.0 V VL VDVSS VDVSS − 10.0 VDVSS + 0.3 V VH1, VH2 VDVSS VL –0.3 VL + 27.0 V VM1, VM2 VDVSS VL – 0.3 VL + 27.0 V AVDD AVSS −0.3 +3.9 V TCVDD TCVSS −0.3 +3.9 V HVDD HVSS −0.3 +3.9 V RGVDD RGVSS −0.3 +3.9 V DVDD DVSS −0.3 +3.9 V DRVDD DRVSS −0.3 +3.9 V RG Output RGVSS −0.3 RGVDD + 0.3 V H1 to H2 Output HVSS −0.3 HVDD + 0.3 V Digital Outputs DVSS −0.3 DVDD + 0.3 V Digital Inputs DVSS −0.3 DVDD + 0.3 V SCK, SL, SDATA DVSS −0.3 DVDD + 0.3 V REFT, REFB AVSS −0.3 AVDD + 0.3 V CCDIN AVSS −0.3 AVDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Resistance θJA = 61.0 °C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulates on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 2. Pin Configuration Table 7. Pin Function Descriptions

1 AI = Analog Input, AO = Analog Output, DI = Digital Input,

DO = Digital Output, DIO = Digital Input/Output, P = Power.

Table 8. Control Register Address Map

Rev. A | Page 12 of 64 Address Content Bit Width Default Value Register Name Register Description 0x0A 23 1 0 Unused 22 1 0 FDPOL FD Polarity Control (0 = Low, 1 = High) (21:16) 6 0x00 XVSGMASK XVSG Masking (See Table 25) (VD (15:12) 4 0 SYNCCNT External SYNC Setting SyncReg)1 (11:10) 2 0 SVREP_MODE Super Vertical Repetition Mode 9 1 0 HBLKEXT H Pulse Blanking Extend Control 8 1 0 HPULSECNT H Pulse Control During Blanking (7:4) 4 C SPATLOGIC SPAT Logic Setting (See Table 27) (3:2) 2 3 SVOS Second V Output Setting (10 = Ouput Repetition 1) 1 1 0 SPAT_EN SPAT Control (0 = SPAT Disable, 1 = SPAT Enable) 0 1 0 MODE Mode Contro l Bit (0 = Mode_A, 1 = Mode_B) 0x0B (23:22) 2 0 Unused 21 1 1 XSUBCK_EN XSUBCK Output Enab le Control (0 = Disable, 1 = Enable) 20 1 1 XVSG_EN XVSG Output Enable Control (0 = Disable, 1 = Enable) (VD (19:17) 3 0 Unused SyncReg)1 16 1 0 STROBE_EN STROBE Output Control (0 = STROBE Output Held Low, 1 = STROBE Output Enabled) 15 1 0 Unused (14:12) 3 0 XSUBCKNUM_HP High Prec ision Shutter XSUBCLK Pulse Position/Number 11 1 0 Unused (10:0) 11 0x7FF XSUBCKNUM To tal Number of XSUBCKs Per Field 0x0C (23:21) 3 0 Unused 20 1 0 MSHUTINIT MSHUT Init ialize (1 = Forces MSHUT Low) (19:18) 2 0 Unused (VD 17 1 0 Unused SyncReg)1 16 1 0 MSHUTEN MSHUT Control (0 = MSHUT Held at Last State, 1 = MSHUT Output) 15 1 0 Unused (14:12) 3 0 MSHUTPOS_HP MSHUT Posi tion during High Precision Operation 11 1 0 Unused (10:0) 11 0x000 MSHUTPOS MSHUT Position during Normal Operation 0x0D (23:17) 7 – Unused 16 1 0 VSUBPOL VSUB Active Polarity (0 = Low, 1 = High) (VD (15:11) 5 – Unused SyncReg)1 (10:0) 11 0x000 VSUBTOG VSUB Toggle Posi tion. Active Starting Line in any Field. 0x0E (23:22) 2 0 Unused (21:20) 2 0 TESTMODE1 This Re gister Should Always Be Set = 0. (19:18) 2 0 Unused (VD 17 1 0 TESTMODE2 This Regi ster Should Always Be Set = 0. SyncReg)1 16 1 0 TESTMODE3 This Regist er Should Always Be Set = 0. (15:10) 6 0x00 Unused (9:0) 10 0x000 VGAGAIN VGA Gain 0x0F (23:8) 16 0 Unused (7:0) 8 60 XVSGLEN_1 XVSGTOG_1 Pulse Width 0x17 (23:13) 11 – Unused (12:0) 13 0x1FFF XV1SPAT_TOG1 XV1SPAT Toggle Position #1 (Mode_A Active) 0x18 (23:13) 11 – Unused (12:0) 13 0x1FFF XV1SPAT_TOG2 XV1SPAT Toggle Position #2 (Mode_A Active) 0x19 (23:13) 11 – Unused (12:0) 13 0x1FFF XV2SPAT_TOG1 XV2SPAT Toggle Position #1 (Mode_A Active) 0x1A (23:13) 11 – Unused (12:0) 13 0x1FFF XV2SPAT_TOG2 XV2SPAT Toggle Position #2 (Mode_A active)

Rev. A | Page 13 of 64 Address Content Bit Width Default Value Register Name Register Description 0x1B (23:13) 11 – Unused (12:0) 13 0x1FFF XV3SPAT_TOG1 XV3SPAT Toggle Position #1 (Mode_A active) 0x1C (23:13)) 11 – Unused (12:0 13 0x1FFF XV3SPAT_TOG2 XV3SPAT Toggle Position #2 (Mode_A active) 0x1D (23:13) 11 – Unused (12:0) 13 0x1FFF XV4SPAT_TOG1 XV4SPAT Toggle Position #1 (Mode_A active) 0x1E (23:13) 11 – Unused (12:0) 13 0x1FFF XV4SPAT_TOG2 XV4SPAT Toggle Position #2 (Mode_A Active) 0x1F (23:13) 11 – Unused (12:0) 13 0x1FFF XV1SPAT_TOG1 XV1SPAT Toggle Position #1 (Mode_A Active) 0x20 (23:13) 11 – Unused (12:0) 13 0x1FFF XV1SPAT_TOG2 XV1SPAT Toggle Position #2 (Mode_B Active) 0x21 (23:13) 11 – Unused (12:0) 13 0x1FFF XV2SPAT_TOG1 XV2SPAT Toggle Position #1 (Mode_B Active) 0x22 (23:13) 11 – Unused (12:0) 13 0x1FFF XV2SPAT_TOG2 XV2SPAT Toggle Position #2 (Mode_B Active) 0x23 (23:13) 11 – Unused (12:0) 13 0x1FFF XV3SPAT_TOG1 XV3SPAT Toggle Position #1 (Mode_B Active) 0x24 (23:13) 11 – Unused (12:0) 13 0x1FFF XV3SPAT_TOG2 XV3SPAT Toggle Position #2 (Mode_B Active) 0x25 (23:13) 11 – Unused (12:0) 13 0x1FFF XV4SPAT_TOG1 XV4SPAT Toggle Position #1 (Mode_B Active) 0x26 (23:13) 11 – Unused (12:0) 13 0x1FFF XV4SPAT_TOG2 XV4SPAT Toggle Position #2 (Mode_B Active) 0xD5 (23:4) 20 0x00000 Unused 3 1 1 DCLK2SEL DCLK2 Selector (0 = Select Internal FD Signal To Be Output on FD/DCLK2 Pin 16, 1 = Select CLI To Be Output on FD/DCLK2 Pin 16) 2 1 0 DCLK1SEL DCLK1 Selector (0 = Select DLL Version for DCLK1 Output, 1 = Select CLI for DCLK1 Output) (1:0) 2 0 CLKDIV Input Clock Divider (0 = No Division, 1 = 1/2, 2 = 1/3, 3 = 1/4) 0xD6 (23:1) 23 0x000000 Unused 0 1 1 SLAVE_MODE Operating Mode ( 0 = Master Mode, 1 = Slave Mode) 1 This register defaults to VD synchronous mode type at power-up. VD sync type registers do not get updated until the first falling edge of VD is asserted after the register has been programmed. VD sync type registers can be programmed to be asynchronous registers by setting VDMODE = 1 (Address 0x01).

Table 9. System Register Address Map (Address 0x14)

Rev. A | Page 15 of 64 Register Content Bit Width Default (Decimal) Register Name Register Description Sys_Reg(9) (31:23) 9 89 VTPLEN3 Vertical Sequence #3: Length Between Repetitions 22 1 0 XV1STARTPOL3 Vertical Sequence #3: XV1 Start Polarity 21 1 0 XV2STARTPOL3 Vertical Sequence #3: XV2 Start Polarity 20 1 1 XV3STARTPOL3 Vertical Sequence #3: XV3 Start Polarity 19 1 1 XV4STARTPOL3 Vertical Sequence #3: XV4 Start Polarity (18:10) 9 0 XV1TOG1POS3 Vertical Se quence #3: XV1 Toggle Position 1 (9:1) 9 60 XV1TOG2POS3 Vertical Sequ ence #3: XV1 Toggle Position 2 0 1 XV2TOG1POS3 [8] Sys_Reg(10) (31:24) 8 30 XV2TOG1POS3 [7:0] Vert ical Sequence #3: XV2 Toggle Position 1 (23:15) 9 90 XV2TOG2POS3 Vertical Se quence #3: XV2 Toggle Position 2 (14:6) 9 0 XV3TOG1POS3 Vertical Se quence #3: XV3 Toggle Position 1 (5:0) 6 XV3TOG2POS3 [8:3] Sys_Reg(11) (31:29) 3 60 XV3TOG2POS3 [2:0] Vert ical Sequence #3: XV3 Toggle Position 2 (28:20) 9 30 XV4TOG1POS3 Vertical Se quence #3: XV4 Toggle Position 1 (19:11) 9 90 XV4TOG2POS3 Vertical Se quence #3: XV4 Toggle Position 2 (10:1) 10 0 HBLKHPOS H1 Pulse ON Po sition during Blanking Period 0 1 – Unused Sys_Reg(12) (31:20) 12 2283 HDLEN 1 12-bit Gray Code HD Counter Value (Gray Code Number) (19:10) 10 130 HLEN 10-Bit HL Counter Values (9:1) 9 100 OLEN 9-Bit OL Counter Value 0 1 BLLEN [8] Sys_Reg(13) (31:24) 8 0 BLLEN [7:0] 9-bit BL Counter Value (23:16) 8 118 MSHUTLEN MSHUT Sequence Length (15:5) 11 1048 XVSGTOG_0 XVSGTOG_0 Toggle Position (4:0) 5 XVSGTOG_1 [10:6] Sys_Reg(14) (31:26) 6 1198 XVSGTOG_1 [5:0] XVSG TOG_1 Toggle Position (25:18) 8 60 XVSGLEN_0 XVSGTOG_0 Pulse Width (17:9) 9 19 XSUBCK1TOG1 XS UBCK1 1st Toggle Position (8:0) 9 88 XSUBCK1TOG2 XSUB CK1 2nd Toggle Position Sys_Reg(15) (31:23) 9 19 XSUBCK2T OG1 XSUBCK2 1st Toggle Position (22:14:) 9 88 XSUBCK2TOG2 XS UBCK2 2nd Toggle Position (13:2) 12 2243 CLPTOG1 1 CLPOB Toggle Position 1 (Gray Code Number) (1:0) 2 CLPTOG2 [11]1 Sys_Reg(16) (31:22) 10 2278 CLPTOG2 [10:0] 1 CLPOB Toggle Position 2 (Gray Code Number) (21:18) 4 9 VDRISE VD Toggle Position 1 (17:8) 10 120 HDRISE HD Toggle Position 2 (7:0) 8 – Unused 1 Register value must be a gray code number (see Gray Code Registers section).

Table 10. Mode_A Register Map (Address 0x15) 1 Register value must be a gray code number (see Gray Code Registers section).

Table 11. Mode_B Register Map (Address 0x16) 1 Register value must be a gray code number (See Gray Code Registers section).

(SCK), serial load (SL), and serial data (SDATA). Table 13. Types of Serial Interface Registers Addresses Are Used. See Table 8. successive writes to control registers. register map is listed in Table 9. low during access to system registers, as shown in Figure 11.

1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
3. THIS TIMING PATTERN MUST BE WRITTEN FOR EACH REGISTER WRITE WITH SL REMAINING HIGH FOR AT

LEAST ONE FULL SCK PERIOD BEFORE ASSERTING SL LOW AGAIN FOR THE NEXT REGISTER WRITE. Figure 10. 3-Wire Serial Interface Timing for Control Registers

8 BIT ADDRESS NUMBER OF 32 BIT

1. SL PULSES ARE IGNORED UNTIL THE LSB BIT OF THE LAST DATA N WORD IS CLOCKED IN.
2. VALID SL PULSE. SL MUST BE ASSERTED HIGH WHEN ALL SDI DATA TRANSMISSIONS HAVE BEEN FINISHED.

Figure 11. System and Mode Register Writes Figure 12. VD Synchronous Type Register Writes Table 8. Register writes to synchronous and asynchronous register operation begins. See Figure 12. 0x0E. Also see Table 8, the Control Register Address Map.

The AD9929 AFE signal processing chain is shown in Figure 13. AFE section are listed in Table 14. Table 14. AFE Registers achieving the best performance from the CCD. Figure 13. AFE Block Diagram

crossover voltage is not programmable.

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6ns TYP).

1 PIXEL

Figure 15. High Speed Clock Resolution from CLI Master Clock Input

1. RG RISING EDGE (FIXED EDGE AT 000000)
2. RG FALLING EDGE (RGNEGLOC (ADDRESS 0x03))
3. SHP SAMPLE LOCATION (SHPLOC (ADDRESS 0x02))
4. SHD SAMPLE LOCATION (SHDLOC (ADDRESS 0x02))
5. H1 RISING EDGE LOCATION (H1POSLOC (ADDRESS 0x03))
6. H1 NEGATIVE EDGE LOCATION (FIXED AT (H1POSLOC + 24 STEPS))
7. H2 IS ALWAYS THE INVERSE OF H1

Figure 16. High Speed Clock Programmable Locations Table 15. RG, H1, SHP, SHD, DCLK, and DOUTPHASE Timing Parameters

1 The two MSB bits are used to select the quadrant

Table 16. Precision Timing Edge Locations for RG, H1, SHP, SHD, DCLK, and DOUTPHASE

01 P[16] P[36]

10 P[26] P[06]

11 P[36] P[16]

function of the SYNCCNT register is described in Table 17. synchronization with SYNCPOL = 0. Table 17. External Synchronization (Master Mode)

0 Disable External Synchronization

1 VD Sync at every SYNC Pulse

2 VD Sync after 2nd Applied SYNC Pulse

3 VD Sync after 3rd Applied SYNC Pulse

4 VD Sync after 4th Applied SYNC Pulse

5 VD Sync after 5th Applied SYNC Pulse

6 VD Sync after 6th Applied SYNC Pulse

7 VD Sync after 7th Applied SYNC Pulse

8 VD Sync after 8th Applied SYNC Pulse

9 VD Sync after 9th Applied SYNC Pulse

10 VD Sync after 10th Applied SYNC Pulse

11 VD Sync after 11th Applied SYNC Pulse

12 VD Sync after 12th Applied SYNC Pulse

13 VD Sync after 13th Applied SYNC Pulse

14 VD Sync after 14th Applied SYNC Pulse

15 VD Sync after 1st Applied SYNC Pulse Only

4 CLI

2 CLIMIN

4 CLI 4 CLI

Figure 20. Example of Synchronization with SYNCPOL = 0 and SYNCCNT = 1 Figure 21. Example of Synchronization with SYNCPOL = 0 and CYNCCNT = 3

sets HL as a reference for the rising edge of the HD pulse. Table 18. HD and VD Registers 1 Register value must be a gray code number (see Gray Code Registers section).

1. THE SET-UP DELAY IS 4 CLI CYCLES. THE ACTUAL LENGTH OF ONE LINE IS 4 MORE CYCLES

THAN VALUE SET IN HDLEN AND HDLASTLEN DUE TO SET-UP DELAY.

1. VDRISE REFERENCES THE 11-BIT VD-COUNTER.
2. HDRISE REFERENCES THE 10-BIT HL-CONTER.

Figure 22. VD and HD Horizontal Timing

1. CLPTOG2 (SYS_REG (15 AND 16))

Figure 25. Location of CLPOB using CLPTOG1 and CLPTOG2 Registers.

1. THE INTERNAL CLPMASK SIGNAL EXTENDS ONE EXTRA HD CYCLE FROM WHEN THE CLPMASK PERIOD CHANGES FROM LOW TO HIGH.

AS A RESULT, ONE ADDITIONAL CLPOB PULSE IS MASKED AS SHOWN AT POSITIONS A AND B. Figure 26. CLPOB Outputs with CLPMODE = 0 the first line of the following CCD region. Table 20. SCP and CLPEN

1 SCP0 is not a programmable register and therefore not listed in the register

Figure 34. Steps 3 and 4: An Example of Building an Entire Field Readout by Assigning Sequences to Multiple CCD Regions

Rev. A | Page 37 of 64 Table 22. XV1 to XV4 Registers to Configure XXV1 to XXV4 Pulses for each VTP Pattern

Description

VTPLEN0 9 Sys_Reg(1) V Counter 0–511 Length between Repetitions XV1STARTPOL0 1 Sys_Reg(1) High/Low XV1 Starting Polarity for VTP0 (0 = Low, 1 = High) XV2STARTPOL0 1 Sys_Reg(1) High/Low XV2 Starting Polarity for VTP0 (0 = Low, 1 = High) XV3STARTPOL0 1 Sys_Reg(1) High/Low XV3 Starting Polarity for VTP0 (0 = Low, 1 = High) XV4STARTPOL0 1 Sys_Reg(1) High/Low XV4 Starting Polarity for VTP0 (0 = Low, 1 = High) XV1TOG1POS0 9 Sys_Reg(1) V Counter 0–511 XV1 Toggle Position 1 for VTP0 XV1TOG2POS0 9 Sys_Reg(1) V Counter 0–511 XV1 Toggle Position 2 for VTP0 XV2TOG1POS0 9 Sys_Reg(1 & 2) V Counte r 0–511 XV2 Toggle Position 1 for VTP0 XV2TOG2POS0 9 Sys_Reg(2) V Counter 0–511 XV2 Toggle Position 2 for VTP0 XV3TOG1POS0 9 Sys_Reg(2) V Counter 0–511 XV3 Toggle Position 1 for VTP0 XV3TOG2POS0 9 Sys_Reg(2 & 3) V Counte r 0–511 XV3 Toggle Position 2 for VTP0 XV4TOG1POS0 9 Sys_Reg(3) V Counter 0–511 XV3 Toggle Position 1 for VTP0 XV4TOG2POS0 9 Sys_Reg(3) V Counter 0–511 XV3 Toggle Position 2 for VTP0 VTP0 VTPLEN1 9 Sys_Reg(3) V Counter 0–512 Length between Repetitions XV1STARTPOL1 1 Sys_Reg(3) High/Low XV1 Starting Polarity for VTP1 (0 = Low, 1 = High) XV2STARTPOL1 1 Sys_Reg(3) High/Low XV2 Starting Polarity for VTP1 (0 = Low, 1 = High) XV3STARTPOL1 1 Sys_Reg(4) High/Low XV3 Starting Polarity for VTP1 (0 = Low, 1 = High) XV4STARTPOL1 1 Sys_Reg(4) High/Low XV4 Starting Polarity for VTP1 (0 = Low, 1 = High) XV1TOG1POS1 9 Sys_Reg(4) V Counter 0–511 XV1 Toggle Position 1 for VTP1 XV1TOG2POS1 9 Sys_Reg(4) V Counter 0–511 XV1 Toggle Position 2 for VTP1 XV2TOG1POS1 9 Sys_Reg(4 V Counter 0– 511 XV2 Toggle Position 1 for VTP1 XV2TOG2POS1 9 Sys_Reg(4 & 5) V Counte r 0–511 XV2 Toggle Position 2 for VTP1 XV3TOG1POS1 9 Sys_Reg(5) V Counter 0–511 XV3 Toggle Position 1 for VTP1 XV3TOG2POS1 9 Sys_Reg(5) V Counter 0–511 XV3 Toggle Position 2 for VTP1 XV4TOG1POS1 9 Sys_Reg(5 & 6) V Counte r 0–511 XV3 Toggle Position 1 for VTP1 XV4TOG2POS1 9 Sys_Reg(6) V Counter 0–511 XV3 Toggle Position 2 for VTP1 VTP1 VTPLEN2 9 Sys_Reg(6) V Counter 0–512 Length between Repetitions XV1STARTPOL2 1 Sys_Reg(6) High/Low XV1 Starting Polarity for VTP2 (0 = Low, 1 = High) XV2STARTPOL2 1 Sys_Reg(6) High/Low XV2 Starting Polarity for VTP2 (0 = Low, 1 = High) XV3STARTPOL2 1 Sys_Reg(6) High/Low XV3 Starting Polarity for VTP2 (0 = Low, 1 = High) XV4STARTPOL2 1 Sys_Reg(6) High/Low XV4 Starting Polarity for VTP2 (0 = Low, 1 = High) XV1TOG1POS2 9 Sys_Reg(6) V Counter 0–511 XV1 Toggle Position 1 for VTP2 XV1TOG1POS2 9 Sys_Reg(7) V Counter 0–511 XV1 Toggle Position 1 for VTP2 XV1TOG2POS2 9 Sys_Reg(7) V Counter 0–511 XV1 Toggle Position 2 for VTP2 XV2TOG1POS2 9 Sys_Reg(7) V Counter 0–511 XV2 Toggle Position 1 for VTP2 XV3TOG1POS2 9 Sys_Reg(7 & 8) V Counte r 0–511 XV3 Toggle Position 1 for VTP2 XV3TOG2POS2 9 Sys_Reg(8) V Counter 0–511 XV3 Toggle Position 2 for VTP2 XV4TOG1POS2 9 Sys_Reg(8) V Counter 0–511 XV3 Toggle Position 1 for VTP2 XV4TOG2POS2 9 Sys_Reg(8) V Counter 0–511 XV3 Toggle Position 2 for VTP2 VTP2

Rev. A | Page 38 of 64 Register Name Bit Width Register Type Reference Counter Range VTPLEN3 9 Sys_Reg(9) V Counter 0–512 Length between Repetitions XV1STARTPOL3 1 Sys_Reg(9) High/Low XV1 Starting Polarity for VTP3 (0 = Low, 1 = High) XV2STARTPOL3 1 Sys_Reg(9) High/Low XV1 Starting Polarity for VTP3 (0 = Low, 1 = High) XV3STARTPOL3 1 Sys_Reg(9) High/Low XV1 Starting Polarity for VTP3 (0 = Low, 1 = High) XV4STARTPOL3 1 Sys_Reg(9) High/Low XV1 Starting Polarity for VTP3 (0 = Low, 1 = High) XV1TOG1POS3 9 Sys_Reg(9) V Counter 0–511 XV1 Toggle Position 1 for VTP3 XV1TOG2POS3 9 Sys_Reg(9) V Counter 0–511 XV1 Toggle Position 2 for VTP3 XV2TOG1POS3 9 Sys_Reg(9 &10) V Counte r 0–511 XV2 Toggle Position 1 for VTP3 XV2TOG2POS3 9 Sys_Reg(10) V Counter 0–511 XV2 Toggle Position 2 for VTP3 XV3TOG1POS3 9 Sys_Reg(10) V Counter 0–511 XV3 Toggle Position 1 for VTP3 XV3TOG2POS3 9 Sys_Reg(10&11) V Counter 0–511 XV3 Toggle Position 2 for VTP3 XV4TOG1POS3 9 Sys_Reg(11) V Counter 0–511 XV3 Toggle Position 1 for VTP3 XV4TOG2POS3 9 Sys_Reg(11) V Counter 0–511 XV3 Toggle Position 2 for VTP3 VTP3 Table 23. Mode_A and Mode_B Registers for VTPx Selection 1 Register settings 6 and 7 are not used. Table 24. Mode_A and Mode_B Registers for CCD Region Selection

SPATLOGIC settings and operation. low and then toggles high at the first XVxSPAT_TOG1 position. XVxSPAT_TOG3 = XVxSPAT_TOG4 = 0x1FFF. Table 26. HD and VD Registers

Table 27. SPATLOCIC Register (Address 0x0A)

required for programming of XSUBCK pulses for each mode. gate, as specified by XVSGACTLINE (Mode_Reg(1)). XSUBCKSUPPRESS = 1, as shown in Figure 50. modes, known as single pulse mode and multiple pulse mode. Table 33. Single and Multiple Pulse Mode

1 Position #1 1 additional pulse

2 Position #2 2 additional pulses

3 Position #3 3 additional pulses

4 Position #4 4 additional pulses

5 Position #5 5 additional pulses

6 Position #6 6 additional pulses

7 Position #7 7 additional pulses

Table 34. XSUBCK Registers Pulses Number of XSUBCK Pulses per Field.

1. XVSGTOG_x (x = 0, 1) REFERENCES THE 13-BIT ST COUNTER
2. XVSGACTLINE (PROGRAMMABLE AT MODE_REG(1))
3. XVSGLEN (PROGRAMMABLE AT SYS_REG(14))
4. XVSGTOG_0 (PROGRAMMABLE AT SYS_REG(13))
5. XVSGTOG_1 (PROGRAMMABLE AT SYS_REG(13))

Figure 55. Example of VSG Pulse

2 LINES 3 LINES

Figure 56. VSUB Timing Example an example of controlling VSUB using these registers. Table 36. VSUB Registers VSUB on and off toggle positions and polarity.

1. Program VSUBTOG = 2 and VSUBPOL = 1.
2. Since the VSUBTOG and VSUBPOL are VD synchronous
3. VSUB is asserted high after two HD cycles.
4. Program VSUBTOG = 3 and VSUBPOL = 0.
5. Since the VSUBTOG and VSUBPOL are VD synchronous
6. VSUB is asserted low after three HD cycles.

Table 38 describes the state of the digital I/Os for different operating conditions. Table 38. I/O Levels 1 OUTCONT_REG is a register setting located at Address 0x05. It defaults to 0 at power-up. 2 VD and HD operate in master mode.

recommended (refer to Figure 66 for each step).

1. Turn on power supplies as described in the Power Supply
2. Apply the CLI master clock input.

CLI is output on DCLK2 Pin 16 at this time.

1. Reset the internal AD9929 registers. Write a 0x000000 to
2. Program DIGSTBY and AFESTBY registers (Address 0x05)

= 1 and all other necessary control registers.

1. Program system registers (Address 0x20).
2. Program Mode_A registers (Address 0x21).
3. Program Mode_B registers (Address 0x22).
4. Program OUTCONT_REG register (Address 0x05) = 1.
5. Program control register MODE (Address 0x0A) = 0. This
6. Program control register MODE (Address 0x0A) = 1. This

least 4 CLI cycles before the start of the next field. 1OUTCONT IS AN INTERNAL SIGNAL THAT IS CONTROLLED USING REGISTER OUTCONT_REG (ADDRESS 0x05). 2DCLK2 WILL BE OUTPUT ON THE FD/DCLK2 PIN 16 PROVIDING REGISTER DCLK2SEL (ADDRESS 0xD5) = 1. THE DCLK2SEL REGISTER DEFAULTS TO 1 AT POWER-UP. 3IT TAKES 11 CLI CLOCKS FROM WHEN OCONT GOES HIGH UNTIL VD, HD, AND DIGITAL OUTPUT DATA IS VALID. 4THERE IS A 500µS SETTLING TIME FROM WHEN THE DIGSTBY REGISTER IS SET TO WHEN THE DCLK1 IS STABLE. Figure 66. Recommended Start-Up Sequence and Synchronization, Master Mode

ing sequence is recommended (refer to Figure 67 for each step).

1. Program OUTCONT_REG (Address 0x05) = 0. This

digital outputs to become disabled.

1. Program registers AFESTBY (Address 0x05) = 0 and
2. When ready to come out of standby operation, program
3. Program necessary control registers.
4. Program control register MODE (Address 0x0A) = 0. This
5. Program register OUTCONT_REG (Address 0x05) = 1.

all digital outputs to become active. 1DCLK2 WILL BE OUTPUT ON THE FD/DCLK2 PIN 16 PROVIDING REGISTER DCLK2SEL (ADDRESS 0xD5) = 1. 2IT TAKES 11 CLI CLOCKS FROM WHEN OCONT GOES HIGH UNTIL VD, HD, AND DIGITAL OUTPUT DATA IS VALID. Figure 67. Recommended Standby Sequence

sequence is recommended (refer to Figure 68 for each step).

1. Program OUTCONT_REG (Address 0x05) = 0.
2. Program registers AFESTBY (Address 0x05) = 0 and
3. Remove power from AD9929.

1DCLK2 WILL BE OUTPUT ON THE FD/DCLK2 PIN 16 PROVIDING REGISTER DCLK2SEL (ADDRESS 0xD5) = 1. Figure 68. Recommended Shut-Down Sequence

after any changes in the CLI clock frequency. *IT TAKES 4 CLI CLOCK CYCLES FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD AND DIGITAL OUTPUT DATA IS VALID. Figure 69. Reset Sequence That Must Be Applied when Changing the CLI Clock Frequency During Operation

1. RECOMMENDED PLACEMENT FOR CLI RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
3. OUTPUT DATA LATENCY IS NINE CYCLES.

Figure 70. Output Data Pipeline Delay

Rev. A | Page 60 of 64 CIRCUIT LAYOUT INFORMATION The AD9929 typical circuit connection is shown in Figure 71. The PCB layout is critical in achieving good image quality from the AD9929 product. All of the supply pins must be decoupled to ground with good quality, high frequency chip capacitors. The 0.1 µF decoupling capacitors should be located as close as possible to the supply pins, and should have a very low induc- tance path to a continuous ground plane. There should also be a 4.7 µF or larger capacitor for each main supply, although it is not necessary for each individual pin. In most applications it is easier and recommended to share the same supply for AVDD, DVDD, TCVDD, RGVDD, and HVDD, as long as the individual supply pins are separately bypassed at each supply pin. A separate 3 V supply should be used for DRVDD with this supply pin decoupled to the same ground plane as the rest of the chip. A separate ground for DRVSS is not recommended. The vertical driver VM supply pins can be connected to indi- vidual supplies or to the same supply, depending on the appli- cation requirement for the mid-level voltage on the vertical outputs. These pins may also be directly connected to the common ground plane, as shown in Figure 71. The analog bypass pins, REFB, REFT, should also be carefully decoupled to ground as close as possible to their respective pins. The analog input, CCDIN, capacitor should also be located close to the pin. The H1, H2, and RG printed circuit board traces should be designed to have low inductance to avoid excessive distortion of the signals. Heavier traces are recommended because of the large transient current demand by the CCD on H1 and H2. If possible, physically locate the AD9929 close to the CCD to reduce the inductance on these lines. As always, the routing path should be as direct as possible from the AD9929 to the CCD. Careful trace impedance considerations must also be made with applications using a flex printed circuit (FPC) con- necting the CCD to the AD9929. FPC trace impedances can be controlled by applying a solid uniform ground plane under the H1, H2, and RG traces. This helps minimize the amount of overshoot and ringing on these signals at the CCD inputs.

3 SERIAL

5 V1-V4, SUBCK

Figure 71. AD9929 Typical Circuit Configuration

0.25 MIN

9.00 BSC SQ

7.20 BSC

0.12 MAX

Figure 72. 64-Lead Chip Scale Ball Grid Array [CSPBGA]

Rev. A | Page 63 of 64 NOTES

Rev. A | Page 64 of 64 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D04593-0-1/04(A)