AD9920ABBCZRL

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12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator AD9920A Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.

FEATURES

Integrated 19-channel V-driver

1.8 V AFETG core

24 programmable vertical clock signals Correlated double sampler (CDS) with −3 dB, 0 dB, +3 dB, and +6 dB gain 12-bit, 40.5 MHz analog-to-digital converter (ADC) Black level clamp with variable level control Complete on-chip timing generator Precision Timing core with ~400 ps resolution On-chip 3 V horizontal and RG drivers General-purpose outputs (GPOs) for shutter and system support On-chip sync generator with external sync input On-chip 1.8 V low dropout (LDO) regulator 105-ball, 8 mm × 8 mm CSP_BGA package

APPLICATIONS

The AD9920A is a highly integrated charge-coupled device (CCD) signal processor for digital still camera applications. It includes a complete analog front end (AFE) with analog-to-digital conversion, combined with a full-function programmable timing generator and 19-channel vertical driver (V-driver). The timing generator is capable of supporting up to 24 vertical clock signals to control advanced CCDs. The on-chip V-driver supports up to 19 channels for use with six-field CCDs. A Precision Timing® core allows adjust- ment of high speed clocks with approximately 400 ps resolution at 40.5 MHz operation. The AD9920A also contains six GPOs that can be used for shutter and system functions. The analog front end includes black level clamping, variable gain CDS, and a 12-bit ADC. The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control. The AD9920A is specified over an operating temperature range of −25°C to +85°C. FUNCTIONAL BLOCK DIAGRAM 06878-001 AD9920A CDS VGA CLAMP 12-BIT ADC DCLK SCK SDATA CLI VREF 6dB TO 42dB HORIZONTAL DRIVERS VERTICAL TIMING CONTROL RG H1 TO H8 GPO5 GPO6 REFT REFB PRECISION TIMING GENERATOR SYNC GENERATOR INTERNAL CLOCKS HD VD INTERNAL REGISTERS CCDIN –3dB, 0dB, +3dB, +6dB HL CLOGPO1 TO GPO4, GPO7, GPO8 XV1 TO XV24 XSUBCK LDOOUT LDOIN LDO REG VERTICAL DRIVER SUBCK XSUBCNT SYNC/RST V1A TO V6 (3-LEVEL) V7 TO V16 (2-LEVEL) D0 TO D11 SL Figure 1.

Rev. B | Page 2 of 112 TABLE OF CONTENTS Internal Vertical Driver Connections (18-Channel Mode) .. 53 Internal Vertical Driver Connections (19-Channel Mode) .. 54 Output Polarity of Vertical Transfer Clocks and Substrate Complete Exposure/Readout Operation Using Primary Manual Shutter Operation Using Enhanced SYNC Modes .. 73

Rev. B | Page 3 of 112

REVISION HISTORY

6/10—Rev. A to Rev. B Changes to Special Vertical Sequence Alternation Changes to SUBCK Low Speed Operation Section Changes to Figure 86, ShotTimer Sequences Section, Changes to Complete Exposure/Readout Operation Changes to Power-Down Sequence for Master and Changes to Layout of Internal Registers Section 6/09—Revision A: Initial Version

Rev. B | Page 4 of 112 SPECIFICATIONS Table 1. Parameter Test Conditions/Comments Min Typ Max Unit TEMPERATURE RANGE Operating −25 +85 °C Storage −65 +150 °C POWER SUPPLY VOLTAGE INPUTS AVDD AFE analog supply 1.6 1.8 2.0 V TCVDD Timing core supply 1.6 1.8 2.0 V CLIVDD CLI input supply 1.6 3.0 3.6 V RGVDD RG, HL driver supply 2.1 3.0 3.6 V HVDD1 and HVDD2 H1 to H8 driver supplies 2.1 3.0 3.6 V DVDD Digital logic supply 1.6 1.8 2.0 V DRVDD Parallel data output driver supply 1.6 3.0 3.6 V IOVDD Digital I/O supply 1.6 3.0 3.6 V V-DRIVER POWER SUPPLY VOLTAGES VDVDD V-driver/logic supply 1.6 3.0 3.6 V VH1, VH2 V-driver high supply 11.0 15.0 16.5 V VL1, VL2 V-driver low supply −8.5 −7.5 −5.5 V VM1, VM2 V-driver midsupply −1.5 0.0 +1.5 V VLL SUBCK low supply −11.0 −7.5 −5.5 V VH1, VH2 to VL1, VL2, VLL 23.5 V VMM1 SUBCK midsupply VLL 0.0 VDVDD V LDO2 LDOIN LDO supply input 2.5 3.0 3.6 V Output Voltage 1.8 1.9 2.05 V Output Current 60 100 mA POWER SUPPLY CURRENTS—40.5 MHz OPERATION AVDD 1.8 V 27 mA TCVDD 1.8 V 5 mA CLIVDD 3 V 1.5 mA RGVDD 3.3 V, 20 pF RG load, 20 pF HL load 10 mA HVDD1 and HVDD23 3.3 V, 480 pF total load on H1 to H8 59 mA DVDD 1.8 V 9.5 mA DRVDD 3 V, 10 pF load on each data output pin (D0 to D11) 6 mA IOVDD 3 V, depends on load and output frequency of digital I/O 2 mA POWER SUPPLY CURRENTS—STANDBY MODE OPERATION Standby1 Mode 20 mA Standby2 Mode 5 mA Standby3 Mode 1.5 mA MAXIMUM CLOCK RATE (CLI) 40.5 MHz MINIMUM CLOCK RATE (CLI) 10 MHz 1 VMM must be greater than VLL and less than VDVDD. 2 LDO should be used only for the AD9920A 1.8 V supplies, not for external circuitry.

3 The total power dissipated by the HVDD (or RGVDD) can be approximated using the following equation:

Total HVDD Power = (CL × HVDD × Pixel Frequency) × HVDD

Rev. B | Page 5 of 112 DIGITAL SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS (IOVDD) High Level Input Voltage VIH VDD − 0.6 V Low Level Input Voltage VIL 0.6 V High Level Input Current IIH 10 μA Low Level Input Current IIL 10 μA Input Capacitance CIN 10 pF LOGIC OUTPUTS (IOVDD, DRVDD) High Level Output Voltage VOH I OH = 2 mA VDD − 0.5 V Low Level Output Voltage VOL I OL = 2 mA 0.5 V RG and H-DRIVER OUTPUTS (HVDD1, HVDD2, and RGVDD) High Level Output Voltage VOH Maximum current VDD − 0.5 V Low Level Output Voltage VOL Maximum current 0.5 V Maximum H1 to H8 Output Current Programmable 30 mA Maximum HL and RG Output Current Programmable 17 mA Maximum Load Capacitance Each output 60 pF CLI INPUT With CLO oscillator disabled High Level Input Voltage VIHCLI CLIVDD/2 + 0.5 V Low Level Input Voltage VILCLI CLIVDD/2 − 0.5 V ANALOG SPECIFICATIONS AVDD = 1.8 V , fCLI = 40.5 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit CDS1 DC Restore AVDD − 0.5 V 1.21 1.3 1.44 V Allowable CCD Reset Transient Limit is the lower of AVDD + 0.3 V or 2.2 V 0.5 0.8 V CDS Gain Accuracy VGA gain = 6.3 dB (Code 15, default value) −3 dB CDS Gain −3.1 −2.6 −2.1 dB 0 dB CDS Gain −0.6 −0.1 +0.4 dB +3 dB CDS Gain 2.7 3.2 3.7 dB +6 dB CDS Gain 5.2 5.7 6.2 dB Maximum Input Range Before Saturation −3 dB CDS Gain 1.4 V p-p 0 dB CDS Gain 1.0 V p-p +3 dB CDS Gain 0.7 V p-p +6 dB CDS Gain 0.5 V p-p Allowable OB Pixel Amplitude1 0 dB CDS Gain (Default) −100 +200 mV +6 dB CDS Gain −50 +100 mV VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range Low Gain VGA Code 15, default 6.3 dB Maximum Gain VGA Code 1023 42.4 dB

0.6 LSB rms

1 Input signal characteristics are defined as shown in Figure 2. 2 See the Terminology section. Figure 2. Input Signal Characteristics

Rev. B | Page 7 of 112 TIMING SPECIFICATIONS CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V , fCLI = 40.5 MHz, unless otherwise noted. Table 4. Parameter Test Conditions/ Comments Symbol Min Typ Max Unit MASTER CLOCK See Figure 18 CLI Clock Period tCONV 24.7 ns CLI High/Low Pulse Width 0.8 × tCONV/2 t CONV/2 1.2 × t CONV/2 ns Delay from CLI Rising Edge to Internal Pixel Position 0 t CLIDLY 6 ns SLAVE MODE SPECIFICATIONS See Figure 105 VD Falling Edge to HD Falling Edge tVDHD 0 VD period − tCONV ns HD Falling Edge to CLI Rising Edge Only valid if OSC_RST = 0 tHDCLI 3 tCONV − 2 ns HD Falling Edge to CLO Rising Edge Only valid if OSC_RST = 1 tHDCLO 3 tCONV − 2 ns CLI Rising Edge to SHPLOC Internal sample edge tCLISHP 3 tCONV − 2 ns AFE SHPLOC Sample Edge to SHDLOC Sample Edge See Figure 23 tS1 0.8 × t CONV/2 t CONV/2 t CONV − tS2 ns SHDLOC Sample Edge to SHPLOC Sample Edge See Figure 23 tS2 0.8 × t CONV/2 t CONV/2 t CONV − tS1 ns AFE Pipeline Delay See Figure 26 16 Cycles AFE CLPOB Pulse Width 2 20 Pixels DATA OUTPUTS Output Delay from DCLK Rising Edge See Figure 25 tOD 1 ns Pipeline Delay from SHP/SHD Sampling to Data Output

16 Cycles

Maximum SCK Frequency Must not exceed CLI frequency fSCLK 40.5 MHz SL to SCK Setup Time tLS 10 ns SCK to SL Hold Time tLH 10 ns SDATA Valid to SCK Rising Edge Setup tDS 10 ns SCK Falling Edge to SDATA Valid Hold tDH 10 ns TIMING CORE SETTING RESTRICTIONS Inhibited Region for SHP Edge Location1 See Figure 23 tSHPINH 50 62 Edge location Inhibited Region for SHP or SHD with Respect to H-Clocks2, 3, 4 See Figure 23 and Figure 24 RETIME = 0, MASK = 0 tSHDINH HxNEGLOC − 14 HxNEGLOC − 2 Edge location RETIME = 0, MASK = 1 tSHDINH HxPOSLOC − 14 HxPOSLOC − 2 Edge location RETIME = 1, MASK = 0 tSHPINH HxNEGLOC − 14 HxNEGLOC − 2 Edge location RETIME = 1, MASK = 1 tSHPINH HxPOSLOC − 14 HxPOSLOC − 2 Edge location Inhibited Region for DOUTPHASE Edge Location See Figure 23 tDOUTINH SHDLOC + 1 SHDLOC + 12 Edge location 1 Applies only to slave mode operation. The inhibited area for SHP is needed to meet the timing requirement for tCLISHP for proper H-counter reset operation. 2 When the HBLKRETIME bits (Address 0x35, Bits[3:0]) are enabled, the inhibit region for the SHD location changes to the inhibit region for the SHP location. 3 When the HBLK masking polarity registers (V-sequence Register 0x18[24:21]) are set to 0, the H-edge reference becomes HxNEGLOC. 4 The H-clock signals that have SHP/SHD inhibit regions depend on the HCLK mode: Mode 1 = H1; Mode 2 = H1, H2; Mode 3 = H1, H3; and 3-Phase Mode = Phase 1, Phase 2, and Phase 3.

Rev. B | Page 8 of 112 VERTICAL DRIVER SPECIFICATIONS VH1, VH2 = 12 V; VM1, VM2, VMM = 0 V; VL1, VL2, VLL = −6 V; CL shown in load model; TA = 25°C. Table 5. Parameter Symbol Test Conditions/Comments Min Typ Max Unit V1A TO V13 Simplified load conditions, 3000 pF to ground + 30 Ω in series, SRSW = VSS Delay Time, VL to VM and VM to VH tPLM, tPMH 40 ns Delay Time, VM to VL and VH to VM tPML, tPHM 40 ns Rise Time, VL to VM tRLM 150 ns Rise Time, VM to VH tRMH 315 ns Fall Time, VM to VL tFML 250 ns Fall Time, VH to VM tFHM 165 ns Output Currents At −7.25 V 10 mA At −0.25 V −22 mA At +0.25 V 22 mA At +14.75 V −10 mA RON 35 Ω V14, V15, V16 Simplified load conditions, 3000 pF to ground + 30 Ω in series Delay Time, VL to VM tPLM 45 ns Delay Time, VM to VL tPML 45 ns Rise Time, VL to VM tRLM 345 ns Fall Time, VM to VL tFML 280 ns Output Currents At −7.25 V 10 mA At −0.25 V −7 mA RON 55 Ω SUBCK OUTPUT Simplified load conditions, 1000 pF to ground Delay Time, VLL to VH tPLH 50 ns Delay Time, VH to VLL tPHL 50 ns Delay Time, VLL to VMM tPLM 50 ns Delay Time, VMM to VH tPMH 50 ns Delay Time, VH to VMM tPHM 50 ns Delay Time, VMM to VLL tPML 50 ns Rise Time, VLL to VH tRLH 50 ns Rise Time, VLL to VMM tRLM 55 ns Rise Time, VMM to VH tRMH 50 ns Fall Time, VH to VLL tFHL 55 ns Fall Time, VH to VMM tFHM 100 ns Fall Time, VMM to VLL tFML 40 ns Output Currents At −7.25 V 20 mA At −0.25 V −12 mA At +0.25 V 12 mA At +14.75 V −20 mA RON 35 Ω SRCTL INPUT RANGE Valid only when SRSW is high 0.8 VDVDD V

Figure 3. Definition of V-Driver Timing Specifications

soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance

Figure 4. Pin Configuration Table 8. Pin Function Descriptions J7, K8 AVSS P Analog Supply Ground. A10 DVDD P Digital Logic Supply. A9 DVSS P Digital Logic Ground. L5 CLIVDD P CLI Input Supply. K6 TCVDD P Analog Timing Core Supply. K4 TCVSS P Analog Timing Core Ground. A2 DRVDD P Data Driver Supply. B2 DRVSS/LDOVSS P Data Driver and LDO Ground. L3 RGVDD P RG, HL Driver Supply. K3 RGVSS P RG, HL Driver Ground. C1 LDOOUT P LDO Output Voltage. H11 IOVDD P Digital I/O Supply. G11 IOVSS P Digital I/O Ground. C11 VDVDD P V-Driver Logic Supply (3 V). C10 VDVSS P V-Driver Ground. E3 VM1 P V-Driver Midsupply. D3 VL1 P V-Driver Low Supply. C3 VH1 P V-Driver High Supply. J3 VH2 P V-Driver High Supply. H3 VL2 P V-Driver Low Supply. F3 VM2 P V-Driver Midsupply. G3 VMM P V-Driver Midsupply for SUBCK Output. J4 VLL P V-Driver Low Supply for SUBCK Output. L7 CCDIN AI CCD Signal Input. C2 SRCTL AI Slew Rate Control Pin. Tie to VDVSS if not used. L8 REFT AO Voltage Reference Top Bypass. L9 REFB AO Voltage Reference Bottom Bypass. D11 VD DIO Vertical Sync Pulse. E10 HD DIO Horizontal Sync Pulse.

Rev. B | Page 12 of 112 Pin No. Mnemonic Type 1 Description E11 SYNC/RST DO SYNC Pin (Internal Pull-Up Resistor)/External Reset Input (Active Low). K9 SL DI 3-Wire Serial Load Pulse (Internal Pull-Up Resistor). K10 SDATA DI 3-Wire Serial Data. L10 SCK DI 3-Wire Serial Clock. B11 VDR_EN DI Enable V-Outputs When High. K11 XSUBCNT DI XSUBCNT Input to SUBCK Buffer. C9 SRSW DI Slew Rate Control Enable. Tie to ground to disable. J6 LEGEN DI Legacy Mode Enable Bar. Tie to ground for legacy 18-channel mode. J5 CLI DI Reference Clock Input. K5 CLO DO Clock Output for Crystal. F10 GPO1 DO General-Purpose Output. H9 GPO2 DO General-Purpose Output. G10 GPO3 DO General-Purpose Output. F11 GPO4 DO General-Purpose Output. H10 GPO7 DO General-Purpose Output. J11 GPO8 DO General-Purpose Output. B9 D0 DO Data Output (LSB). C6 D1 DO Data Output. C7 D2 DO Data Output. A8 D3 DO Data Output. A7 D4 DO Data Output. B7 D5 DO Data Output. B6 D6 DO Data Output. A6 D7 DO Data Output. A5 D8 DO Data Output. B4 D9 DO Data Output. A4 D10 DO Data Output. A3 D11 DO Data Output (MSB). B3 DCLK DO Data Clock Output. D1 H1 DO CCD Horizontal Clock. D2 H2 DO CCD Horizontal Clock. F1 H3 DO CCD Horizontal Clock. F2 H4 DO CCD Horizontal Clock. H1 H5 DO CCD Horizontal Clock. H2 H6 DO CCD Horizontal Clock. K1 H7 DO CCD Horizontal Clock. K2 H8 DO CCD Horizontal Clock. L2 HL DO CCD Horizontal Clock. L4 RG DO CCD Reset Gate Clock. G9 V1A VO3 CCD Vertical Transfer Clock. Three-level output (XV1 + XV16). G6 V1B VO3 CCD Vertical Transfer Clock. Three-level output (XV1 + XV17). G5 V2A VO3 CCD Vertical Transfer Clock. Three-level output (XV2 + XV18). E9 V2B VO3 CCD Vertical Transfer Clock. Three-level output (XV2 + XV19). J9 V3A VO3 CCD Vertical Transfer Clock. Three-level output (XV3 + XV20). F6 V3B VO3 CCD Vertical Transfer Clock. Three-level output. LEGEN is low, XV3 + XV21. LEGEN is high, XV23 + XV21. F5 V4 VO3 CCD Vertical Transfer Clock. Three-level output (XV4 + XV22). E5 V5 VO3 CCD Vertical Transfer Clock. Three-level output. LEGEN is low, XV5 + XV23. LEGEN is high, XV5 + GPO5. D10 V6 VO3 CCD Vertical Transfer Clock. Three-level output. LEGEN is low, XV6 + XV24. LEGEN is high, XV6 + GPO6. F9 V7 VO2 CCD Vertical Transfer Clock. Two-level output (XV7). F7 V8 VO2 CCD Vertical Transfer Clock. Two-level output (XV8).

Rev. B | Page 13 of 112 Pin No. Mnemonic Type 1 Description D9 V9 VO2 CCD Vertical Transfer Clock. Two-level output (XV9). C4 V10 VO2 CCD Vertical Transfer Clock. Two-level output (XV10). C5 V11 VO2 CCD Vertical Transfer Clock. Two-level output (XV11). B5 V12 VO2 CCD Vertical Transfer Clock. Two-level output (XV12). E6 V13 VO2 CCD Vertical Transfer Clock. Two-level output (XV13). E7 V14 VO2 CCD Vertical Transfer Clock. Two-level output (XV14). C8 V15 VO2 CCD Vertical Transfer Clock. Two-level output (XV15). J8 V16 VO2 CCD Vertical Transfer Clock. Two-level output (XV24). Available only when LEGEN is high (19-channel mode). G7 SUBCK VO3 CCD Substrate Clock Output. A1, A11, B8, B10, J10, L1, L11 NC Not Internally Connected. 1 AI = analog input; AO = analog output; DI = digital input; DO = digital output; DIO = digital input/output; P = power; VO2 = vertical driver output, two-level; VO3 = vertical driver output, three-level.

Rev. B | Page 16 of 112 TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, each for its respective input, must be present over all operating conditions. Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Peak Nonlinearity Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9920A from a true straight line. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level 1 LSB and 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately amplified to fill the ADC full-scale range. Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage. Tot a l O utput Noi s e The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage using the relationship

1 LSB = (ADC Full Scale/2

n Codes) where n is the bit resolution of the ADC. For the AD9920A, 1 LSB = 0.244 mV .

and the AFE correlated double sampling. the Power-Up Sequence for Master Mode section. divides the master clock period into 64 steps or edge positions. gramming the CLIDIVIDE register (AFE Register Address 0x0D). The AD9920A then internally divides the CLI frequency by 2. are equal to H1. H2, H4, H6, and H8 are always inverses of H1. timing locations for all of the high speed clock signals.

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (

1 PIXEL

Figure 18. High Speed Clock Resolution from CLI, Master Clock Input Figure 19. High Speed Clock Programmable Locations (HCLKMODE = 0x01)

Bits[4:0]), it is possible to select a different configuration. settings for HCLK Mode 2 and HCLK Mode 3, respectively. used together for maximum flexibility in drive strength settings. H6, and H8 outputs connected together to drive the CCD H2.

• H1 and H2 are connected to CCD Phase 1.
• H5 and H6 are connected to CCD Phase 2.
• H7 and H8 are connected to CCD Phase 3.

Table 9. Timing Core Register Parameters for H1, H2, HL, RG, SHP, and SHD Positive Edge 6 0 to 63 edge location Positive edge location for H1, H2, HL, H3P1, and RG. Negative Edge 6 0 to 63 edge location Negative edge location for H1, H2, HL, H3P1, and RG. Sampling Location 6 0 to 63 edge location Sampling location for internal SHP and SHD signals. Drive Strength 3 0 to 7 current steps Drive current for H1 to H8, HL, and RG outputs (4.3 mA per step). Table 10. HCLK Modes, Selected by Address 0x24, Bits[4:0] Mode 1 0x01 H1 edges are programmable with H3 = H5 = H7 = H1, H2 = H4 = H6 = H8 = inverse of H1. Mode 2 0x02 H1 edges are programmable with H3 = H5 = H7 = H1. H2 edges are programmable with H4 = H6 = H8 = H2. Mode 3 0x04 H1 edges are programmable with H3 = H1 and H2 = H4 = inverse of H1. H5 edges are programmable with H7 = H5 and H6 = H8 = inverse of H5. 3-Phase Mode 0x10 H1 edges are programmable using Address 0x33 and H2 = H1 (Phase 1). H5 edges are programmable using Address 0x31 and H6 = H5 (Phase 2). H7 edges are programmable using Address 0x30 and H8 = H7 (Phase 3). Invalid Selection All other values Invalid register settings. Do not use.

are active low and should be programmed accordingly. containing a unique pulse pattern for CLPOB and PBLK. each change in the vertical timing. of the existing CLPOB pattern settings. (PBLK) masking areas to be created. 0x1FFF or a value greater than the programmed VD length. Table 11. CLPOB and PBLK Pattern Registers CLPOBPOL 1 High/low Starting polarity of CLPOB for each V-sequence. PBLKPOL 1 High/low Starting polarity of PBLK for each V-sequence. CLPOBTOG1 13 0 to 8191 pixel location First CLPOB toggle position within line for each V-sequence. CLPOBTOG2 13 0 to 8191 pixel location Second CLPOB toggle position within line for each V-sequence. PBLKTOG1 13 0 to 8191 pixel location First PBLK toggle position within line for each V-sequence. PBLKTOG2 13 0 to 8191 pixel location Second PBLK toggle position within line for each V-sequence. CLPMASKSTART 13 0 to 8191 line location CLPOB masking area—starting line within field (maximum of three areas). CLPMASKEND 13 0 to 8191 line location CLPOB masking area—ending line within field (maximum of three areas). PBLKMASKSTART 13 0 to 8191 line location PBLK masking area—starting line within field (maximum of three areas). PBLKMASKEND 13 0 to 8191 line location PBLK masking area—ending line within field (maximum of three areas).

Table 12. HBLK Pattern Registers HBLK_MODE 2 0 to 1 HBLK modes Enables different HBLK toggle position operations. 0 = normal mode; six toggle positions available for even and odd lines. odd alternation is not needed, set toggles for even and odd lines to the same value. 1 = advanced HBLK mode; divides HBLK interval into six repeat areas. to HBLKTOGE6 registers (Address 0x19 to Address 0x1E; see Table 63). 2 = test mode only; do not access. 3 = test mode only; do not access. HBLKSTART 13 0 to 8191 pixel location Start location for HBLK in HBLK Mode 0 and HBLK Mode 1. HBLKEND 13 0 to 8191 pixel location End location for HBLK in HBLK Mode 0 and HBLK Mode 1. HBLKLEN 13 0 to 8191 pixels HBLK length in HBLK Mode 0 and HBLK Mode 1. HBLKREP 13 0 to 8191 repetitions Number of HBLK repetitions in HBLK Mode 0 and HBLK Mode 1. HBLKMASK_H1 1 High/low Masking polarity for H1/H3/H5/H7 during HBLK. HBLKMASK_H2 1 High/low Masking polarity for H2/H4/H6/H8 during HBLK. HBLKMASK_HL 1 High/low Masking polarity for HL during HBLK. HBLKMASK_H3P 1 High/low Masking polarity for H3P during 3-phase mode during HBLK. HBLKTOGO1 13 0 to 8191 pixel location First HBLK toggle position for odd lines in HBLK Mode 0. HBLKTOGO2 13 0 to 8191 pixel location Second HBLK toggle position for odd lines in HBLK Mode 0. HBLKTOGO3 13 0 to 8191 pixel location Third HBLK toggle position for odd lines in HBLK Mode 0. HBLKTOGO4 13 0 to 8191 pixel location Fourth HBLK toggle position for odd lines in HBLK Mode 0. HBLKTOGO5 13 0 to 8191 pixel location Fifth HBLK toggle position for odd lines in HBLK Mode 0. HBLKTOGO6 13 0 to 8191 pixel location Sixth HBLK toggle position for odd lines in HBLK Mode 0. HBLKTOGE1 13 0 to 8191 pixel location First HBLK toggle position for even lines in HBLK Mode 0. HBLKTOGE2 13 0 to 8191 pixel location Second HBLK toggle position for even lines in HBLK Mode 0. HBLKTOGE3 13 0 to 8191 pixel location Third HBLK toggle position for even lines in HBLK Mode 0. HBLKTOGE4 13 0 to 8191 pixel location Fourth HBLK toggle position for even lines in HBLK Mode 0. HBLKTOGE5 13 0 to 8191 pixel location Fifth HBLK toggle position for even lines in HBLK Mode 0. HBLKTOGE6 13 0 to 8191 pixel location Sixth HBLK toggle position for even lines in HBLK Mode 0. HBLK Mode 1 for even lines; odd lines defined using HBLKALT_PAT. Bits[3:0]: RA0H1REPA. Number of H1 pulses following HBLKSTARTA. Bits[7:4]: RA0H1REPB. Number of H1 pulses following HBLKSTARTB. Bits[11:8]: RA0H1REPC. Number of H1 pulses following HBLKSTARTC. RA1H1REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 1. Number of H1 repetitions for HBLKSTARTA/B/C. RA2H1REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 2. Number of H1 repetitions for HBLKSTARTA/B/C. RA3H1REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 3. Number of H1 repetitions for HBLKSTARTA/B/C. RA4H1REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 4. Number of H1 repetitions for HBLKSTARTA/B/C. RA5H1REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 5. Number of H1 repetitions for HBLKSTARTA/B/C. HBLK Mode 1 for even lines; odd lines defined using HBLKALT_PAT. Bits[3:0]: RA0H2REPA. Number of H2 pulses following HBLKSTARTA. Bits[7:4]: RA0H2REPB. Number of H2 pulses following HBLKSTARTB. Bits[11:8]: RA0H2REPC. Number of H2 pulses following HBLKSTARTC. RA1H2REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 1. Number of H2 repetitions for HBLKSTARTA/B/C. RA2H2REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 2. Number of H2 repetitions for HBLKSTARTA/B/C. RA3H2REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 3. Number of H2 repetitions for HBLKSTARTA/B/C. RA4H2REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 4. Number of H2 repetitions for HBLKSTARTA/B/C. RA5H2REPA/B/C 12 0 to 15 HCLK pulses HBLK Repeat Area 5. Number of H2 repetitions for HBLKSTARTA/B/C.

HBLKSTARTA 13 0 to 8191 pixel location HBLK Repeat Area Start Position A for HBLK Mode 1. Set to 8191 if not used. HBLKSTARTB 13 0 to 8191 pixel location HBLK Repeat Area Start Position B for HBLK Mode 1. Set to 8191 if not used. HBLKSTARTC 13 0 to 8191 pixel location HBLK Repeat Area Start Position C for HBLK Mode 1. Set to 8191 if not used. defined even line repeat areas. HBLKALT_PAT1 3 0 to 5 even repeat area HBLK Mode 1, Repeat Area 1 pattern for odd lines. HBLKALT_PAT2 3 0 to 5 even repeat area HBLK Mode 1, Repeat Area 2 pattern for odd lines. HBLKALT_PAT3 3 0 to 5 even repeat area HBLK Mode 1, Repeat Area 3 pattern for odd lines. HBLKALT_PAT4 3 0 to 5 even repeat area HBLK Mode 1, Repeat Area 4 pattern for odd lines. HBLKALT_PAT5 3 0 to 5 even repeat area HBLK Mode 1, Repeat Area 5 pattern for odd lines.

1 PIXEL 1 PIXEL 1 PIXEL

Figure 33. Example of Correct HBLK Behavior incorrect blanking on Phase 1 and Phase 2. exact pulse behavior for each HCLK phase can be generated.

1 PIXEL 1 PIXEL1 PIXEL1 PIXEL1 PIXEL

Figure 34. Incorrect HBLK Behavior Caused by Internal Clock Position Figure 35. Fine Retime on Phase 2 to Achieve Correct HBLK

28 DUMMY PIXELS

48 OB PIXELS4 OB PIXELS

10 VERTICAL

2 VERTICAL

Figure 39. Example CCD Configuration

1. PBLK ACTIVE (LOW) SHOULD NOT BE USED DURING CLPOB ACTIVE (LOW).

Figure 40. Horizontal Sequence Example

each of the pattern repetitions when repetitions are used. value plus the toggle position. are not simultaneously available for VSG pulses. V-pattern group registers are unknown. Table 14. Vertical Pattern Group Registers VTOG1 13 First toggle position within the line for each XV1 to XV24 output, relative to VSTART value. VTOG2 13 Second toggle position, relative to VSTART value. VTOG3 13 Third toggle position, relative to VSTART value. VTOG4 13 Fourth toggle position, relative to VSTART value. START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS. 1START POLARITY (LOCATED IN V-SEQUENCE REGISTERS). 3SECOND TOGGLE POSITION (THIRD AND FOURTH TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS). 4TOTAL PATTERN LENGTH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGISTERS). Figure 42. Vertical Pattern Group Programmability

how these registers are used to generate the V-sequences. registers select which V-pattern is used in a given V-sequence. binning by using the VREP registers for odd and even lines. registers specify where in the line the V-pattern group starts. RESUME3, and FREEZE4/RESUME4 registers can be enabled. is located in the field register section (see Table 64). 1START POSITION IN THE LINE OF THE SELECTED V-PATTERN GROUP. 3V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP. 4NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED). 5START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS. 6MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL. Figure 43. V-Sequence Programmability

Table 15. Summary of V-Sequence Registers (see Table 11 and Table 12 for the CLPOB, PBLK, and HBLK Register Summary) HOLD 4 Use in conjunction with VMASK_EVEN and VMASK_ODD. 1 = Enable HOLD function instead of FREEZE/RESUME function. for start, polarity, length, and repetition are used when this mode is selected. 1 = enable the addition of all toggle positions from VPATSELA/B/C/D. 2 to 15 = test mode only; do not use. Group B, Group C, and Group D. 0 = disable alternation. Group A uses VREPA_1, Groups B/C/D use VREP_EVEN for all lines. 1 = two-line. Group A alternates VREPA_1 and VREPA_2. Groups B/C/D alternate VREP_EVEN and VREP_ODD. VREP_ODD, VREP_ODD, VREP_EVEN, VREP_ODD, VREP_ODD pattern. group (A, B, C, and D); Group A is the LSB. Set bit high to enable. Recommended value is enabled. HDLENE 14 HD line length for even lines in the V-sequence. HDLENO 14 HD line length for odd lines in the V-sequence. VPOL 24 Group A start polarity bits for each XV1 to XV24 signal. GROUPSEL_0 24 Assigns each XV1 to XV12 signal to Group A, Group B, Group C, or Group D. Two bits for each signal. GROUPSEL_1 24 Assigns each XV13 to XV24 signal to Group A, Group B, Group C, or Group D. Two bits for each signal. VPATSELA 5 Selected V-pattern for Group A. VPATSELB 5 Selected V-pattern for Group B. VPATSELC 5 Selected V-pattern for Group C. VPATSELD 5 Selected V-pattern for Group D. VSTARTA 13 Start position for the selected V-pattern Group A. VSTARTB 13 Start position for the selected V-pattern Group B. VSTARTC 13 Start position for the selected V-pattern Group C. VSTARTD 13 Start position for the selected V-pattern Group D. VLENA 13 Length of selected V-pattern Group A. VLENB 13 Length of selected V-pattern Group B. VLENC 13 Length of selected V-pattern Group C. VLEND 13 Length of selected V-pattern Group D. VREPA_1 13 Number of repetitions for the V-pattern Group A for first lines (even). VREPA_2 13 Number of repetitions for the V-pattern Group A for second lines (odd). VREPA_3 13 Number of repetitions for the V-pattern Group A for third lines. VREPA_4 13 Number of repetitions for the V-pattern Group A for fourth lines.

Rev. B | Page 36 of 112 Register Length (Bits) Description VREPB_ODD 13 Number of repetitions for the V-pattern Group B for odd lines. VREPC_ODD 13 Number of repetitions for the V-pattern Group C for odd lines. VREPD_ODD 13 Number of repetitions for the V-pattern Group D for odd lines. VREPB_EVEN 13 Number of repetitions for the V-pattern Group B for even lines. VREPC_EVEN 13 Number of repetitions for the V-pattern Group C for even lines. VREPD_EVEN 13 Number of repetitions for the V-pattern Group D for even lines. FREEZE1 13 Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as VALTSEL0_EVEN, Bits[12:0] register when special VSEQALT_EN mode is enabled. FREEZE2 13 Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as VALTSEL1_EVEN, Bits[12:0] register when special VSEQALT_EN mode is enabled. FREEZE3 13 Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as VALTSEL0_ODD, Bits[12:0] register when special VSEQALT_EN mode is enabled. FREEZE4 13 Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as VALTSEL1_ODD, Bits[12:0] register when special VSEQALT_EN mode is enabled. RESUME1 13 Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as VALTSEL0_EVEN, Bits[17:13] register when special VSEQALT_EN mode is enabled. RESUME2 13 Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as VALTSEL1_EVEN, Bits[17:13] register when special VSEQALT_EN mode is enabled. RESUME3 13 Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as VALTSEL0_ODD, Bits[17:13] register when special VSEQALT_EN mode is enabled. RESUME4 13 Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as VALTSEL1_ODD, Bits[17:13] register when special VSEQALT_EN mode is enabled. LASTREPLEN_A 13 Separate length for last repetition of vertical pulses for Group A. Must be enabled using LASTREPLEN_EN. Should be programmed to a value equal to the VLENA register. LASTREPLEN_B 13 Separate length for last repetition of vertical pulses for Group B. Must be enabled using LASTREPLEN_EN. Should be programmed to a value equal to the VLENB register. LASTREPLEN_C 13 Separate length for last repetition of vertical pulses for Group C. Must be enabled using LASTREPLEN_EN. Should be programmed to a value equal to the VLENC register. LASTREPLEN_D 13 Separate length for last repetition of vertical pulses for Group D. Must be enabled using LASTREPLEN_EN. Should be programmed to a value equal to the VLEND register. VSEQALT_EN 1 Special V-sequence alternation mode is enabled when this register is programmed high. VALTSEL0_EVEN 18 Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Group A, Group B, Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi- mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.) VALTSEL1_EVEN 18 Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Group A, Group B, Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi- mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.) VALTSEL0_ODD 18 Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Group A, Group B, Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi- mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.) VALTSEL1_ODD 18 Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Group A, Group B, Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi- mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.) SPC_PAT_EN 3 Enable special V-pattern to be inserted into one repetition of a VPATA series. SPC_PAT_EN, Bit 0: set to 1 to enable VPATB to be used as special pattern insertion. SPC_PAT_EN, Bit 1: set to 1 to enable VPATC to be used as special pattern insertion. SPC_PAT_EN, Bit 2: set to 1 to enable VPATD to be used as special pattern insertion. SEQ_ALT_INC 1 0 = normal operation. 1 = automatically increments the sequence number at the end of the line, unless a sequence change position boundary is reached. SEQ_ALT_RST 1 0 = normal operation. 1 = automatically resets the sequence number back to the sequence defined for that particular region in the active field register.

VLENB, VLENC, and VLEND register values, respectively. assigned Group A, Group B, Group C, and Group D patterns. HBLK Mode 0 alternation used together.

1. THE NUMBER OF REPEATS FOR V-PATTERN GROUPS A/B/C/D CAN BE ALTERNATED ON ODD AND EVEN LINES.
2. GROUP A ALSO SUPPORTS 3- AND 4-LINE ALTERNATION USING THE ADDITIONAL VREPA_3 AND VREPA_4 REGISTERS.
3. THE HBLK TOGGLE POSITIONS CAN BE ALTERNATED BETWEEN ODD AND EVEN LINES TO GENERATE DIFFERENT HBLK PATTERNS.

Figure 50. Odd/Even Line Alternation of V-Pattern Group Repetitions and HBLK Toggle Positions

to continue in the masking area.

1. WHEN HOLD = 1 FOR ANY V-SEQUENCE GROUP, THE FREEZE AND RESUME REGISTERS ARE USED TO SPECIFY THE HOLD AREA.
2. IN THIS EXAMPLE, XV1 TO XV10 ARE ASSIGNED TO GROUP A. HOLD BIT FOR GROUP A = 1.
3. H-COUNTER FOR GROUP A (XV1 TO XV10) STOPS DURING HOLD AREA.

Figure 53. Hold Area for Group A

allows the user to create a loop of sequences for a given region. sequence number automatically increments to Sequence 4. until it reaches the next sequence change position. Vertical Sequence Alternation (SVSA) Mode section). Table 18. Register Settings for the Example in Figure 56 Figure 56. Example Output Using SEQ_ALT_INC and SEQ_ALT_RST Functions

within each region, a different V-sequence can be selected. registers then select which V-sequence is used in each region. the total number of pixels per line. separate masking in SGACTLINE1 and SGACTLINE2. patterns are created separately using the SG pattern registers. must be programmed to occur before SGACTLINE1. Table 19. Field Registers (CLPOB, PBLK Masking Shown in Table 11) SEQ 5 0 to 31 V-sequence number Selected V-sequence for each region in the field. MULT_SWEEP 2 0 to 3 Enable multiplier mode and/or sweep mode for each region. 0 = multiplier off, sweep off. 1 = multiplier off, sweep on. 2 = multiplier on, sweep off. 3 = multiplier on, sweep on. SCP 13 0 to 8191 line number Sequence change position for each region. VDLEN 13 0 to 8191 lines Total number of lines in each field. HDLASTLEN 13 0 to 8191 pixels Length in pixels of the last HD line in each field. SGMASK 24 High/low, each VSG Set high to mask each individual VSG output. SGACTLINE1 13 0 to 8191 line number Selects the line in the field where the VSG signals are active. not used, set it equal to SGACTLINE1 or to the maximum value.

determines which vertical outputs are assigned as VSG pulses. either TOG1 and TOG2 or TOG3 and TOG4 to the VSG signal. available when a vertical signal is selected to be a VSG pulse. mation, see the Substrate Clock Operation (SUBCK) section. must be programmed to 0xFF8000. Table 21. VSG Control Registers (also see Field Registers in Table 19) 24 High/low Selection of VSG signals from XV signals. Set to 1 to make signal a VSG. The recommended setting for this register is 0xFF8000. Bit 0: XV1 selection (0 = XV pulse; 1 = VSG pulse). Toggle 3 and Toggle 4 are used. Bit 0: XV1 selection (0 = use TOG1, TOG2; 1 = use TOG3, TOG4). SGMASK 24 High/low, each VSG Set high to mask each individual VSG output. SGACTLINE1 13 0 to 8191 line number Selects the line in the field where the VSG signals are active. is not used, set it equal in value to SGACTLINE1 or to the maximum value. 1START POLARITY OF PULSE (FROM VPOL IN SEQUENCE REGISTERS). 2FIRST TOGGLE POSITION (FROM V-PATTERN REGISTERS). 3SECOND TOGGLE POSITION (FROM V-PATTERN REGISTERS). 4ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (FROM FIELD REGISTERS). Figure 60. Vertical Sensor Gate Pulse Placement

nation of field timing to meet the requirements of the system. changed with each camera mode change. depending on how the camera is being used. register (Address 0x2A) specifies how many total fields are used. Any value from 1 to 7 can be selected using these three bits. mode register settings for different field configurations. together in the same field (VD period). Table 22. Mode Registers 0x2A MODE 3 Total number of fields to cycle through. Set from 1 to 7. 0x2B FIELD1 5 Selected field (from FIELD registers in configurable memory) for the first field to cycle through. FIELD2 5 Selected field (from FIELD registers in configurable memory) for the second field to cycle through. FIELD3 5 Selected field (from FIELD registers in configurable memory) for the third field to cycle through. FIELD4 5 Selected field (from FIELD registers in configurable memory) for the fourth field to cycle through. FIELD5 5 Selected field (from FIELD registers in configurable memory) for the fifth field to cycle through. 0x2C FIELD6 5 Selected field (from FIELD registers in configurable memory) for the sixth field to cycle through. FIELD7 5 Selected field (from FIELD registers in configurable memory) for the seventh field to cycle through.

Rev. B | Page 51 of 112 VERTICAL TIMING EXAMPLE To better understand how the AD9920A vertical timing genera- tion is used, consider the example CCD timing chart in Figure 64. This example illustrates a CCD using a general three-field read- out technique. As shown in Figure 64, each readout field must be divided into separate regions to perform each step of the readout. The sequence change positions (SCPs) determine the line bound- aries for each region, and the SEQ registers assign a particular V-sequence to each region. The V-sequences contain the specific timing information required in each region: V1 to V6 pulses (using V-pattern groups), HBLK/CLPOB timing, and VSG patterns for the SG active lines. This timing example requires four regions for each of the three fields, labeled Region 0, Region 1, Region 2, and Region 3. Because the AD9920A allows many individual fields to be programmed, FIELD1, FIELD2, and FIELD3 can be used to meet the require- ments of this timing example. The four regions for each field are very similar in this example, but the individual registers for each field allow flexibility to accommodate other timing charts. Region 0 is a high speed, vertical shift region. Sweep mode can be used to generate this timing operation with the desired number of high speed vertical pulses needed to clear any charge from the CCD vertical registers. Region 1 consists of only two lines and uses standard single-line vertical shift timing. The timing of this region area is the same as the timing in Region 3. Region 2 is the sensor gate line in which the VSG pulses transfer the image into the vertical CCD registers. This region may require the use of the second V-pattern group for the SG active line. Region 3 also uses the standard single-line vertical shift timing, the same timing as Region 1. Four regions are required in each of the three fields. The timing for Region 1 and Region 3 is essentially the same, reducing the complexity of the register programming. Other registers must be used during the actual readout operation. These include the mode registers, shutter control registers (PRIMARY_ACTION, SUBCK, and GPO for MSHUT and VSUB control), and AFE gain registers. Important Note Regarding Signal Polarities When programming the AD9920A to generate the V1 to V24 and SUBCK signals, the external V-driver circuit usually inverts these signals. Carefully check the timing signals that are required at the input and output of the V-driver circuit being used, and adjust the polarities of the AD9920A outputs accordingly.

Figure 64. CCD Timing Example—Dividing Each Field into Regions

Figure 65. Internal AFETG to V-Driver Connections, Legacy Mode (18-Channel Mode)

Figure 66. Internal AFETG to V-Driver Connections (19-Channel Mode)

Table 23. V1A Output Polarity Table 24. V1B Output Polarity Table 25. V2A Output Polarity Table 26. V2B Output Polarity Table 27. V3A Output Polarity Table 28. V3B Output Polarity Table 29. V4 Output Polarity Table 30. V5 Output Polarity Table 31. V6 Output Polarity Table 32. V7 Output Polarity Table 33. V8 Output Polarity Table 34. V9 Output Polarity

Table 35. V10 Output Polarity Table 36. V11 Output Polarity Table 37. V12 Output Polarity Table 38. V13 Output Polarity Table 39. V14 Output Polarity Table 40. V15 Output Polarity Table 41. V16 Output Polarity Table 42. SUBCK Output Polarity

Figure 80. XSUBCNT, XSUBCK, and SUBCK Output Polarities clocking valid image pixel data out of the CCD. electronic shuttering: normal, high precision, and low speed. suppress the SUBCK pulses during multiple field readouts. of their normal drive strength (that is, when SRSW = VSS). accurately control the exposure time. programmed in the SUBCKNUM register (Address 0x75). described in the Updating New Register Values section.

than one field, the low speed (LS) shutter features can be used. time begins in the field after the exposure operation is initiated. DELAY register along with the PRIMARY_ACTION register. from the normal shutter or high precision shutter operations. number of lines following SGACTLINE1. ing after the read begins (SUBCKMASK_NUM = 3). SUBCK pulses at the beginning of the field of exposure. Table 43. SUBCK and Exposure/Read Register Parameters SGMASK_NUM 13 0 to 8191 number of fields Exposure duration (number of fields to suppress VSG) for LS operation. SUBCKMASK_NUM 13 0 to 8191 number of fields Exposure plus readout duration (number of fields to suppress SUBCK) for LS. SUBCKMASK_SKIP1 1 On/off Suppress SG/SUBCK masks for one field (default = 0). Typically set to 1. SUBCKSUPPRESS 13 0 to 8191 lines Number of lines to suppress the start of SUBCK pulses after SGACTLINE1. SUBCKNUM 13 1 to 8191 number of pulses Total number of SUBCK pulses per field, at one pulse per line. SG_SUPPRESS 1 On/off Suppress the SG and allow SUBCK to finish at SUBCKNUM. SUBCK_TOG1 14 0 to 16383 pixel locations SUBCK Toggle Position 1. SUBCK_TOG2 14 0 to 16383 pixel locations SUBCK Toggle Position 2. SUBCK_POL 1 Low/high SUBCK start polarity. SUBCKHP_TOG1 14 0 to 16383 pixel locations High precision SUBCK Toggle Position 1. Selectable as SG or VD updated. SUBCKHP_TOG2 14 0 to 16383 pixel locations High precision SUBCK Toggle Position 2. Selectable as SG or VD updated.

• Normal (single count)
• RapidShot (repeating count)
• ShotTimer (delayed count)
• ShotTimer with RapidShot
• Manual exposure
• Manual readout
• Force to idle The primary counter regulates the expose and read actions by regulating the SUBCK and VSG signals. In addition, if the RapidShot feature is used with the primary counter, the SUBCK and VSG masking automatically repeats as necessary for multiple expose/read cycles. The secondary counter has no effect on the SUBCK or VSG signal. Both counters can be used to regulate the general-purpose signals described in the General-Purpose Outputs (GPOs) section.

Table 44. Primary/Secondary Field Counter Registers (Address 0x70, Address 0x71, and Address 0x72) appropriate GP_PROTOCOL register to 1. 2 = RapidShot. After reaching the maximum counter value, the counter wraps and repeats until reset. delay of n fields between each repetition. 5 = manual exposure. Primary counter stays in exposure until manual readout or reset to idle. This mode keeps the SUBCK and VSG pulses masked indefinitely. 6 = manual readout. Primary counter switches to readout (VSG pulses becomes active). PRIMARY_MAX 13 Primary counter maximum value. SECOND_MAX 12 Secondary counter maximum value. VDHD_MASK 3 Mask VD/HD during counter operation. ShotTimer with RapidShot, the delay value is used between each repetition. PRIMARY_SKIP 1 When using ShotTimer with RapidShot, use the primary delay value only before the first count (exposure). RapidShot, the delay value is used between each repetition. SECOND_SKIP 1 When using ShotTimer with RapidShot, use the secondary delay value only before the first count.

available to be programmed and assigned to special GPO pins. OUT_CONTROL. The GPO registers are described in Table 45. Using GPO section for more information. field counters through the GP protocol register (Address 0x73).

1. Program the toggle positions (Address 0x7C to
2. Program the GP protocol (Address 0x73).
3. Program the counter parameters (Address 0x71 to
4. Activate the counter (Address 0x70).

For Protocol 1 (no counter association), skip Step 3 and Step 4. the GP signals smooth integration with concurrent operations. primary counter without expose/read activity. operations are easily handled by the AD9920A. addition, GP1 or GP2 can deliver its original toggles. Table 45. GPO Registers GP2_PROTOCOL 3 0 to 7 1 = no counter association; use MANUAL_TRIG bits to enable each GP signal. GP3_PROTOCOL 3 0 to 7 2 = test only. GP4_PROTOCOL 3 0 to 7 3 = test only. GP5_PROTOCOL 3 0 to 7 4 = link to mode counter (from vertical timing generation). GP6_PROTOCOL 3 0 to 7 5 = link to primary counter (also allows GP signals to repeat with RapidShot). GP7_PROTOCOL 3 0 to 7 6 = link to secondary counter (also allows GP signals to repeat with RapidShot). GP8_PROTOCOL 3 0 to 7 7 = keep on. MANUAL_TRIG 8 On/off Manual trigger for each GP signal. For use with Protocol 1. GP[1:8]_POL 8 Low/high Starting polarity for GP signals. Only updated when GPx_PROTOCOL = 0. 0 = select vertical signals visible at GPO4 to GPO8 when output is enabled. GPO_OUTPUT_EN 8 On/off 1 = enable GPO1 to GPO4, GPO7, and GPO8 outputs (one bit per output). 0 = disable GPO1 to GPO4, GPO7, and GPO8 outputs; pins are high-Z (default). GPx_USE_LUT 8 On/off Send GP signals through a programmable lookup table (LUT). LUT_FOR_GP12 4 Logic setting Desired logic to be realized on GPO1 combined with GPO2. LUT_FOR_GP34 4 Logic setting Desired logic to be realized on GPO3 combined with GPO4. LUT_FOR_GP56 4 Logic setting Desired logic to be realized on GPO5 combined with GPO6.

Rev. B | Page 65 of 112 Register Length (Bits) Range Description LUT_FOR_GP78 4 Logic setting Desired logic to be realized on GPO7 combined with GPO8. Example logic settings for LUT_FOR_GPxy: 0x06 = GPy XOR GPx (see Figure 89). 0x07 = GPy NAND GPx. 0x08 = GPy AND GPx. 0x0E = GPy OR GPx. GPx_TOGx_FD 13 0 to 8191 fields Field of activity, relative to primary and secondary counter for corresponding toggle. GPx_TOGx_LN 13 0 to 8191 lines Line of activity for corresponding toggle. GPx_TOGx_PX 13 0 to 8191 pixels Pixel of activity for corresponding toggle. GPO_INT_EN 1 On/off When set to 1, internal signals are viewable on GPO1 to GPO3. Also, set the SEL_GPx bit low to output internal signals. GPO1 = internal clock. GPO2 = CLPOB. GPO3 = delayed sample clock.

Rev. B | Page 69 of 112 COMPLETE EXPOSURE/READOUT OPERATION USING PRIMARY COUNTER AND GPO SIGNALS Figure 90 illustrates a typical expose/read cycle while exercising the GPO signals. Using a three-field CCD with an exposure time that is greater than one field but less than two fields in duration requires a total of five fields for the entire exposure/readout operation. Other exposure times and CCD field configurations require modification of these example settings. Note that if the mode registers are changed to be VD updated, as shown in the Mode Registers section and in Figure 63, the mode update is delayed by one additional field. This should be accounted for in selecting the number of fields to cycle and in determining which VD location to write to the mode registers. 1. The primary counter is used to control the masking of VSG and SUBCK during exposure/readout. The PRIMARY_MAX register (Address 0x71) should be set equal to the total number of fields used for exposure and readout. In this example, PRIMARY_MAX = 5. The SUBCK masking should not occur immediately at the next VD edge (Step 2) because this would define an exposure time that begins in the previous field. Write to the PRIMARY_DELAY register (Address 0x72) to delay the masking of VSG and SUBCK pulses in the first exposure field. In this example, PRIMARY_DELAY = 1. Write to the SUBCKMASK_NUM register (Address 0x74) to specify the number of fields to mask SUBCK while the CCD data is read. In this example, SUBCKMASK_NUM = 4. Write to the SGMASK_NUM register (Address 0x74) to specify the number of fields to mask VSG outputs during exposure. In this example, SGMASK_NUM = 1. Write to the PRIMARY_ACTION register (Address 0x70) to trigger the GP1 (STROBE), GP2 (MSHUT), and GP3 (VSUB) signals and to start the expose/read operation. Write to the mode registers to configure the next five fields. The first two fields during exposure are the same as the current draft mode fields, and the following three fields are the still image frame readout fields. The register settings for the draft mode field and the three readout fields are previously programmed. Note that if the mode registers are changed to VD updated, only one field of exposure should be included (the second one) because the mode settings are delayed an extra field. 2. VD/HD falling edge updates the serial writes from 1. 3. GP3 (VSUB) output turns on at the field/line/pixel specified. In Figure 90, VSUB Example 1 and Example 2 use GP3TOG1_FD = 1. 4. GP1 (STROBE) output turns on and off at the location specified. 5. GP2 (MSHUT) output turns off at the location specified. 6. The next VD falling edge automatically starts the first read field. 7. The next VD falling edge automatically starts the second read field. 8. The next VD falling edge automatically starts the third read field. 9. Write to the mode register to reconfigure the single draft mode field timing. Note that if the mode registers are changed to VD updated, this write should occur one field earlier. 10. VD/HD falling edge updates the serial writes from 9. VSG outputs return to draft mode timing. SUBCK output resumes operation. GP2 (MSHUT) output returns to the on position (active or open). GP3 (VSUB) output returns to the off position (inactive).

Figure 90. Complete Exposure/Readout Operation Using Primary Counter and GPO Signals

additional control of the exposure operation. operates, highlighting the behavior of the mode field designator. and use V-Sequence 0 behavior. See Figure 95 for more details. register (Address 0x13, Bit 3) to 1. can also be masked, if required (see Figure 96). The following steps are shown in Figure 99.

1. To turn on VSUB, write to the appropriate GP registers to

ACTION = 5). This change takes effect after the next VD.

1. To turn on MSHUT during the interval between the next

MSHUT is in the on position, it has line and pixel control.

1. If the mode register is programmed to cycle through

counter from incrementing during the SYNC interval.

1. Write to the manual readout trigger to begin the manual

necessary to insert a dummy VD to delay the readout. Table 47. Registers for Enhanced SYNC Modes

5SUBCK OUTPUT IS SUPPRESSED DURING EXPOSURE AND READOUT WHEN EXPOSURE TRIGGER IS USED. Figure 99. Enhanced SYNC Mode—Manual Shutter Operation, SLR Mode

1S1 IS NORMALLY CLOSED; S2 IS NORMALLY OPEN. Figure 100. Analog Front End Functional Block Diagram The AD9920A signal processing chain is shown in Figure 100. image from the raw CCD pixel data. restore switch is active during the SHP sample pulse time. for achieving the best performance from the CCD. range is reduced (see the Analog Specifications section).

Rev. B | Page 79 of 112 APPLICATIONS INFORMATION POWER-UP SEQUENCE FOR MASTER MODE When the AD9920A is powered up, the following sequence is recommended (refer to Figure 102 for each step). Note that a SYNC signal is required for master mode operation. If an external SYNC pulse is not available, it is possible to generate an internal SYNC event by writing to the SWSYNC register. 1. Turn on the 3 V and 1.8 V power supplies for the AD9920A and start master clock CLI. 2. The SYNC/RST pin is configured as the RST pin by default. It must be brought high before any register writes are performed. Configure the SYNC/RST pin for SYNC functionality by writing Register 0x12 = 0x00, and then perform a software reset by writing Register 0x10 to 0x01. 3. Make sure that VDR_EN is low. If driving VDR_EN with a GPO, set the appropriate bit in the GPO_OUTPUT_EN register (Address 0x7A, Bits[23:16]) to 1 to configure it as an output and make sure that the appropriate bit in the GP_STBY3 register (Address 0x27, Bits[15:8]) is set to 0. 4. Power up the V-driver supplies. 5. Define the standby status of the AD9920A vertical outputs. Write to the Standby2 and Standby3 polarity registers (Address 0x25 and Address 0x26 = 0x1FF8000). Write 0xFF8000 to Address 0x1C to configure the XV and VSG signals. Write 0x100000 to Register 0xD1. When using 3-phase HCLK mode, enable this mode before Step 6 by setting Address 0x24 = 0x10. 6. Place the AFE into normal operation and enable clamping (Address 0x00 = 0x04). If using CLO to drive a crystal, set OSC_RST = 1. Wait at least 500 μs before performing Step 8. 7. Load the required registers to configure vertical timing, horizontal timing, high speed timing, and shutter timing. 8. Reset the internal timing core (TGCORE_RST). If a 2× clock is used for CLI, the CLIDIVIDE register (Address 0x0D) should be set to 1 before TGCORE_RST is written (Address 0x14 = 0x01). Wait at least 100 μs before performing Step 9. 9. Bring the VDR_EN pin high. If driving VDR_EN with a GPO, write to the appropriate GPO polarity bit in Address 0x7A to set the VDR_EN signal high (updated at the next VD). Note that IOVDD must be at the same voltage as VDVDD if GPO is used for VDR_EN. 10. Enable the AD9920A outputs (OUT_CONTROL register, Address 0x11 = 0x01). OUT_CONTROL is a VD-updated register; therefore, the outputs become active after the next VD falling edge. 11. Enable master mode operation by setting Register 0x20 = 0x01. 12. Generate a SYNC event. SYNC should be high at power- up. Bring the SYNC input low for a minimum of 100 ns, and then bring SYNC high again. This resets the internal counters and starts VD/HD operation. The first VD/HD edge allows VD-updated register updates (including updates of OUT_CONTROL) to occur, enabling all outputs. If a hardware SYNC is not available, the SWSYNC register (Address 0x13, Bit 24) can be used to initiate a SYNC event. Note that VDR_EN must remain high to achieve proper vertical outputs during normal operation.

Figure 102. Recommended Power-Up Sequence and Synchronization, Master Mode

Rev. B | Page 81 of 112 POWER-UP SEQUENCE FOR SLAVE MODE When the AD9920A is used in slave mode, the VD/HD inputs are used to synchronize the internal counters. For more detail on the counter reset operation, see Figure 103. 1. Turn on the 3 V and 1.8 V power supplies for the AD9920A, and start master clock CLI. 2. Reset the internal AD9920A registers. If the SYNC/RST pin is functioning as RST, apply a rising edge to the SYNC/RST pin. If the SYNC/RST pin is function- ing as SYNC, tie this pin high. Then perform a software reset by writing Register 0x10 to 0x01. 3. Make sure that VDR_EN is low. If driving VDR_EN with a GPO, set the appropriate bit in the GPO_OUTPUT_EN register (Address 0x7A, Bits[23:16]) to 1 to configure it as an output and make sure that the appropriate bit in the GP_STBY3 register (Address 0x27, Bits[15:8]) is set to 0. 4. Power up the V-driver supplies. 5. Define the standby status of the AD9920A vertical outputs. Write to the Standby2 and Standby3 polarity registers (Address 0x25 and Address 0x26 = 0x1FF8000). Write 0xFF8000 to Address 0x1C to configure the XV and VSG signals. Write 0x100000 to Register 0xD1. When using 3-phase HCLK mode, enable this mode before Step 6 by setting Address 0x24 = 0x10. 6. Place the AFE into normal operation and enable clamping (Address 0x00 = 0x04). If using CLO to drive a crystal, set OSC_RST = 1. Wait at least 500 μs before performing Step 8. 7. Load the required registers to configure vertical timing, horizontal timing, high speed timing, and shutter timing. 8. Reset the internal timing core (TGCORE_RST). If a 2× clock is used for CLI, the CLIDIVIDE register (Address 0x0D) should be set to 1 before TGCORE_RST is written (Address 0x14 = 0x01). Wait at least 100 μs before performing Step 9. 9. Bring the VDR_EN pin high. If driving VDR_EN with a GPO, write to the appropriate GPO polarity bit (Address 0x7A) to set the VDR_EN signal high (updated at the next VD). Note that IOVDD must be at the same voltage as VDVDD if GPO is used for VDR_EN. 10. Enable the AD9920A outputs (OUT_CONTROL register, Address 0x11 = 0x01). OUT_CONTROL is a VD-updated register; therefore, the outputs become active after the next VD falling edge. 11. Enable slave mode operation by setting Register 0x0E = 0x100. 12. Start VD and HD timing to synchronize the internal counters and begin operation. VD-updated registers are updated at the first VD falling edge. Note that VDR_EN must remain high to achieve proper vertical outputs during normal operation.

Figure 103. Recommended Power-Up Sequence and Synchronization, Slave Mode

1. Write 0 to the appropriate bit in the GPO_OUTPUT_EN
2. The next VD edge updates Address 0x7A, causing the
3. Write 0x03 to the AFE standby register (Address 0x00) to

place the AD9920A into Standby3 mode.

1. Power down the V-driver supplies.
2. Power down the 3 V and 1.8 V supplies.

Figure 104. Recommended Power-Down Sequence, Master or Slave Mode

• The HD falling edge should be located in the same CLI clock cycle as the VD falling edge or later than the VD falling edge. The HD falling edge should not be located within one cycle prior to the VD falling edge.
• If possible, all start-up serial writes should be performed with VD and HD disabled. This prevents unknown behavior caused by partial updating of registers before all information is loaded. See the Power-Up Sequence for Master Mode section.
• There is an inhibit area for SHPLOC to meet the timing requirement t CLISHP (see Figure 105, Figure 23, and Figure 24). This restriction is necessary to guarantee a stable reset of the H-counter in slave mode.
• When operating the part in slave mode and using a crystal oscillator to generate CLI, it can be very difficult to meet the t HDCLI specification because there is no phase control over the oscillator output. Special care must be taken to meet the critical t HDCLI specification when operating in this condition. VD HD CLI XX XX XX XX XX XX X XXXX XXX X tCLIDLY 06878-105

35.5 CYCLES

1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, AND THEN LATCHED BY SHPLOC (INTERNAL SAMPLING EDGE).
2. INTERNAL H-COUNTER IS ALWAYS RESET 35.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE AT SHDLOC (INTERNAL SAMPLING EDGE).
3. DEPENDING ON THE VALUE OF SHPLOC, H-COUNTER RESET CAN OCCUR 36 OR 37 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHPLOC = 32, SHDLOC = 0 IS SHOWN. IN THIS CASE, THE H-COUNTER RESET OCCURS 36 CLI RISING EDGES AFTER HD FALLING EDGE.
5. HD FALLING EDGE SHOULD OCCUR COINCIDENT WITH THE VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER THE VD FALLING EDGE. HD FALLING

EDGE SHOULD NOT OCCUR WITHIN ONE CYCLE IMMEDIATELY BEFORE THE VD FALLING EDGE. Figure 105. External VD/HD and Internal H-Counter Synchronization, Slave Mode Figure 106. Example of Slave Mode Register Settings to Obtain Desired Toggle Positions

of Address 0x00 control the power-down state of the device. Table 48. Power States Set by Standby Register

00 Normal operation (full power)

01 Standby1 mode

10 Standby2 mode

11 Standby3 mode (lowest power)

polarities are programmable using Address 0x27. until Address 0x7A is used to select them as outputs. frequency, the timing core must be reset for proper operation. that the timing core operates properly. Table 49. Standby Mode Operation for HCLKMODE = 0x1, 0x2, or 0x4 oscillator and external crystal. 2 Standby3 mode takes priority over OUT_CONTROL for determining the output polarities. 3 These polarities assume OUT_CONTROL = high because OUT_CONTROL = low takes priority over Standby1 and Standby2. 4 Standby1 and Standby2 set H and RG drive strength to minimum value (4.3 mA).

Table 50. Standby Mode Operation for HCLKMODE = 0x10 oscillator and external crystal. 2 Standby3 mode takes priority over OUT_CONTROL for determining the output polarities. 3 These polarities assume OUT_CONTROL = high because OUT_CONTROL = low takes priority over Standby1 and Standby2. 4 Standby1 and Standby2 set H and RG drive strength to minimum value (4.3 mA).

rest of the chip. A separate ground for DRVSS is not recommended. decoupled to ground as close as possible to their respective pins. and H8 outputs connected together to drive CCD H2.

• H1 and H3 connected to CCD H1
• H2 and H4 connected to CCD H2
• H5 and H7 connected to CCD H3
• H6 and H8 connected to CCD H4 TYPICAL 3 V SYSTEM The AD9920A typical circuit connections for a 3 V system are shown in Figure 110 and Figure 112. This application uses an external 3.3 V supply, which is connected to the LDO input of the AD9920A. The LDO provides 1.8 V to the AVDD, TCVDD, and DVDD pins. EXTERNAL CRYSTAL APPLICATION The AD9920A contains an on-chip oscillator for driving an external crystal. Figure 108 shows an example application using a typical 27 MHz crystal. There is an internal feedback resistor (typical value ≈ 7 MΩ). However, in the event that the internal resistance is too high and prevents proper crystal operation, an external resistor can be added in parallel. The value of this external resistor is typically between 1 MΩ and 2 MΩ. For the exact value of this resistor and other necessary external resistors and capacitors, it is best to consult the crystal manufacturer. Note that a 2× crystal is not recommended for use with the CLO oscillator circuit. The crystal frequency should not exceed 40.5 MHz. 5pF TO 20pF 5pF TO 20pF CLI CLO AD9920A XTAL ~7MΩ USER DEFINED ~375Ω J5 K5 06878-108

Figure 108. Crystal Application Using CLI/CLO

6 GENERAL-PURPOSE OUTPUTS

Figure 109. Typical 1.8 V Circuit Configuration in Legacy Mode (18-Channel Mode)

Figure 110. Typical 3 V Circuit Configuration in Legacy Mode (18-Channel Mode)

Figure 111. Typical 1.8 V Circuit Configuration in 19-Channel Mode

Figure 112. Typical 3 V Circuit Configuration in 19-Channel Mode

V-pattern groups and the number of V-sequences. occupies 16 register addresses. V-sequences plus the number of V-sequences multiplied by 40. occupy a continuous block of addresses. SEQNUM = 4, the V-sequences occupy 160 address locations. Therefore, the field registers begin at 0x530 (that is, 0x490 + 160). The AD9920A address space contains many unused addresses. carefully so that undefined registers are not written to. Figure 115. Layout of AD9920A Registers

3 V-PATTERN GROUPS

4 V-SEQUENCES

2 FIELDS

Figure 116. Example Register Configuration

column that identifies when each register is updated. Table 51. Register Update Locations register is immediately updated. VD Register is updated at the next VD falling edge. registers are not affected by the update register. start of the SG active line. power-up and reset functions. register, the last one done before SCP1 is the one that is updated. these registers during SCP locations. Figure 117. Register Update Locations (See Table 51 for Definitions)

When an address contains fewer than 28 data bits, all remaining bits must be written as 0s. Table 52. AFE Registers 0x00 [1:0] 0x03 SCK STANDBY Standby modes. 0 = normal operation (full power). 3 = Standby3 mode (lowest power). [2] 0x01 CLPENABLE 0 = disable OB clamp. [3] 0 CLPSPEED 0 = select normal OB clamp settling. 1 = select fast OB clamp settling. [4] 0 FASTUPDATE 0 = ignore CDS gain. 1 = very fast clamping when CDS gain is updated. [5] 0 PBLK_LVL 0 = blank data outputs to 0 during PBLK. 1 = blank data outputs to programmed clamp level during PBLK. [6] 0 DCBYP 0 = enable input dc restore circuit during PBLK. 1 = disable input dc restore circuit during PBLK. 0x01 [0] 0 SCK DOUTDISABLE 0 = data outputs are driven. 1 = data outputs are three-stated. [1] 0 DOUTLATCH 0 = latch data outputs using DOUTPHASE register setting. 1 = output latch is transparent. [2] 0 GRAYEN 1 = enable gray coding of digital data output. 0x02 [0] 0 VD Test Do not access, or set to 0. 0x03 [23:0] 0xFFFFFF VD Test Do not access, or set to 0xFFFFFF. 0x04 [2:0] 0 VD CDSGAIN CDS gain setting. All other values are invalid. 0x05 [9:0] 0x0F VD VGAGAIN VGA gain. 6 dB to 42 dB (0.035 dB per step). 0x06 [9:0] 0x1EC VD CLAMPLEVEL Optical black clamp level. 0 LSB to 255 LSB (0.25 LSB per step). 0x07 [27:0] 0 VD Test Do not access, or set to 0. 0x08 [27:0] 0 VD Test Do not access, or set to 0. 0x09 [27:0] 0 VD Test Do not access, or set to 0. 0x0A [27:0] 0 VD Test Do not access, or set to 0. 0x0B [27:0] 0 SCK UNUSED Do not access, or set to 0. 0x0C [27:0] 0 SCK Test Do not access, or set to 0. 0x0D [0] 0 VD CLIDIVIDE 0 = do not divide CLI frequency. 1 = divide CLI frequency by 2. [7:1] 0 Test Do not access, or set to 0. 0x0E [7:0] 0 SCK Test Set to 0. [8] 0 VDHD_IE VD/HD input enable. Set to 1 to enable VD/HD inputs for slave mode.

Table 53. Miscellaneous Registers 0x10 [0] 0 SCK SW_RST Software reset. Bit self-clears to 0 when a reset occurs. 1 = reset Address 0x00 to Address 0xFF back to default values. 0x11 [0] 0 VD OUT_CONTROL 0 = make all outputs dc inactive. 1 = enable outputs at next VD edge. 0x12 [0] 0x01 SCK RST_SYNC_EN 0 = configure SYNC/RST as SYNC pin. 1 = configure SYNC/RST as RST pin (default configuration is RST). [4:1] 0 Test Test mode only. Must be set to 0. 0x13 [0] 0x01 SCK SYNCENABLE 1 = external synchronization enable. Configure SYNC/RST pin as an input. [1] 0 SYNCPOL SYNC active polarity. [2] 0 SYNCSUSPEND Suspend clocks during SYNC active pulse. [3] 0 ENH_SYNC_EN 1 = enable enhanced sync/shutter operations. [4] 0 SYNC_MASK_HD 1 = mask HD during SYNCSUSPEND. [5] 0x01 SYNC_MASK_VD 1 = mask VD during SYNCSUSPEND. [6] 0x01 SYNC_MASK_V 1 = mask XV outputs during SYNCSUSPEND. [7] 0 Test Test mode only. Must be set to 0. [12:8] 0 Test Test mode only. Must be set to 0. [13] 0 Test Test mode only. Must be set to 0. [14] 0 SYNC_EDGE_EN 1 = enable SYNC to use only one edge to reset. [15] 0 SYNC_RST_SHUTEN 1 = enable reset of the shutter control after SYNC operation occurs. [16] 0 GPO_RST_SYNC 1 = reset shutter and GPO control at SYNC operation. [17] 0 SYNC_CNT_INC 1 = increment field counter by 1 when SYNC occurs. [19:18] 0 UNUSED Set unused bits to 0. [23:20] 0 Test Test mode only. Must be set to 0. [24] 0 SWSYNC 1 = initiate software SYNC event (self-clears to 0 after SYNC). [25] 0 REG_RST_SHUT 1 = force shutter control to reset until REG_RST_SHUT = 0. 0x14 [0] 0 SCK TGCORE_RST Timing core reset bar. 0x15 [0] 0 SCK OSC_RST CLO oscillator reset bar. 0 = oscillator in power-down state. 1 = resume oscillator operation. 0x16 [27:0] 0x01 SCK Test Test mode only. Must be set to 1. [13] 0 PREVENTUP Prevents the update of the VD-updated registers. 1 = prevent update of VD-updated registers. 0x18 [27:0] 0 SCK Test Test mode only. Set to 0. 0x19 [27:0] 0 SCK Test Test mode only. Set to 0. 0x1A [27:0] 0 SCK Test Test mode only. Set to 0. 0x1B [27:0] 0x0A SCK Test Test mode only. Set to 0x0A. 0x1C [23:0] 0 SCK VSGSELECT 1 = each bit selects XV pulses for use as VSG pulses. 0x1D [23:0] 0 SCK VSGMASK_CTL VSG masking. Overrides settings in field registers when enabled. [24] 0 VSGMASK_CTL_EN 0 = disable VSGMASK_CTL bits. VSG masking is controlled by field registers. 1 = enable VSGMASK_CTL bits to control VSG masking. 0x1E [27] 0 SCK UNUSED Do not access, or set to 0. 0x1F [0] 0x01 SCK HCNT14_EN 1 = enable 14-bit H-counter. [1] 0x01 PBLK_MASK_EN 1 = disable clamp operation if PBLK is active at the same time as CLPOB.

Table 54. VD/HD Registers 0x20 [0] 0 SCK MASTER VD/HD master or slave mode. 0 = slave mode, 1 = master mode. 0x21 [0] 0 VD VDHDPOL VD/HD active polarity. 0 = low, 1 = high. 0x22 [12:0] 0 VD HDRISE Rising edge location for HD. Minimum value is 36 pixels. [25:13] 0 VDRISE Rising edge location for VD. Table 55. I/O Registers 0x23 [0] 0 SCK OSC_NVR Oscillator normal voltage range. Set to match CLIVDD supply voltage. [1] 0 XV_NVR XV output normal voltage range. Set to match VDVDD supply voltage. [2] 0 IO_NVR I/O normal voltage range. Set to match IOVDD supply voltage. [3] 0 DATA_NVR Data pin normal voltage range. Set to match DRVDD supply voltage. [4] 0 Test Test use only. Set to 0. [5] 0 Test Test use only. Set to 0. [6] 0 Test Test use only. Set to 0. 0x24 [4:0] 0x01 SCK HCLKMODE Selects HCLK output configuration. Should be written to desired value. Note that all other settings are invalid. [5] 0 Test Test use only. Set to 0. 0x25 [24:0] 0 SCK VT_STBY12 Bits[23:0]: Standby1 and Standby2 polarity for XV[23:0]. Bit 24: Standby1 and Standby2 polarity for XSUBCK. Settings also apply when OUT_CONTROL = low. 0x26 [24:0] 0 SCK VT_STBY3 Bits[23:0]: Standby3 polarity for XV[23:0]. Bit 24: Standby3 polarity for XSUBCK. 0x27 [7:0] 0 SCK GP_STDBY12 Standby1 and Standby2 polarity for GPO outputs. Settings also apply when OUT_CONTROL = low. [15:8] 0 GP_STDBY3 Standby3 polarity for GPO outputs. Table 56. Memory Configuration and Mode Registers 0x28 [4:0] 0 SCK VPATNUM Total number of V-pattern groups. [9:5] 0 SEQNUM Total number of V-sequences. 0x29 [27] 0 SCK UNUSED Do not access, or set to 0. 0x2A [2:0] 0 SCK Mode Total number of fields in the mode register. 0x2B [4:0] 0 SCK FIELD1 Selected first field in the mode register. [9:5] 0 FIELD2 Selected second field in the mode register. [14:10] 0 FIELD3 Selected third field in the mode register. [19:15] 0 FIELD4 Selected fourth field in the mode register. [24:20] 0 FIELD5 Selected fifth field in the mode register.

0x2C [4:0] 0 SCK FIELD6 Selected sixth field in the mode register. [9:5] 0 FIELD7 Selected seventh field in the mode register. 0x2D [27] 0 SCK UNUSED Do not access, or set to 0. 0x2E [27] 0 SCK UNUSED Do not access, or set to 0. 0x2F [27] 0 SCK UNUSED Do not access, or set to 0. Table 57. Timing Core Registers 0x30 [5:0] 0 SCK H1POSLOC H1 rising edge location in HCLK Mode 1, Mode 2, and Mode 3. Phase 3 (H7/H8) rising edge location in 3-phase mode. [13:8] 0x20 H1NEGLOC H1 falling edge location in HCLK Mode 1, Mode 2, and Mode 3. Phase 3 (H7/H8) falling edge location in 3-phase mode. [16] 0x01 Test Test use only. Set to 1. 0x31 [5:0] 0 SCK H2POSLOC H2 rising edge location in HCLK Mode 2. H5 rising edge location in HCLK Mode 3. Phase 2 (H5/H6) rising edge location in 3-phase mode. [13:8] 0x20 H2NEGLOC H2 falling edge location in HCLK Mode 2. H5 falling edge location in HCLK Mode 3. Phase 2 (H5/H6) falling edge location in 3-phase mode. [16] 0x01 Test Test use only. Set to 1. 0x32 [5:0] 0 SCK HLPOSLOC HL rising edge location. [13:8] 0x20 HLNEGLOC HL falling edge location. [16] 0x01 Test Test use only. Set to 1. 0x33 [5:0] 0 SCK H3P1POSLOC Phase 1 (H1/H2) rising edge location in 3-phase mode. [13:8] 0x20 H3P1NEGLOC Phase 1 (H1/H2) falling edge location in 3-phase mode. [16] 0x01 Test Test use only. Set to 1. 0x34 [5:0] 0 SCK RGPOSLOC RG rising edge location. [13:8] 0x10 RGNEGLOC RG falling edge location. [16] 0x01 Test Test use only. Set to 1. [1] 0 H2HBLKRETIME Retime H2 HBLK to internal clock. [2] 0 HLHBLKRETIME Retime HL HBLK to internal clock. [3] 0 H3PHBLKRETIME Retime H3 HBLK to internal clock. [7:4] 0 HCLK_WIDTH Enables wide H-clocks during HBLK interval. Set to 0 to disable. [8] 0 Test Test use only. Set to 0. [9] 0 HLHBLK 1 = enable HBLK for HL. [19:10] 0 Test Test use only. Set to 0. [20] 0 H1FINERETIME Adds one additional retime operation to H1 HBLK signal. [21] 0 H2FINERETIME Adds one additional retime operation to H2 HBLK signal. [22] 0 HLFINERETIME Adds one additional retime operation to HL HBLK signal.

0x36 [2:0] 0x01 SCK H1DRV H1 drive strength. [6:4] 0x1 H2DRV H2 drive strength (same range as H1DRV). [10:8] 0x1 H3DRV H3 drive strength (same range as H1DRV). [14:12] 0x1 H4DRV H4 drive strength (same range as H1DRV). [18:16] 0x1 HLDRV HL drive strength. [22:20] 0x1 RGDRV RG drive strength (same range as HLDRV). 0x37 [2:0] 0x1 SCK H5DRV H5 drive strength (same range as H1DRV). [6:4] 0x1 H6DRV H6 drive strength (same range as H1DRV). [10:8] 0x1 H7DRV H7 drive strength (same range as H1DRV). [14:12] 0x1 H8DRV H8 drive strength (same range as H1DRV). [18:16] 0x1 Test Test use only. Set to 1. [22:20] 0x1 Test Test use only. Set to 1. 0x38 [5:0] 0 SCK SHDLOC SHD sampling edge location. [13:8] 0x20 SHPLOC SHP sampling edge location. [21:16] 0x10 SHPWIDTH SHP width (controls input dc restore switch active time). 0x39 [5:0] 0 SCK DOUTPHASEP DOUT phase control, positive edge. Specifies location of DOUT. 32 edges to maintain 50% duty cycle of internal DOUTPHASE clocking. [18:17] 0 Test Test use only. Set to 0. [19] 0 DCLKINV Invert DCLK output. [22:20] 0 Test Test use only. Set to 0. 0x3A [27] 0 SCK Test Do not access, or set to 0. 0x3B [27] 0 SCK UNUSED Do not access, or set to 0. 0x3C [27] 0 SCK Test Do not access, or set to 0. 0x3D [27] 0 SCK UNUSED Do not access, or set to 0. 0x3E [27] 0 SCK Test Do not access, or set to 0. 0x3F [27] 0 SCK UNUSED Do not access, or set to 0. Table 58. Test Registers—Do Not Access 0x40 to 0x6F Test registers. Do not access.

Table 59. Shutter and GPO Registers 0x70 [2:0] 0 VD PRIMARY_ACTION Select action for primary and secondary counters. [5:3] 0 SECOND_ACTION 0 = idle (do nothing): autoreset on VD. 1 = activate counter (primary: automatic exposure/read). 2 = RapidShot: wrap/repeat counter. 3 = ShotTimer: delay start of count. 4 = ShotTimer with RapidShot. [13:6] 0 MANUAL_TRIG 1: manual trigger for GP signals when Protocol 1 is selected. 0x71 [12:0] 0 VD PRIMARY_MAX Primary counter maximum value. [24:13] 0 SECOND_MAX Secondary counter maximum value. [27:25] 0 VDHD_MASK Mask VD/HD during counter operation. before the first count (exposure). 0x73 [2:0] 0 VD GP1_PROTOCOL Selects protocol for each general-purpose signal. [5:3] 0 GP2_PROTOCOL 0 = idle. [11:9] 0 GP4_PROTOCOL 2 = test use only. [14:12] 0 GP5_PROTOCOL 3 = test use only. [17:15] 0 GP6_PROTOCOL 4 = link to mode counter. [20:18] 0 GP7_PROTOCOL 5 = link to primary counter. [23:21] 0 GP8_PROTOCOL 6 = link to secondary counter. 0x74 [12:0] 0 VD SGMASK_NUM Exposure duration (number of fields to mask SG) for LS operation. [25:13] 0 VD/SG SUBCKMASK_NUM Exposure + readout duration (number of fields to mask SUBCK) for LS. (Register 0x78 and Register 0x74, Bits[27:13]) are updated at SG line. 1 = updated at update line (VD updated). [27] 0 VD/SG SUBCKMASK_SKIP1 Skip the SUBCK mask for the first exposure field only. 0x75 [0] 0 VD/SG Test Test purpose only. Must be set to 0. [13:1] 0 SUBCKSUPPRESS Number of lines after VSG line to begin SUBCK pulses. [26:14] 0 SUBCKNUM Number of SUBCK pulses per field. Must be set less than VDLEN. [27] 0 SG_SUPPRESS Suppress the SG and allow SUBCK to finish at SUBCKNUM. 0x76 [0] 0 VD/SG SUBCK_POL SUBCK start polarity. [1] 0 TESTMODE Test use only. Must be set to 0. 0x77 [13:0] 0 VD/SG SUBCK_TOG1 SUBCK Toggle Position 1. [27:14] 0 SUBCK_TOG2 SUBCK Toggle Position 2. 0x78 [13:0] 0 VD/SG SUBCKHP_TOG1 High precision SUBCK Toggle Position 1. [27:14] 0 SUBCKHP_TOG2 High precision SUBCK Toggle Position 2. 0x79 [25:0] 0 VD TESTMODE Test use only. Must be set to 0.

Rev. B | Page 102 of 112 Address Data Bits Default Value Update Type Name Description 0x7A [0] 0 VD GP1_POL GP1 low/high start polarity. [1] 0 GP2_POL GP2 low/high start polarity. [2] 0 GP3_POL GP3 low/high start polarity. [3] 0 GP4_POL GP4 low/high start polarity. [4] 0 GP5_POL GP5 low/high start polarity. [5] 0 GP6_POL GP6 low/high start polarity. [6] 0 GP7_POL GP7 low/high start polarity. [7] 0 GP8_POL GP8 low/high start polarity. [8] 0x01 SEL_GP1 1 = GP1 signal is selected for GPO1 output. 0 = internal signal is selected. [9] 0x01 SEL_GP2 1 = GP2 signal is selected for GPO2 output. 0 = internal signal is selected. [10] 0x01 SEL_GP3 1 = GP3 signal is selected for GPO3 output. 0 = internal signal is selected. [11] 0x01 SEL_GP4 1 = GP4 signal is selected for GPO4 output. 0 = XSUBCK is selected. [12] 0x01 SEL_GP5 1 = GP5 signal is selected for GPO5 output. 0 = XV21 is selected. [13] 0x01 SEL_GP6 1 = GP6 signal is selected for GPO6 output. 0 = XV22 is selected. [14] 0x01 SEL_GP7 1 = GP7 signal is selected for GPO7 output. 0 = XV23 is selected. [15] 0x01 SEL_GP8 1 = GP8 signal is selected for GPO8 output. 0 = XV24 is selected. [23:16] 0 GPO_OUTPUT_EN 1 = GPO enabled. 0 = GPO is high-Z (default). [24] 0 GPO5_OVERRIDE 1 = when GPO5 is configured as an input, this register overrides the internal OUT_CONT. [25] 0 GPO6_OVERRIDE 1 = when GPO6 is configured as an input, this register overrides the internal HBLK. [26] 0 GPO7_OVERRIDE 1 = when GPO7 is configured as an input, this register overrides the internal CLPOB. [27] 0 GPO8_OVERRIDE 1 = when GPO8 is configured as an input, this register overrides the internal PBLK. 0x7B [7:0] 0 VD GPx_USE_LUT Enable LUT for each GPO signal. 1 = enable. 0 = disable (use normal GP signal). [11:8] 0000 LUT_FOR_GP12 Two-input lookup table results. [15:12] 0000 LUT_FOR_GP34 Examples: {LUT_FOR_GP12} Å [GP2:GP1]. [19:16] 0000 LUT_FOR_GP56 {0110} = GP2 XOR GP1; {1110} = GP2 OR GP1. [23:20] 0000 LUT_FOR_GP78 {0111} = GP2 NAND GP1; {1000} = GP2 AND GP1. 0x7C [12:0] 0 VD GP1_TOG1_FD General-Purpose Signal 1, first toggle position, field location. [25:13] 0 GP1_TOG1_LN General-Purpose Signal 1, first toggle position, line location. 0x7D [12:0] 0 VD GP1_TOG1_PX General-Purpose Signal 1, first toggle position, pixel location. [25:13] 0 GP1_TOG2_FD General-Purpose Signal 1, second toggle position, field location. 0x7E [12:0] 0 VD GP1_TOG2_LN General-Purpose Signal 1, second toggle position, line location. [25:13] 0 GP1_TOG2_PX General-Purpose Signal 1, second toggle position, pixel location. 0x7F [12:0] 0 VD GP1_TOG3_FD General-Purpose Signal 1, third toggle position, field location. [25:13] 0 GP1_TOG3_LN General-Purpose Signal 1, third toggle position, line location. 0x80 [12:0] 0 VD GP1_TOG3_PX General-Purpose Signal 1, third toggle position, pixel location. [25:13] 0 GP1_TOG4_FD General-Purpose Signal 1, fourth toggle position, field location. 0x81 [12:0] 0 VD GP1_TOG4_LN General-Purpose Signal 1, fourth toggle position, line location. [25:13] 0 GP1_TOG4_PX General-Purpose Signal 1, fourth toggle position, pixel location. 0x82 [12:0] 0 VD GP2_TOG1_FD General-Purpose Signal 2, first toggle position, field location. [25:13] 0 GP2_TOG1_LN General-Purpose Signal 2, first toggle position, line location. 0x83 [12:0] 0 VD GP2_TOG1_PX General-Purpose Signal 2, first toggle position, pixel location. [25:13] 0 GP2_TOG2_FD General-Purpose Signal 2, second toggle position, field location. 0x84 [12:0] 0 VD GP2_TOG2_LN General-Purpose Signal 2, second toggle position, line location. [25:13] 0 GP2_TOG2_PX General-Purpose Signal 2, second toggle position, pixel location.

Rev. B | Page 103 of 112 Address Data Bits Default Value Update Type Name Description 0x85 [12:0] 0 VD GP2_TOG3_FD General-Purpose Signal 2, third toggle position, field location. [25:13] 0 GP2_TOG3_LN General-Purpose Signal 2, third toggle position, line location. 0x86 [12:0] 0 VD GP2_TOG3_PX General-Purpose Signal 2, third toggle position, pixel location. [25:13] 0 GP2_TOG4_FD General-Purpose Signal 2, fourth toggle position, field location. 0x87 [12:0] 0 VD GP2_TOG4_LN General-Purpose Signal 2, fourth toggle position, line location. [25:13] 0 GP2_TOG4_PX General-Purpose Signal 2, fourth toggle position, pixel location. 0x88 [12:0] 0 VD GP3_TOG1_FD General-Purpose Signal 3, first toggle position, field location. [25:13] 0 GP3_TOG1_LN General-Purpose Signal 3, first toggle position, line location. 0x89 [12:0] 0 VD GP3_TOG1_PX General-Purpose Signal 3, first toggle position, pixel location. [25:13] 0 GP3_TOG2_FD General-Purpose Signal 3, second toggle position, field location. 0x8A [12:0] 0 VD GP3_TOG2_LN General-Purpose Signal 3, second toggle position, line location. [25:13] 0 GP3_TOG2_PX General-Purpose Signal 3, second toggle position, pixel location. 0x8B [12:0] 0 VD GP3_TOG3_FD General-Purpose Signal 3, third toggle position, field location. [25:13] 0 GP3_TOG3_LN General-Purpose Signal 3, third toggle position, line location. 0x8C [12:0] 0 VD GP3_TOG3_PX General-Purpose Signal 3, third toggle position, pixel location. [25:13] 0 GP3_TOG4_FD General-Purpose Signal 3, fourth toggle position, field location. 0x8D [12:0] 0 VD GP3_TOG4_LN General-Purpose Signal 3, fourth toggle position, line location. [25:13] 0 GP3_TOG4_PX General-Purpose Signal 3, fourth toggle position, pixel location. 0x8E [12:0] 0 VD GP4_TOG1_FD General-Purpose Signal 4, first toggle position, field location. [25:13] 0 GP4_TOG1_LN General-Purpose Signal 4, first toggle position, line location. 0x8F [12:0] 0 VD GP4_TOG1_PX General-Purpose Signal 4, first toggle position, pixel location. [25:13] 0 GP4_TOG2_FD General-Purpose Signal 4, second toggle position, field location. 0x90 [12:0] 0 VD GP4_TOG2_LN General-Purpose Signal 4, second toggle position, line location. [25:13] 0 GP4_TOG2_PX General-Purpose Signal 4, second toggle position, pixel location. 0x91 [12:0] 0 VD GP4_TOG3_FD General-Purpose Signal 4, third toggle position, field location. [25:13] 0 GP4_TOG3_LN General-Purpose Signal 4, third toggle position, line location. 0x92 [12:0] 0 VD GP4_TOG3_PX General-Purpose Signal 4, third toggle position, pixel location. [25:13] 0 GP4_TOG4_FD General-Purpose Signal 4, fourth toggle position, field location. 0x93 [12:0] 0 VD GP4_TOG4_LN General-Purpose Signal 4, fourth toggle position, line location. [25:13] 0 GP4_TOG4_PX General-Purpose Signal 4, fourth toggle position, pixel location. 0x94 [12:0] 0 VD GP5_TOG1_FD General-Purpose Signal 5, first toggle position, field location. [25:13] 0 GP5_TOG1_LN General-Purpose Signal 5, first toggle position, line location. 0x95 [12:0] 0 VD GP5_TOG1_PX General-Purpose Signal 5, first toggle position, pixel location. [25:13] 0 GP5_TOG2_FD General-Purpose Signal 5, second toggle position, field location. 0x96 [12:0] 0 VD GP5_TOG2_LN General-Purpose Signal 5, second toggle position, line location. [25:13] 0 GP5_TOG2_PX General-Purpose Signal 5, second toggle position, pixel location. 0x97 [12:0] 0 VD GP5_TOG3_FD General-Purpose Signal 5, third toggle position, field location. [25:13] 0 GP5_TOG3_LN General-Purpose Signal 5, third toggle position, line location. 0x98 [12:0] 0 VD GP5_TOG3_PX General-Purpose Signal 5, third toggle position, pixel location. [25:13] 0 GP5_TOG4_FD General-Purpose Signal 5, fourth toggle position, field location. 0x99 [12:0] 0 VD GP5_TOG4_LN General-Purpose Signal 5, fourth toggle position, line location. [25:13] 0 GP5_TOG4_PX General-Purpose Signal 5, fourth toggle position, pixel location. 0x9A [12:0] 0 VD GP6_TOG1_FD General-Purpose Signal 6, first toggle position, field location. [25:13] 0 GP6_TOG1_LN General-Purpose Signal 6, first toggle position, line location. 0x9B [12:0] 0 VD GP6_TOG1_PX General-Purpose Signal 6, first toggle position, pixel location. [25:13] 0 GP6_TOG2_FD General-Purpose Signal 6, second toggle position, field location. 0x9C [12:0] 0 VD GP6_TOG2_LN General-Purpose Signal 6, second toggle position, line location. [25:13] 0 GP6_TOG2_PX General-Purpose Signal 6, second toggle position, pixel location. 0x9D [12:0] 0 VD GP6_TOG3_FD General-Purpose Signal 6, third toggle position, field location. [25:13] 0 GP6_TOG3_LN General-Purpose Signal 6, third toggle position, line location.

0x9E [12:0] 0 VD GP6_TOG3_PX General-Purpose Signal 6, third toggle position, pixel location. [25:13] 0 GP6_TOG4_FD General-Purpose Signal 6, fourth toggle position, field location. 0x9F [12:0] 0 VD GP6_TOG4_LN General-Purpose Signal 6, fourth toggle position, line location. [25:13] 0 GP6_TOG4_PX General-Purpose Signal 6, fourth toggle position, pixel location. 0xA0 [12:0] 0 VD GP7_TOG1_FD General-Purpose Signal 7, first toggle position, field location. [25:13] 0 GP7_TOG1_LN General-Purpose Signal 7, first toggle position, line location. 0xA1 [12:0] 0 VD GP7_TOG1_PX General-Purpose Signal 7, first toggle position, pixel location. [25:13] 0 GP7_TOG2_FD General-Purpose Signal 7, second toggle position, field location. 0xA2 [12:0] 0 VD GP7_TOG2_LN General-Purpose Signal 7, second toggle position, line location. [25:13] 0 GP7_TOG2_PX General-Purpose Signal 7, second toggle position, pixel location. 0xA3 [12:0] 0 VD GP7_TOG3_FD General-Purpose Signal 7, third toggle position, field location. [25:13] 0 GP7_TOG3_LN General-Purpose Signal 7, third toggle position, line location. 0xA4 [12:0] 0 VD GP7_TOG3_PX General-Purpose Signal 7, third toggle position, pixel location. [25:13] 0 GP7_TOG4_FD General-Purpose Signal 7, fourth toggle position, field location. 0xA5 [12:0] 0 VD GP7_TOG4_LN General-Purpose Signal 7, fourth toggle position, line location. [25:13] 0 GP7_TOG4_PX General-Purpose Signal 7, fourth toggle position, pixel location. 0xA6 [12:0] 0 VD GP8_TOG1_FD General-Purpose Signal 8, first toggle position, field location. [25:13] 0 GP8_TOG1_LN General-Purpose Signal 8, first toggle position, line location. 0xA7 [12:0] 0 VD GP8_TOG1_PX General-Purpose Signal 8, first toggle position, pixel location. [25:13] 0 GP8_TOG2_FD General-Purpose Signal 8, second toggle position, field location. 0xA8 [12:0] 0 VD GP8_TOG2_LN General-Purpose Signal 8, second toggle position, line location. [25:13] 0 GP8_TOG2_PX General-Purpose Signal 8, second toggle position, pixel location. 0xA9 [12:0] 0 VD GP8_TOG3_FD General-Purpose Signal 8, third toggle position, field location. [25:13] 0 GP8_TOG3_LN General-Purpose Signal 8, third toggle position, line location. 0xAA [12:0] 0 VD GP8_TOG3_PX General-Purpose Signal 8, third toggle position, pixel location. [25:13] 0 GP8_TOG4_FD General-Purpose Signal 8, fourth toggle position, field location. 0xAB [12:0] 0 VD GP8_TOG4_LN General-Purpose Signal 8, fourth toggle position, line location. [25:13] 0 GP8_TOG4_PX General-Purpose Signal 8, fourth toggle position, pixel location. 0xAC [7:0] 0 VD GP_LN_MODE 1 = outputs specified GP pulse on every line. 0xAD [27] 0 VD UNUSED Do not access, or set to 0. 0xAE [27] 0 VD UNUSED Do not access, or set to 0. 0xAF [27] 0 VD UNUSED Do not access, or set to 0. Table 60. Update Control Registers 0xB0 [15:0] 0x5803 SCK AFE_UPDT_SCK Each bit corresponds to one address location. Bit 0: 1 = update Address 0x00 on SL rising edge. Bit 1: 1 = update Address 0x01 on SL rising edge. Bit 15: 1 = update Address 0x0F on SL rising edge. 0xB1 [15:0] 0xA7FC SCK AFE_UPDT_VD Each bit corresponds to one address location. Bit 0: 1 = update Address 0x00 on VD rising edge. Bit 1: 1 = update Address 0x01 on VD rising edge. Bit 15: 1 = update Address 0x0F on VD rising edge. 0xB2 [15:0] 0xD8FD SCK MISC_UPDT_SCK Enable SCK update of miscellaneous registers, Address 0x10 to Address 0x1F . 0xB3 [15:0] 0x2702 SCK MISC_UPDT_VD Enable VD update of miscellaneous registers, Address 0x10 to Address 0x1F . 0xB4 [15:0] 0xFFF9 SCK VDHD_UPDT_SCK Enable SCK update of VD/HD registers, Address 0x20 to Address 0x2F. 0xB5 [15:0] 0x0006 SCK VDHD_UPDT_VD Enable VD update of VD/HD registers, Address 0x20 to Address 0x2F. 0xB6 [15:0] 0xFFFF SCK TC_UPDT_SCK Enable SCK update of timing core registers, Address 0x30 to Address 0x3F . 0xB7 [15:0] 0000 SCK TC_UPDT_VD Enable VD update of timing core registers, Address 0x30 to Address 0x3F. 0xB8 [27:0] 0x04 Test Test register. Do not access, or write to 0x04. 0xB9 [27:0] 0 UNUSED Do not access, or write to 0x00.

0xBA [27:0] 0 UNUSED Do not access, or write to 0x00. 0xBB [27:0] 0 UNUSED Do not access, or write to 0x00. 0xBC [27:0] 0 UNUSED Do not access, or write to 0x00. 0xBD [27:0] 0 UNUSED Do not access, or write to 0x00. 0xBE [27:0] 0 UNUSED Do not access, or write to 0x00. 0xBF [27:0] 0 UNUSED Do not access, or write to 0x00. Table 61. Extra Registers 0xC0 [27:0] 0 VD Test Do not access, or write to 0x00. 0xC1 [27:0] 0 VD Test Do not access, or write to 0x00. 0xC2 [27:0] 0 VD Test Do not access, or write to 0x00. 0xC3 [7:0] 0 SCK GPO_MASK_HIGH 1 = masks GPO[x] to high. Takes priority over normal operation. 0xC4 [27:0] 0 VD Test Test register. Do not access, or set to 0. 0xC5 [27:0] 0x1516 SCK Test Test register. Do not access, or set to 0x1516. 0xC6 [27:0] 0 UNUSED Unused register. Do not access, or set to 0. 0xC7 [27:0] 0 UNUSED Unused register. Do not access, or set to 0. 0xC8 [27:0] 0 SCK Test Test register. Do not access, or set to 0. 0xC9 [27:0] 0xFFFF SCK Test Test register. Do not access, or set to 0xFFFF. 0xCA [27:0] 0 SCK Test Test register. Do not access, or set to 0. 0xCB [27:0] 0 SCK Test Test register. Do not access, or set to 0. 0xCC [27:0] 0 UNUSED Unused register. Do not access, or set to 0. 0xCD [27:0] 0 UNUSED Unused register. Do not access, or set to 0. 0xCE [27:0] 0 UNUSED Unused register. Do not access, or set to 0. 0xCF [27:0] 0 UNUSED Unused register. Do not access, or set to 0. 0xD0 [27:0] 0 SCK Test Test register. Do not access, or set to 0. 0xD1 [19:0] 0 SCK Test Test use only. Set to 0. [20] 0 STARTUP Must be set to 1 to start the device. 0xD2 [27:0] 0 SCK Test Test register. Do not access, or set to 0. 0xD3 [27:0] 0 SCK Test Test register. Do not access, or set to 0. 0xD4 [0] 0 SCK Test Test use only. Set to 0. (must also set SEL_GPx bits low). Note that GPO4 to GPO8 continue to output normal GP toggles. [9:2] 0 Test Test use only. Set to 0. 0xD5 [27:0] 0 SCK Test Test use only. Set to 0. 0xD6 [27:0] 0xA10 SCK Test Test use only. Set to 0xA10. 0xD7 [27:0] 0 SCK Test Test use only. Set to 0. 0xD8 [27:0] 0x888 SCK DOUT_STRENGTH Controls drive strength of data output drivers. 0x888 = normal drive strength. 0x848 = weak drive strength. 0x808 = weaker drive strength. 0xD9 [27:0] 0 SCK Test Test use only. Set to 0. 0xDA [27:0] 0 SCK Test Test use only. Set to 0. 0xDB [27:0] SCK Test Test use only. Set to 0. 0xDC [27:0] 0xF7F SCK Test Test use only. Set to 0xF7F. 0xDD [27:0] 0x14 SCK Test Test use only. Set to 0x14.

0xDE [27:0] 0 SCK Test Test use only. Set to 0. 0xDF [27:0] 0 SCK Test Test use only. Set to 0. Table 62. V-Pattern Group (VPAT) Register Map (Default Values Are Undefined) 0x00 [12:0] X SCP XV1TOG1 XV1 Toggle Position 1. [25:13] X XV1TOG2 XV1 Toggle Position 2. 0x01 [12:0] X SCP XV1TOG3 XV1 Toggle Position 3. [25:13] X XV1TOG4 XV1 Toggle Position 4. 0x02 [12:0] X SCP XV2TOG1 XV2 Toggle Position 1. [25:13] X XV2TOG2 XV2 Toggle Position 2. 0x03 [12:0] X SCP XV2TOG3 XV2 Toggle Position 3. [25:13] X XV2TOG4 XV2 Toggle Position 4. 0x04 [12:0] X SCP XV3TOG1 XV3 Toggle Position 1. [25:13] X XV3TOG2 XV3 Toggle Position 2. 0x05 [12:0] X SCP XV3TOG3 XV3 Toggle Position 3. [25:13] X XV3TOG4 XV3 Toggle Position 4. 0x06 [12:0] X SCP XV4TOG1 XV4 Toggle Position 1. [25:13] X XV4TOG2 XV4 Toggle Position 2. 0x07 [12:0] X SCP XV4TOG3 XV4 Toggle Position 3. [25:13] X XV4TOG4 XV4 Toggle Position 4. 0x08 [12:0] X SCP XV5TOG1 XV5 Toggle Position 1. [25:13] X XV5TOG2 XV5 Toggle Position 2. 0x09 [12:0] X SCP XV5TOG3 XV5 Toggle Position 3. [25:13] X XV5TOG4 XV5 Toggle Position 4. 0x0A [12:0] X SCP XV6TOG1 XV6 Toggle Position 1. [25:13] X XV6TOG2 XV6 Toggle Position 2. 0x0B [12:0] X SCP XV6TOG3 XV6 Toggle Position 3. [25:13] X XV6TOG4 XV6 Toggle Position 4. 0x0C [12:0] X SCP XV7TOG1 XV7 Toggle Position 1. [25:13] X XV7TOG2 XV7 Toggle Position 2. 0x0D [12:0] X SCP XV7TOG3 XV7 Toggle Position 3. [25:13] X XV7TOG4 XV7 Toggle Position 4. 0x0E [12:0] X SCP XV8TOG1 XV8 Toggle Position 1. [25:13] X XV8TOG2 XV8 Toggle Position 2. 0x0F [12:0] X SCP XV8TOG3 XV8 Toggle Position 3. [25:13] X XV8TOG4 XV8 Toggle Position 4. 0x10 [12:0] X SCP XV9TOG1 XV9 Toggle Position 1. [25:13] X XV9TOG2 XV9 Toggle Position 2. 0x11 [12:0] X SCP XV9TOG3 XV9 Toggle Position 3. [25:13] X XV9TOG4 XV9 Toggle Position 4. 0x12 [12:0] X SCP XV10TOG1 XV10 Toggle Position 1. [25:13] X XV10TOG2 XV10 Toggle Position 2. 0x13 [12:0] X SCP XV10TOG3 XV10 Toggle Position 3. [25:13] X XV10TOG4 XV10 Toggle Position 4. 0x14 [12:0] X SCP XV11TOG1 XV11 Toggle Position 1. [25:13] X XV11TOG2 XV11 Toggle Position 2. 0x15 [12:0] X SCP XV11TOG3 XV11 Toggle Position 3. [25:13] X XV11TOG4 XV11 Toggle Position 4. 0x16 [12:0] X SCP XV12TOG1 XV12 Toggle Position 1. [25:13] X XV12TOG2 XV12 Toggle Position 2.

Rev. B | Page 107 of 112 Address Data Bits Default Value Update Type Name Description 0x17 [12:0] X SCP XV12TOG3 XV12 Toggle Position 3. [25:13] X XV12TOG4 XV12 Toggle Position 4. 0x18 [12:0] X SCP XV13TOG1 XV13 Toggle Position 1. [25:13] X XV13TOG2 XV13 Toggle Position 2. 0x19 [12:0] X SCP XV13TOG3 XV13 Toggle Position 3. [25:13] X XV13TOG4 XV13 Toggle Position 4. 0x1A [12:0] X SCP XV14TOG1 XV14 Toggle Position 1. [25:13] X XV14TOG2 XV14 Toggle Position 2. 0x1B [12:0] X SCP XV14TOG3 XV14 Toggle Position 3. [25:13] X XV14TOG4 XV14 Toggle Position 4. 0x1C [12:0] X SCP XV15TOG1 XV15 Toggle Position 1. [25:13] X XV15TOG2 XV15 Toggle Position 2. 0x1D [12:0] X SCP XV15TOG3 XV15 Toggle Position 3. [25:13] X XV15TOG4 XV15 Toggle Position 4. 0x1E [12:0] X SCP XV16TOG1 XV16 Toggle Position 1. [25:13] X XV16TOG2 XV16 Toggle Position 2. 0x1F [12:0] X SCP XV16TOG3 XV16 Toggle Position 3. [25:13] X XV16TOG4 XV16 Toggle Position 4. 0x20 [12:0] X SCP XV17TOG1 XV17 Toggle Position 1. [25:13] X XV17TOG2 XV17 Toggle Position 2. 0x21 [12:0] X SCP XV17TOG3 XV17 Toggle Position 3. [25:13] X XV17TOG4 XV17 Toggle Position 4. 0x22 [12:0] X SCP XV18TOG1 XV18 Toggle Position 1. [25:13] X XV18TOG2 XV18 Toggle Position 2. 0x23 [12:0] X SCP XV18TOG3 XV18 Toggle Position 3. [25:13] X XV18TOG4 XV18 Toggle Position 4. 0x24 [12:0] X SCP XV19TOG1 XV19 Toggle Position 1. [25:13] X XV19TOG2 XV19 Toggle Position 2. 0x25 [12:0] X SCP XV19TOG3 XV19 Toggle Position 3. [25:13] X XV19TOG4 XV19 Toggle Position 4. 0x26 [12:0] X SCP XV20TOG1 XV20 Toggle Position 1. [25:13] X XV20TOG2 XV20 Toggle Position 2. 0x27 [12:0] X SCP XV20TOG3 XV20 Toggle Position 3. [25:13] X XV20TOG4 XV20 Toggle Position 4. 0x28 [12:0] X SCP XV21TOG1 XV21 Toggle Position 1. [25:13] X XV21TOG2 XV21 Toggle Position 2. 0x29 [12:0] X SCP XV21TOG3 XV21 Toggle Position 3. [25:13] X XV21TOG4 XV21 Toggle Position 4. 0x2A [12:0] X SCP XV22TOG1 XV22 Toggle Position 1. [25:13] X XV22TOG2 XV22 Toggle Position 2. 0x2B [12:0] X SCP XV22TOG3 XV22 Toggle Position 3. [25:13] X XV22TOG4 XV22 Toggle Position 4. 0x2C [12:0] X SCP XV23TOG1 XV23 Toggle Position 1. [25:13] X XV23TOG2 XV23 Toggle Position 2. 0x2D [12:0] X SCP XV23TOG3 XV23 Toggle Position 3. [25:13] X XV23TOG4 XV23 Toggle Position 4. 0x2E [12:0] X SCP XV24TOG1 XV24 Toggle Position 1. [25:13] X XV24TOG2 XV24 Toggle Position 2. 0x2F [12:0] X SCP XV24TOG3 XV24 Toggle Position 3. [25:13] X XV24TOG4 XV24 Toggle Position 4.

Table 63. V-Sequence (VSEQ) Registers (Default Values Are Undefined) 0x00 [0] X SCP CLPOBPOL CLPOB start polarity. [1] X PBLKPOL PBLK start polarity. [5:2] X HOLD 1 = enable HOLD function for each VPAT group (A, B, C, D). [6] X VSEQALT_EN Special V-sequence alternation enable. [9:7] X SPC_PAT_EN 1 = enable use of special vertical pattern insertion into VPATA sequence. Bit 0: Use VPATB as the special pattern. Bit 1: Use VPATC as the special pattern. Bit 2: Use VPATD as the special pattern. [15:14] X VREP_MODE Defines V-alternation repetition mode. 00 = single-pattern alternation for all groups. 01 = two-pattern alternation for all groups. 11 = four-pattern alternation for Group A; two-pattern for Groups B/C/D. the V-sequence. One bit for each group (A, B, C, and D); Group A is the LSB. Set bit high to enable. Recommended value is enabled. [21:20] X HBLK_MODE Selection of HBLK modes. 00 = HBLK Mode 0 (normal six-toggle operation). 10 = test use only; do not access. 11 = test use only; do not access. [23:22] X Test Test use only. Set to 0. [24] X SUBCK_MASK 1 = enable SUBCK masking feature. 0x01 [13:0] X SCP HDLENE HD line length for even lines. 0x02 [13:0] X SCP HDLENO HD line length for odd lines. when they are configured as VSG pulses (in Miscellaneous Register 0x1C). register. Set equal to VLENA register. register. Set equal to VLENB register. register. Set equal to VLENC register. register. Set equal to VLEND register. 0x06 [23:0] X SCP VPOL Starting polarities for each V-output signal. 0x07 [23:0] X SCP GROUPSEL_0 Select to which group each V1 to V12 signal is assigned.

Rev. B | Page 109 of 112 Address Data Bits Default Value Update Type Name Description 0x08 [23:0] X SCP GROUPSEL_1 Select to which group each V13 to V24 signal is assigned. 00 = Group A. 01 = Group B. 10 = Group C. 11 = Group D. Bits[1:0]: V13. Bits[3:2]: V14. Bits[23:22]: V24. 0x09 [4:0] X SCP VPATSELA Selected VPAT group for Group A, from VPAT Group 0 to Group 31. [9:5] X VPATSELB Selected VPAT group for Group B, from VPAT Group 0 to Group 31. [14:10] X VPATSELC Selected VPAT group for Group C, from VPAT Group 0 to Group 31. [19:15] X VPATSELD Selected VPAT group for Group D, from VPAT Group 0 to Group 31. [20] X SEQ_ALT_INC 1 = increment sequence number on next line. [21] X SEQ_ALT_RST 1 = reset sequence number to sequence defined for that particular region in the field register. 0x0A [12:0] X SCP VSTARTA Start position of selected V-pattern Group A. [25:13] X VLENA Length of selected V-pattern Group A. 0x0B [12:0] X SCP VREPA_1 Number of repetitions for V-pattern Group A for first lines. [25:13] X VREPA_2 Number of repetitions for V-pattern Group A for second lines. 0x0C [12:0] X SCP VREPA_3 Number of repetitions for V-pattern Group A for third lines. [25:13] X VREPA_4 Number of repetitions for V-pattern Group A for fourth lines. 0x0D [12:0] X SCP VSTARTB Start position of selected V-pattern Group B. [25:13] X VLENB Length of selected V-pattern Group B. 0x0E [12:0] X SCP VREPB_ODD Number of repetitions for V-pattern Group B for odd lines. [25:13] X VREPB_EVEN Number of repetitions for V-pattern Group B for even lines. 0x0F [12:0] X SCP VSTARTC Start position of selected V-pattern Group C. [25:13] X VLENC Length of selected V-pattern Group C. 0x10 [12:0] X SCP VREPC_ODD Number of repetitions for V-pattern Group C for odd lines. [25:13] X VREPC_EVEN Number of repetitions for V-pattern Group C for even lines. 0x11 [12:0] X SCP VSTARTD Start position of selected V-pattern Group D. [25:13] X VLEND Length of selected V-pattern Group D. 0x12 [12:0] X SCP VREPD_ODD Number of repetitions for V-pattern Group D for odd lines. [25:13] X VREPD_EVEN Number of repetitions for V-pattern Group D for even lines. 0x13 [12:0] X SCP FREEZE1 Holds the V-outputs at their current levels. [25:13] X RESUME1 Resumes the operation of V-outputs to finish the pattern. 0x14 [12:0] X SCP FREEZE2 Holds the V-outputs at their current levels. [25:13] X RESUME2 Resumes the operation of V-outputs to finish the pattern. 0x15 [12:0] X SCP FREEZE3 Holds the V-outputs at their current levels. [25:13] X RESUME3 Resumes the operation of V-outputs to finish the pattern. 0x16 [12:0] X SCP FREEZE4 Holds the V-outputs at their current levels. [25:13] X RESUME4 Resumes the operation of V-outputs to finish the pattern. 0x17 [12:0] X SCP HBLKSTART Start location for HBLK in HBLK Mode 0 and HBLK Mode 1. [25:13] X HBLKEND End location for HBLK in HBLK Mode 0 and HBLK Mode 1. 0x18 [12:0] X SCP HBLKLEN HBLK length in HBLK Mode 0 and Mode 1. [20:13] X HBLKREP Number of HBLK repetitions in HBLK Mode 0 and HBLK Mode 1. [21] X HBLKMASK_H1 Masking polarity for H1/H3/H5/H7 during HBLK. [22] X HBLKMASK_H2 Masking polarity for H2/H4/H6/H8 during HBLK. [23] X HBLKMASK_HL Masking polarity for HL during HBLK. [24] X HBLKMASK_H3P Masking polarity for H3P during 3-phase mode during HBLK. 0x19 [12:0] X SCP HBLKTOGO1 First HBLK toggle position for odd lines, or RA0H1REPA/B/C in HBLK Mode 1. [25:13] X HBLKTOGO2 Second HBLK toggle position for odd lines, or RA1H1REPA/B/C.

Rev. B | Page 110 of 112 Address Data Bits Default Value Update Type Name Description 0x1A [12:0] X SCP HBLKTOGO3 Third HBLK toggle position for odd lines, or RA2H1REPA/B/C. [25:13] X HBLKTOGO4 Fourth HBLK toggle position for odd lines, or RA3H1REPA/B/C. 0x1B [12:0] X SCP HBLKTOGO5 Fifth HBLK toggle position for odd lines, or RA4H1REPA/B/C. [25:13] X HBLKTOGO6 Sixth HBLK toggle position for odd lines, or RA5H1REPA/B/C. 0x1C [12:0] X SCP HBLKTOGE1 First HBLK toggle position for even lines, or RA0H2REPA/B/C. [25:13] X HBLKTOGE2 Second HBLK toggle position for even lines, or RA1H2REPA/B/C. 0x1D [12:0] X SCP HBLKTOGE3 Third HBLK toggle position for even lines, or RA2H2REPA/B/C. [25:13] X HBLKTOGE4 Fourth HBLK toggle position for even lines, or RA3H2REPA/B/C. 0x1E [12:0] X SCP HBLKTOGE5 Fifth HBLK toggle position for even lines, or RA4H2REPA/B/C. [25:13] X HBLKTOGE6 Sixth HBLK toggle position for even lines, or RA5H2REPA/B/C. 0x1F [12:0] X SCP HBLKSTARTA HBLK repeat area Start Position A for HBLK Mode 1. Set to 8191 if not used. [25:13] X HBLKSTARTB HBLK repeat area Start Position B for HBLK Mode 1. Set to 8191 if not used. 0x20 [12:0] X SCP HBLKSTARTC HBLK repeat area Start Position C for HBLK Mode 1. Set to 8191 if not used. [16:13] VMASK_EVEN 1 = enable FREEZE/RESUME for each VPAT group (A, B, C, D); even lines. [20:17] VMASK_ODD 1 = enable FREEZE/RESUME for each VPAT group (A, B, C, D); odd lines. 0x21 [2:0] X SCP HBLKALT_PAT0 HBLK Mode 1, Repeat Area 0 pattern for odd lines. [6:4] X HBLKALT_PAT1 HBLK Mode 1, Repeat Area 1 pattern for odd lines. [10:8] X HBLKALT_PAT2 HBLK Mode 1, Repeat Area 2 pattern for odd lines. [14:12] X HBLKALT_PAT3 HBLK Mode 1, Repeat Area 3 pattern for odd lines. [18:16] X HBLKALT_PAT4 HBLK Mode 1, Repeat Area 4 pattern for odd lines. [22:20] X HBLKALT_PAT5 HBLK Mode 1, Repeat Area 5 pattern for odd lines. 0x22 [12:0] X SCP CLPOBTOG1 CLPOB Toggle Position 1. [25:13] X CLPOBTOG2 CLPOB Toggle Position 2. 0x23 [12:0] X SCP PBLKTOG1 PBLK Toggle Position 1. [25:13] X PBLKTOG2 PBLK Toggle Position 2. 0x24 [11:0] X SCP HBLK2OFF_A_E HCLK Offset A for even lines. Used during HBLK Mode 1. [23:12] X HBLK2OFF_A_O HCLK Offset A for odd lines. Used during HBLK Mode 1. 0x25 [11:0] X SCP HBLK2OFF_B_E HCLK Offset B for even lines. Used during HBLK Mode 1. [23:12] X HBLK2OFF_B_O HCLK Offset B for odd lines. Used during HBLK Mode 1. 0x26 [11:0] X SCP HBLK2OFF_C_E HCLK Offset C for even lines. Used during HBLK Mode 1. [23:12] X HBLK2OFF_C_O HCLK Offset C for odd lines. Used during HBLK Mode 1. 0x27 [12:0] X SCP HBLKCNT_START Start position for HBLK counter. For HBLK operation, HBLKCNT_START should be set equal to the value of HBLKSTART; if HBLK interval is not needed, set to 8191. [13] X HBLKEND[13] MSB for HBLKEND register (V-Sequence Register 0x17, Bits[25:13]).

Table 64. Field Registers (Default Values Are Undefined) 0x00 [4:0] X VD SEQ0 Selected V-sequence for first region in the field. [9:5] X SEQ1 Selected V-sequence for second region in the field. [14:10] X SEQ2 Selected V-sequence for third region in the field. [19:15] X SEQ3 Selected V-sequence for fourth region in the field. [24:20] X SEQ4 Selected V-sequence for fifth region in the field. 0x01 [4:0] X VD SEQ5 Selected V-sequence for sixth region in the field. [9:5] X SEQ6 Selected V-sequence for seventh region in the field. [14:10] X SEQ7 Selected V-sequence for eighth region in the field. [19:15] X SEQ8 Selected V-sequence for ninth region in the field. [21:20] MULT_SWEEP0 Enables multiplier mode and/or sweep mode for Region 0. 0 = multiplier off/sweep off. 1 = multiplier off/sweep on. 2 = multiplier on/sweep off. [23:22] MULT_SWEEP1 Enables multiplier mode and/or sweep mode for Region 1. [25:24] MULT_SWEEP2 Enables multiplier mode and/or sweep mode for Region 2. 0x02 [12:0] X VD HDLASTLEN HD last line length. Line length of last line in the field. [14:13] X MULT_SWEEP3 Enables multiplier mode and/or sweep mode for Region 3. [16:15] X MULT_SWEEP4 Enables multiplier mode and/or sweep mode for Region 4. [18:17] X MULT_SWEEP5 Enables multiplier mode and/or sweep mode for Region 5. [20:19] X MULT_SWEEP6 Enables multiplier mode and/or sweep mode for Region 6. [22:21] X MULT_SWEEP7 Enables multiplier mode and/or sweep mode for Region 7. [24:23] X MULT_SWEEP8 Enables multiplier mode and/or sweep mode for Region 8. [25] X HDLASTLEN_13 HD last line length bit [13] when 14-bit H-counter is enabled. 0x03 [12:0] X VD SCP0 V-Sequence Change Position 0. [25:13] X SCP1 V-Sequence Change Position 1. 0x04 [12:0] X VD SCP2 V-Sequence Change Position 2. [25:13] X SCP3 V-Sequence Change Position 3. 0x05 [12:0] X VD SCP4 V-Sequence Change Position 4. [25:13] X SCP5 V-Sequence Change Position 5. 0x06 [12:0] X VD SCP6 V-Sequence Change Position 6. [25:13] X SCP7 V-Sequence Change Position 7. 0x07 [12:0] X VD SCP8 V-Sequence Change Position 8. [25:13] X VDLEN VD field length (number of lines in the field). 0x08 [12:0] X VD SGACTLINE1 SG Active Line 1. [25:13] X SGACTLINE2 SG Active Line 2. Set to SG Active Line 1 or maximum if not used. 0x09 [23:0] X VD SGMASK Masking of VSG outputs during SG active line. 0x0A [12:0] X VD CLPMASKSTART1 CLPOB Mask Region 1 start position. Set to 8191 to disable. [25:13] X CLPMASKEND1 CLPOB Mask Region 1 end position. Set to 0 to disable. 0x0B [12:0] X VD CLPMASKSTART2 CLPOB Mask Region 2 start position. Set to 8191 to disable. [25:13] X CLPMASKEND2 CLPOB Mask Region 2 end position. Set to 0 to disable. 0x0C [12:0] X VD CLPMASKSTART3 CLPOB Mask Region 3 start position. Set to 8191 to disable. [25:13] X CLPMASKEND3 CLPOB Mask Region 3 end position. Set to 0 to disable. 0x0D [12:0] X VD PBLKMASKSTART1 PBLK Mask Region 1 start position. Set to 8191 to disable. [25:13] X PBLKMASKEND1 PBLK Mask Region 1 end position. Set to 0 to disable. 0x0E [12:0] X VD PBLKMASKSTART2 PBLK Mask Region 2 start position. Set to 8191 to disable. [25:13] X PBLKMASKEND2 PBLK Mask Region 2 end position. Set to 0 to disable. 0x0F [12:0] X VD PBLKMASKSTART3 PBLK Mask Region 3 start position. Set to 8191 to disable. [25:13] X PBLKMASKEND3 PBLK Mask Region 3 end position. Set to 0 to disable.

WITH THE EXCEPTION TO PACKAGE HEIGHT.

0.25 MIN

0.91 MIN

Figure 118. 105-Ball Chip Scale Package Ball Grid Array [CSP_BGA] registered trademarks are the prop erty of their respective owners.