AD9914BCPZ-CSL

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3.5 GPSP Direct Digital Synthesizer with 12-Bit DAC

Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►3.5 GSPS internal clock speed ►Integrated 12-bit DAC ►Frequency tuning resolution to 190 pHz ►16-bit phase tuning resolution ►12-bit amplitude scaling ►Programmable modulus ►Automatic linear and nonlinear frequency sweeping capability ►32-bit parallel datapath interface ►8 frequency/phase offset profiles ►Phase noise: −128 dBc/Hz (1 kHz offset at 1396 MHz) ►Wideband SFDR < −50 dBc ►Serial or parallel input/output control ►1.8 V/3.3 V power supplies ►Software and hardware controlled power-down ►88-lead LFCSP package ►PLL REF CLK multiplier ►Phase modulation capability ►Amplitude modulation capability COMMERCIAL SPACE FEATURES ►Supports aerospace applications ►Wafer diffusion lot traceability ►Radiation lot acceptance test (RLAT) ►Total ionizing dose (TID) ►Radiation benchmark ►Single event latch-up (SEL)

APPLICATIONS

►Low Earth orbit (LEO) space payloads ►Agile LO frequency synthesis ►Programmable clock generators ►FM chirp source for radar and scanning systems ►Test and measurement equipment ►Acousto-optic device drivers ►Polar modulators ►Fast frequency hopping FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The AD9914S-CSL is a direct digital synthesizer (DDS) featuring a 12‑ bit digital-to-analog converter (DAC). The AD9914S-CSL uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a fre- quency-agile analog output sinusoidal waveform at up to 1.4 GHz. The AD9914S-CSL enables fast frequency hopping and fine tuning resolution (64‑ bit capable using programmable modulus mode). The AD9914S-CSL also offers fast phase and amplitude hopping capability. The frequency tuning and control words are loaded into the AD9914S-CSL via a serial or parallel input/output port. The AD9914S-CSL also supports a user defined linear sweep mode of operation for generating linear swept waveforms of frequency, phase, or amplitude. A high speed, 32-bit parallel data input port is included, enabling high data rates for polar modulation schemes and fast reprogramming of the phase, frequency, and amplitude tuning words. The AD9914S-CSL is specified to operate over the extended in- dustrial temperature range (see the Absolute Maximum Ratings section). Additional application and technical information can be found in the Commercial Space Products Program brochure and the AD9914 data sheet. Analog Devices is in the process of updating documentation to provide terminology and language that is culturally appropriate. This is a process with a wide scope and will be phased in as quickly as possible. Thank you for your patience.

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REVISION HISTORY

5/2022—Revision 0: Initial Version

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analog.com Rev. 0 | 4 of 17 DC SPECIFICATIONS DAC_RSET pin (RSET) = 3.3 kΩ, output current (IOUT) = 20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VOLTAGE DVDD_I/O 3.135 3.30 3.465 V Pin 16, Pin 83 DVDD 1.71 1.80 1.89 V Pin 6, Pin 23, Pin 73 AVDD (3.3 V) 3.135 3.30 3.465 V Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52, Pin 53, Pin 60 AVDD (1.8 V) 1.71 1.80 1.89 V Pin 32, Pin 56, Pin 57 SUPPLY CURRENT See also the total power dissipation specifications DVDD_I/O Current (IDVDD_I/O) 20 mA Pin 16, Pin 83 DVDD Current (IDVDD) 433 mA Pin 6, Pin 23, Pin 73 AVDD (3.3V) Current (IAVDD(3.3V)) 640 mA Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52, Pin 53, Pin 60 AVDD (1.8V) Current (IAVDD(1.8V)) 178 mA Pin 32, Pin 56, Pin 57 TOTAL POWER DISSIPATION Base DDS Power, Phase-Locked Loop (PLL) Disabled 2392 3091 mW 3.5 GHz, single-tone mode, modules disabled, linear sweep disabled, amplitude scaler disabled Base DDS Power, PLL Enabled 2237 2627 mW 2.5 GHz, single-tone mode, modules disabled, linear sweep disabled, amplitude scaler disabled Linear Sweep Additional Power 28 mW Modulus Additional Power 20 mW Amplitude Scaler Additional Power 138 mW Manual or automatic Full Power-Down Mode 400 616 mW Using either the power-down and enable register or the EXT_PWR_DWN pin CMOS LOGIC INPUTS Input High Voltage (VIH) 2.0 DVDD_I/O V Input Low Voltage (VIL) 0.8 V Input Current (IINH, IINL) ±60 ±200 µA At VIN = 0 V and VIN = DVDD_I/O Maximum Input Capacitance (CIN) 3 pF CMOS LOGIC OUTPUTS Output High Voltage (VOH) 2.7 DVDD_I/O V IOH = 1 mA Output Low Voltage (VOL) 0.4 V IOL = 1 mA REF CLK INPUT CHARACTERISTICS REF CLK inputs must always be ac-coupled (both single‑ ended and differential) REF CLK Multiplier Bypassed Input Capacitance 1 pF Single-ended, each pin Input Resistance 1.4 kΩ Differential Internally Generated DC Bias Voltage 2 V Differential Input Voltage 0.8 1.5 V p-p REF CLK Multiplier Enabled Input Capacitance 1 pF Single-ended, each pin Input Resistance 1.4 kΩ Differential Internally Generated DC Bias Voltage 2 V Differential Input Voltage 0.8 1.5 V p-p

analog.com Rev. 0 | 5 of 17 AC SPECIFICATIONS external reference clock frequency = 3.5 GHz with REF CLK multiplier bypassed, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments REF CLK INPUT Input frequency range REF CLK Multiplier Bypassed Input Frequency Range 500 3500 MHz Maximum output frequency (fOUT) is 0.4 × SYSCLK frequency (fSYSCLK) Duty Cycle 45 50 55 % Minimum Differential Input Level 632 mV p-p Equivalent to 316 mV swing on each leg System Clock (SYSCLK) PLL Enabled VCO Frequency Range 2400 2500 MHz VCO Gain (KV) 60 MHz/V Maximum PFD Rate 125 MHz CLOCK DRIVERS SYNC_CLK Output Driver Frequency Range 146 MHz Duty Cycle 33 % See Figure 22 Rise Time and Fall Time (20% to 80%) 650 ps SYNC_OUT Output Driver 10 pF load Frequency Range 9.1 MHz Duty Cycle 33 66 % CFR2 register, Bit 9 = 1 Rise Time (20% to 80%) 1350 ps 10 pF load Fall Time (20% to 80%) 1670 ps 10 pF load DAC OUTPUT CHARACTERISTICS Output Frequency Range (First Nyquist Zone)0 1750 MHz Output Resistance 50 Ω Single-ended (each pin internally terminated to AVDD (3.3 V)) Output Capacitance 1 pF Full-Scale Output Current 20.48 mA Range depends on DAC RSET resistor Gain Error −10 +10 % FS Output Offset 0.6 μA Voltage Compliance Range AVDD − 0.50 AVDD + 0.50V Wideband Spurious-Free Dynamic Range (SFDR) See the Typical Performance Characteristics section

101.1 MHz Output −66 dBc 0 MHz to 1750 MHz

427.5 MHz Output −65 dBc 0 MHz to 1750 MHz

696.5 MHz Output −57 dBc 0 MHz to 1750 MHz

1396.5 MHz Output −52 dBc 0 MHz to 1750 MHz

Narrow-Band SFDR See the Typical Performance Characteristics section

100.5 MHz Output −95 dBc ±500 kHz

427.5 MHz Output −95 dBc ±500 kHz

696.5 MHz Output −95 dBc ±500 kHz

1396.5 MHz Output −92 dBc ±500 kHz

DIGITAL TIMING SPECIFICATIONS Time Required to Enter Power-Down 45 ns Power-down mode loses DAC/PLL calibration settings Time Required to Leave Power-Down 250 ns Must recalibrate DAC/PLL Minimum Master Reset Time 24 SYSCLK cycles

analog.com Rev. 0 | 6 of 17 Table 2. Parameter Min Typ Max Unit Test Conditions/Comments Maximum DAC Calibration Time (tCAL) 135 µs See the DAC calibration output information in the AD9914 data sheet for this formula Maximum PLL Calibration Time (tREF_CLK) 16 ms PFD rate = 25 MHz 8 ms PFD rate = 50 MHz Maximum Profile Toggle Rate 2 SYNC_CLK period PARALLEL PORT TIMING Write Timing Address Setup Time to WR Active 1 ns Address Hold Time to Inactive 0 ns Data Setup Time to WR Inactive 3.8 ns Data Hold Time to WR Inactive 0 ns WR Minimum Low Time 2.1 ns WR Minimum High Time 3.8 ns Minimum WR Time 10.5 ns Read Timing Address to Data Valid 92 ns Address Hold to RD Inactive 0 ns RD Active to Data Valid 69 ns RD Inactive to Data Tristate 50 ns RD Minimum Low Time 69 ns RD Minimum High Time 50 ns SERIAL PORT TIMING SCLK Clock Rate (1/tCLK ) 80 MHz SCLK duty cycle = 50%, maximum SCLK rate applies only to write cycles, read cycles are constrained to < 3 MHz SCLK Pulse Width High, tHIGH 1.5 ns SCLK Pulse Width Low, tLOW 5.1 ns SDIO to SCLK Setup Time, tDS 4.9 ns SDIO to SCLK Hold Time, tDH 0 ns SCLK Falling Edge to Valid Data on SDIO/ SDO, tDV 78 ns CS to SCLK Setup Time, tS 4 ns CS to SCLK Hold Time, tH 0 ns CS Minimum Pulse Width High, tPWH 4 ns DATA PORT TIMING D31 to D0 Setup Time to SYNC_CLK2 ns D31 to D0 Hold Time to SYNC_CLK 0 ns F3 to F0 Setup Time to SYNC_CLK 2 ns F3 to F0 Hold Time to SYNC_CLK 0 ns I/O_UPDATE Pin Setup Time to SYNC_CLK2 ns I/O_UPDATE Pin Hold Time to SYNC_CLK 0 ns Profile Pin Setup Time to SYNC_CLK2 ns Profile Pin Hold Time to SYNC_CLK 0 ns DR_CTL/DR_HOLD Setup Time to SYNC_CLK2 ns DR_CTL/DR_HOLD Hold Time to SYNC_CLK 0 ns DATA LATENCY (PIPELINE DELAY) 1 SYSCLK cycle = 1 period of the system clock (1/fS) Single Tone Mode or Profile Mode (Matched Latency Disabled) Frequency 318 SYSCLK cycles OSK disabled

342 SYSCLK cycles OSK enabled

analog.com Rev. 0 | 7 of 17 Table 2. Parameter Min Typ Max Unit Test Conditions/Comments Phase 294 SYSCLK cycles OSK disabled

318 SYSCLK cycles OSK enabled

Amplitude 102 SYSCLK cycles OSK enabled Single Tone Mode or Profile Mode (Matched Latency Enabled) Frequency 318 SYSCLK cycles OSK disabled Phase 318 SYSCLK cycles OSK disabled Amplitude 342 SYSCLK cycles OSK enabled Modulation Mode with 32-Bit Parallel Port (Matched Latency Disabled) Frequency 318 SYSCLK cycles OSK disabled Phase 294 SYSCLK cycles OSK disabled Amplitude 102 SYSCLK cycles OSK enabled Modulation Mode with 32-Bit Parallel Port (Matched Latency Enabled) Frequency 318 SYSCLK cycles OSK disabled Phase 318 SYSCLK cycles OSK disabled Amplitude 342 SYSCLK cycles OSK enabled Sweep Mode (Match Latency Disabled) Frequency 342 SYSCLK cycles OSK disabled

366 SYSCLK cycles OSK enabled

Phase 318 SYSCLK cycles OSK disabled Amplitude 126 SYSCLK cycles OSK enabled Sweep Mode (Match Latency Enabled) Frequency 342 SYSCLK cycles OSK disabled Phase 342 SYSCLK cycles OSK disabled Amplitude 366 SYSCLK cycles OSK enabled

RADIATION TEST AND LIMIT SPECIFICATIONS analog.com Rev. 0 | 8 of 17 mA, and external reference clock frequency = 3.5 GHz with REF CLK multiplier bypassed, unless otherwise noted. Total ionizing dose (TID) testing characterized to 50 krads (30 krads + 50% overstress) with biased annealing at 100°C for 168 hours. Once characterized, TID testing is performed to 30 krads only. Table 3. Parameter Min Typ Max Unit DC SPECIFICATIONS DVDD_I/O 3.135 3.3 3.465 V Full Power-Down Mode 400 606 mW Internally Generated DC Bias Voltage 2 V Maximum Current 0.93 1 A Maximum Power 2.5 2.75 W DIGITAL INPUT AND OUTPUT LEAKAGE CURRENT Low 20 35 50 μA High 50 120 μA AC SPECIFICATIONS Offset Error −15 +15 mV Gain Error −10 +10 %FS

ing conditions for extended periods may affect product reliability. 1 Results are from simulations. Printed circuit board (PCB) is JEDEC multilayer. been used as screening levels for rejection of spacecraft materials. Table 6. Outgas Testing damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.

Figure 3. Pin Configuration Table 7. Pin Function Descriptions configuration is set by the state of the four function pins (F0 to F3). FSK, PSK, or ASK data or as an address line for programming the internal registers. FSK, PSK, or ASK data or as an address line for programming the internal registers. FSK, PSK, or ASK data or as an address line for programming the internal registers. FSK, PSK, or ASK data or as an address line for programming the internal registers. FSK, PSK, or ASK data or as an address line for programming the internal registers. for programming the internal registers. for programming the internal registers. FSK, PSK, or ASK data or as an address line for programming the internal registers.

invoked via F0 to F3, this pin resets the serial port. to F3, this pin is used for readback mode for serial operation. this pin to change the values of the internal registers. either 8-bit data or16-bit data. 6, 23, 73 DVDD (1.8V) I Digital Core Supplies (1.8 V). 7, 17, 24, 74, 84 DGND I Digital Ground. 16, 83 DVDD_I/O (3.3V) I Digital Input and Output Supplies (3.3 V). 32, 56, 57 AVDD (1.8V) I Analog Core Supplies (1.8 V). AVDD (3.3V) I Analog DAC Supplies (3.3 V). the corresponding registers. State changes must be set up on the SYNC_CLK pin (Pin 82). the function pins determine how the 32-bit parallel data-word is partitioned for FSK, PSK, or ASK modulation mode. capacitor between this pin and ground can improve noise performance at the DAC output. 54 REF_CLK I Complementary Reference Clock Input. Analog input. 55 REF_CLK I Reference Clock Input. Analog input. 58 LOOP_FILTER O External PLL Loop Filter Node. 59 REF O Local PLL Reference Supply. Typically at 2.05 V. 61 SYNC_OUT O Digital Synchronization Output. This pin synchronizes multiple chips. 62 SYNC_IN I Digital Synchronization Input. This pin synchronizes multiple chips. 63 DRCTL I Ramp Control. Digital input (active high). This pin controls the sweep direction (up/down). 64 DRHOLD I Ramp Hold. Digital input (active high). Pauses the sweep when active. programmed upper or lower limit. sweeps the amplitude up to the amplitude scale factor. parallel data port (D0 to D31), must be set up on the rising edge of this signal.

85 MASTER_RESET I Master Reset. Digital input (active high). This pin clears all memory elements and sets registers to default values. buffers to the corresponding internal registers. EPAD Exposed Pad. The EPAD must be soldered to ground.

Figure 16. Absolute Phase Noise Curves of Normalized REF CLK Source to Figure 17. Residual Phase Noise Curves Figure 18. Power Supply Current vs. SYSCLK Figure 19. Absolute Phase Noise Curves of DDS Output Using Internal PLL at

2.5 GHz Operation

Figure 20. Residual Phase Noise vs. Absolute Phase Noise Measurement Figure 21. Residual Phase Noise vs. Normalized Absolute REF CLK Source

registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 27. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]