AD9913

AD9913 (Rev. E)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 32

Technical content

Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer Data Sheet AD9913 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2007–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

50 mW at up to 250 MSPS internal clock speed

100 MHz analog output

0.058 Hz or better frequency resolution

0.022° phase tuning resolution Programmable modulus in frequency equation Phase noise ≤ –135 dBc per Hz @ 1 kHz offset (DAC output) (<115 dBc per Hz when using on-board PLL multiplier) Excellent dynamic performance >80 dB SFDR @ 100 MHz (±100 kHz offset) A OUT Automatic linear frequency sweeping capability 8 frequency or phase offset profiles

1.8 V power supply

Software and hardware controlled power-down Parallel and serial programming options 32-lead LFCSP package Optional PLL REF_CLK multiplier Internal oscillator (can be driven by a single crystal) Phase modulation capability

APPLICATIONS

Portable and handheld equipment Agile LO frequency synthesis Programmable clock generator FM chirp source for radar and scanning systems GENERAL DESCRIPTION The AD9913 is a complete direct digital synthesizer (DDS) designed to meet the stringent power consumption limits of portable, handheld, and battery-powered equipment. The AD9913 features a 10-bit digital-to-analog converter (DAC) operating up to 250 MSPS. The AD9913 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a complete, digitally-program- mable, high frequency synthesizer capable of generating a frequency agile analog output sinusoidal waveform at up to 100 MHz. The AD9913 provides fast frequency hopping and fine tuning resolution. The AD9913 also offers fine resolution phase offset control. Control words are loaded into the AD9913 through the serial or parallel I/O port. The AD9913 also supports a user- defined linear sweep mode of operation for generating highly linearized swept waveforms of frequency. To support various methods of generating a system clock, the AD9913 includes an oscillator, allowing a simple crystal to be used as the frequency reference, as well as a high speed clock multiplier to convert the reference clock frequency up to the full system clock rate. For power saving considerations, many of the individual blocks of the AD9913 can be powered down when not in use. The AD9913 operates over the extended industrial temperature range of −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM REF_CLK INPUT CIRCUITRY TIMING AND CONTROL LOGIC DDS 10-BIT DAC USER INTERFACE AD9913 07002-001 Figure 1.

Rev. E | Page 2 of 32 TABLE OF CONTENTS

REVISION HISTORY

11/2020—Rev. D to Rev. E 3/2019—Rev. C to Rev. D 11/2017—Rev. B to Rev. C 8/2016—Rev. A to Rev. B 6/2010—Rev. 0 to Rev. A Added Register Update (I/O Update) section and Figure 35 .. 25 Changes to Register Bit Descriptions Section and Bit 7 10/2007—Revision 0: Initial Version

Rev. E | Page 3 of 32 SPECIFICATIONS ELECTRICAL SPECIFICATIONS AVDD (1.8 V), DVDD (1.8 V), and DVDD_I/O = 1.8 V ± 5%, T = 25°C, RSET = 4.64 kΩ, DAC full-scale current = 2 mA, external reference clock frequency = 250 MHz with REF_CLK multiplier disabled, unless otherwise noted. Table 1. Parameter Conditions/Comments Min Typ Max Unit REF_CLK INPUT CHARACTERISTICS Frequency Range REF_CLK Multiplier Disabled 250 MHz Enabled 250 MHz REF_CLK Input Divider Frequency Full temperature range 83 MHz VCO Oscillation Frequency VCO1 16 250 MHz VCO2 100 250 MHz PLL Lock Time 25 MHz reference clock, 10× PLL 60 μs External Crystal Mode 25 MHz CMOS Mode VIH 0.9 V VIL 0.65 V Input Capacitance 3 pF Input Impedance (Differential) 2.7 kΩ Input Impedance (Single-Ended) 1.35 kΩ Duty Cycle 45 55 % REF_CLK Input Level 355 1000 mV p-p DAC OUTPUT CHARACTERISTICS Full-Scale Output Current 4.6 mA Gain Error −14 −6 %FS Output Offset +0.1 μA Differential Nonlinearity −0.4 +0.4 LSB Integral Nonlinearity −0.5 +0.5 LSB AC Voltage Compliance Range ±400 mV SPURIOUS-FREE DYNAMIC RANGE Refer to Figure 6 SERIAL PORT TIMING CHARACTERISTICS SCLK Frequency 32 MHz SCLK Pulse Width Low 17.5 ns High 3.5 ns SCLK Rise/Fall Time 2 ns Data Setup Time to SCLK 5.5 ns Data Hold Time to SCLK 0 ns Data Valid Time in Read Mode 22 ns PARALLEL PORT TIMING CHARACTERISTICS PCLK Frequency 33 MHz PCLK Pulse Width Low 10 ns High 20 ns PCLK Rise/Fall Time 2 ns Address/Data Setup Time to PCLK 3.0 ns Address/Data Hold Time to PCLK 0.3 ns Data Valid Time in Read Mode 8 ns IO_UPDATE/PROFILE(2:0) TIMING Setup Time to SYNC_CLK 0.5 ns Hold Time to SYNC_CLK 1 SYNC_CLK cycles

Rev. E | Page 4 of 32 Parameter Conditions/Comments Min Typ Max Unit MISCELLANEOUS TIMING CHARACTERISTICS Wake-Up Time1 Fast Recovery Mode 1 SYSCLK cycles 2 Full Sleep Mode 60 μs Reset Pulse Width High 5 SYSCLK cycles DATA LATENCY (PIPELINE DELAY) Frequency, Phase-to-DAC Output Matched latency enabled 11 SYSCLK cycles Frequency-to-DAC Output Matched latency disabled 11 SYSCLK cycles Phase-to-DAC Output Matched latency disabled 10 SYSCLK cycles Delta Tuning Word-to-DAC Output (Linear Sweep) 14 SYSCLK cycles CMOS LOGIC INPUTS Logic 1 Voltage 1.2 V Logic 0 Voltage 0.4 V Logic 1 Current −700 +700 nA Logic 0 Current −700 +700 nA Input Capacitance 3 pF CMOS LOGIC OUTPUTS 1 mA load Logic 1 Voltage 1.5 V Logic 0 Voltage 0.125 V POWER SUPPLY CURRENT DVDD (1.8 V) Pin Current Consumption 46.5 mA DAC_CLK_AVDD (1.8 V) 4.7 mA DAC_AVDD (1.8 V) Pin Current Consumption 6.2 mA PLL_AVDD (1.8 V) 1.8 mA CLK_AVDD (1.8 V) Pin Current Consumption 4.3 mA POWER CONSUMPTION Single Tone Mode PLL enabled, CMOS input 50 66.5 mW PLL disabled, differential input 57 70.5 mW PLL enabled, XTAL input 52 68.5 mW Modulus Mode PLL disabled 94.6 mW Linear Sweep Mode PLL disabled 98.4 mW Power-Down Full 15 mW Safe PLL enabled 44.8 mW PLL Modes VCO 1 Differential Input Mode 11 mW CMOS Input Mode 7.5 mW Crystal Mode 5.4 mW VCO 2 Differential Input Mode 15 mW CMOS Input Mode 11.5 mW Crystal Mode 9.4 mW 1 Refer to the Power-Down Features section. 2 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency, the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the SYSCLK frequency is the same as the external reference clock frequency.

operational section of this specification is not implied. extended periods may affect product reliability. AVOID OVERDRIVING DIGITAL INPUTS. Figure 2. Equivalent Input and Output Circuits

1. EXPOSED PAD SHOULD BE SOLDERED TO GROUND.

Figure 3. Pin Configuration Table 3. Pin Function Descriptions Data Line (D5) to program registers. Address Line (ADR4), and Data Line (D4) to program registers. Address Line (ADR3), and Data Line (D3) to program registers. 4 DVDD I Digital Power Supply (1.8 V). 6 ADR2/D2 I/O Parallel Port Address Line 2 and Data Line 2. 7 ADR1/D1 I/O Parallel Port Addr ess Line 1and Data Line 1. 8 ADR0/D0 I/O Parallel Port Address Line 0 and Data Line 0. edge of this signal to maintain constant pipe line delay through the device. 10 SER/PAR I Serial Port and Parallel Port Selection. Logic low = serial mode; logic high = parallel mode. AVDD I Analog Power Supply (1.8 V). 13 REF_CLK I Reference Clock Input. See the REF_CLK Overview section for more details. 14 REF_CLK I Complementary Reference Clock Input. See the REF_CLK Overview section for more details. 19 IOUT O Open Source DAC Complementary Output Source. Current mode. Connect through 50 Ω to AGND. 20 IOUT O Open Source DAC Output Source. Current mode. Connect through 50 Ω to AGND.

Rev. E | Page 7 of 32 Pin No. Mnemonic I/O Description 26 PWR_DWN_CTL I External Power-Down, Digital Input (Active High). A high level on this pin initiates the currently programmed power-down mode. See the Power-Down Features section for further details. If unused, tie to ground. 27 IO_UPDATE I I/O Update; Digital Input. A high on this pin indicates a transfer of the contents of the I/O buffers to the corresponding internal registers. 28 CS I Chip Select for Serial and Parallel Port. Digital input (active low). Bringing this pin low enables the AD9913 to detect serial (SCLK) or parallel (PCLK) clock rising/falling edges. Bringing this pin high causes the AD9913 to ignore input on the data pins. 29 SDIO(WR/RD) I/O Bidirectional Data Line for Seri al Port Operation and Write/Read Enable for Parallel Port Operation. 30 SCLK/PCLK I Input Clock for Serial and Parallel Port. 31 ADR7/D7 I/O Parallel Port Address Line 7 and Data Line 7. 32 ADR6/D6 I/O Parallel Port Address Line 6 and Data Line 6. 33 Exposed Paddle The EPAD shou ld be soldered to ground.

• Single tone
• Direct switch
• Programmable modulus
• Linear sweep The modes relate to the data source used to supply the DDS with its signal control parameters: frequency, phase, or ampli- tude. The partitioning of the data into different combinations of frequency, phase, and amplitude is handled automatically based on the mode and/or specific control bits. SINGLE TONE MODE Single tone mode is the default operational mode and is active when both the direct switch mode bit and the auxiliary accumulator enable bit are not set. This mode outputs a single frequency as programmed by the user in the frequency tuning word (FTW) register. A phase offset value is also available in single tone mode via the POW register. DIRECT SWITCH MODE Direct switch mode enables FSK or PSK modulation. This mode simply selects the frequency or phase value programmed into the profile registers. Frequency or phase is determined by the destination bits in CFR1 [13:12]. Direct switch mode is enabled using the direct switch mode active bit in register CFR1 [16]. Two approaches are designed for switching between profile registers. The first is programming the internal profile control bits, CFR1 [22:20], to the desired value and issuing an IO_UPDATE. The second approach, with higher data throughput, is achieved by changing the profile control pins [2:0]. Control bit CFR1 [27] is for selection between the two approaches. The default state uses the profile pins. To perform 8-tone FSK or PSK, program the FTW word or phase offset word in each profile. The internal profile control bits or the profile pins are used for the FSK or PSK data. Table 4 shows the relationship between the profile selection pin or bit approach.

Table 4. Profile Selection

000 Profile 0

001 Profile 1

010 Profile 2

011 Profile 3

100 Profile 4

101 Profile 5

110 Profile 6

111 Profile 7

power of 2 in the denominator. values to the appropriate register.  Register 0x06 [63:32] holds the B value.  Register 0x06 [31:0] holds the X value.  Register 0x07 [31:0] holds the A value. loaded into the linear sweep parameter register (Register 0x06). frequency or phase. Table 5 depicts the direction of the sweep.

Figure 23. Display of Ramp-Up and Ramp-Down Capability Using the External Profile Pins

Table 6. Clock Input Mode Configuration

000 Differential Input, PLL Enabled

001 Differential Input, PLL Disabled (Default)

100 CMOS Input, PLL Enabled

101 CMOS Input PLL Disabled

Figure 26. Internal Clock Path Functional Block Diagram the recommended circuit configuration. Figure 27. Crystal Connection Diagram source, either single-ended or differential signals can be used. pins to avoid disturbing the internal dc bias voltage of ~1.35 V. See Figure 28 for more details. 28 assume a signal source with a 50 Ω output impedance. Figure 28. Direct Connection Diagram CMOS mode be tied to ground through a 10 kΩ resistor. Figure 29. CMOS-Driven Diagram cation factor. The PLL is also equipped with a PLL_LOCK bit.

Rev. E | Page 19 of 32 is to reset digital logic in the PLL circuit with an active low signal. The function of CFR2 [5] is to power up or power down the PLL. CFR2 [4] is the PLL LO range bit. When operating the AD9913 with the PLL enabled, CFR2 [4] adjusts PLL loop filter components to allow low frequency reference clock inputs. CFR2 [3] enables a divide-by-two circuit at the input of the PLL phase detector. If this bit is enabled the reference clock signal is divided by 2 prior to multiplication in the PLL. Refer to the electrical specifications for the maximum reference clock input frequency when utilizing the PLL with the divide by 2 circuit enabled. If the divide by 2 circuit is disabled and the PLL is enabled, then the maximum reference clock input frequency is one-half the maximum rate indicated in the electrical specifications table for the maximum input divider frequency. The AD9913 PLL uses one of two VCOs for producing the system clock signal. CFR2 Bit 2 is a select bit that enables an alternative VCO in the PLL. The basic operation of the PLL is not affected by the state of this bit. The purpose of offering two VCOs is to provide performance options. The two VCOs have approximately the same gain characteristics, but differ in other aspects. The overall spurious performance, phase noise, and power consumption may change based on the setting of CFR2 Bit 2. It is important to consider that for either VCO, the minimum oscillation frequency must be satisfied, and that minimum oscillation frequency is significantly different between the two oscillators. CFR2 [15:9], along with CFR2 [3], determine the multiplication of the PLL. CFR2 [15] enables a divider at the output of the PLL. The bits CFR [14:9] control the feedback divider. The feedback divider is composed of two stages: ÷ N (1:31) selected by CFR2 [13:9]; 1 or 2 selected by CFR2 [14]. Note that the same system clock frequency can be obtained with different combinations of CFR2 [15:9] and CFR2 [3]. One combination may work better in a given application either to run at lower power or to satisfy the VCOs minimum oscillation frequency. Note that the AD9913 maximum system clock frequency is 250 MHz. If the user intends to use high values for the PLL feedback divider ratio, then care should be taken that the system clock frequency does not exceed 250 MHz. PLL LOCK INDICATION CFR2 [0] is a read-only bit that displays the status of the PLL lock signal. When the AD9913 is programmed to use the PLL, there is some amount of time required for the loop to lock. While the loop is not locked, the chip system clock operates at the reference clock frequency presented to the part at the pins. Once the PLL lock signal goes high, the system clock frequency switches asynchronously to operate at the PLL output frequency. To maintain a system clock frequency with or without a locked loop if the PLL lock signal transistions low, the chip reverts to the reference clock signal while the loop attempts to acquire lock once again. Table 7 describes how to configure the PLL multiplication factor using the appropriated register bits.

Table 7. PLL Multiplication Factor Configuration

consistent with other Analog Devices, Inc. DDS products. Table 8. Power-Down Controls

Rev. E | Page 23 of 32 Instruction Byte The instruction byte contains the following information as shown in the instruction byte bit map. Instruction Byte Information Bit Map MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 R/W X X A4 A3 A2 A1 A0 R/W—Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. Logic high indicates read operation. Logic 0 indicates a write operation. X, X—Bit 6 and Bit 5 of the instruction byte are don’t care. A4, A3, A2, A1, A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. Serial Interface Port Pin Description SCLK—Serial Port Clock The serial clock pin is used to synchronize data to and from the AD9913 and to run the internal state machines. CS—Chip Select Active low input that allows more than one device on the same serial communications line. The SDIO pin goes to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until chip select is reactivated low. Chip select can be tied low in systems that maintain control of SCLK. SDIO—Serial Data I/O. Data is always written into and read from the AD9913 on this pin. MSB/LSB Transfers The AD9913 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the CFR1 [23]. The default value is MSB first. The instruction byte must be written in the format indicated by Control Register 0x00 Bit 8. That is, if the AD9913 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. For MSB first operation, the serial port controller generates the most significant byte (of the specified register) address first followed by the next less significant byte addresses until the I/O operation is complete. All data written to (read from) the AD9913 must be in MSB first order. If the LSB mode is active, the serial port controller generates the least significant byte address first followed by the next greater significant byte addresses until the I/O operation is complete. All data written to (read from) the AD9913 must be in LSB first order. Notes on Serial Port Operation The LSB first bit resides in CFR1 [23]. Note that the configuration changes immediately upon writing to the byte containing the LSB first bit. Therefore, care must be taken to compensate for this new configuration for the remainder of the current communication cycle. Reading profile registers requires that the external profile select pins (PS[2:0]) be configured to select the corresponding register. PARALLEL I/O PROGRAMMING Parallel Port Interface Pin Description CS—Chip Select An active low on this pin indicates that a read/write operation is about to be performed. If this pin goes high during an access, the parallel port is reset to its initial condition. R/W—Read/Write A high on Pin 29 combined with CS active low indicates a read operation. A low on this pin indicates a write operation. PCLK—Parallel Port Clock The parallel clock pin is used to synchronize data to and from the AD9913 and to run the internal state machines. ADDR/DATA [7:0] The 8-bit address/data bus. It works in a bidirectional fashion to support both read and write operations. Notes on Parallel Port Operation Each operation works in a 3-PCLK cycle with the first clock cycle for addressing, the second for reading or writing, and the third for re-initialization. In parallel port operation, each byte is programmed individually.

contents from the buffer register into the active register. sent synchronously or asynchronously relative to the SYNC_CLK. otherwise, a time uncertainty of one SYNC_CLK period is present. THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B. Figure 35. I/O Synchronization Timing Diagram

number is the LSB for that register. Table 9. Control Registers

Rev. E | Page 27 of 32 Register Name (Serial Address) [Serial Bit Range]/Parallel Address MSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 0 Default Value Linear Sweep Ramp Rate Register (0x08) [7:0]/0x22 Rising Sweep Ramp Rate Word [7:0] 0x00 [15:8]/0x23 Rising Sweep Ramp Rate Word [15:8] 0x00 [23:16]/0x24 Falling Sweep Ramp Rate Word [7:0] 0x00 [31:24]/0x25 Falling Sweep Ramp Rate Word [15:8] 0x00 Profile 0 (0x09) [7:0]/0x26 Frequency Tuning Word [7:0] 0x00 [15:8]/0x27 Frequency Tuning Word [15:8] 0x00 [23:16]/0x28 Frequency Tuning Word [23:16] 0x00 [31:24]/0x29 Frequency Tuning Word [31:24] 0x00 [39:32]/0x2A Phase Offset Word [7:0] 0x00 [47:40]/0x2B Open [1:0] Phase Offset Word [13:8] 0x00 Profile 1 (0x0A) [7:0]/0x2C Frequency Tuning Word [7:0] 0x00 [15:8]/0x2D Frequency Tuning Word [15:8] 0x00 [23:16]/0x2E Frequency Tuning Word [23:16] 0x00 [31:24]/0x2F Frequency Tuning Word [31:24] 0x00 [39:32]/0x30 Phase Offset Word [7:0] 0x00 [47:40]/0x31 Open [1:0] Phase Offset Word [13:8] 0x00 Profile 2 (0x0B) [7:0]/0x32 Frequency Tuning Word [7:0] 0x00 [15:8]/0x33 Frequency Tuning Word [15:8] 0x00 [23:16]/0x34 Frequency Tuning Word [23:16] 0x00 [31:24]/0x35 Frequency Tuning Word [31:24] 0x00 [39:32]/0x36 Phase Offset Word [7:0] 0x00 [47:40]/0x37 Open [1:0] Phase Offset Word [13:8] 0x00 Profile 3 (0x0C) [7:0]/0x38 Frequency Tuning Word [7:0] 0x00 [15:8]/0x39 Frequency Tuning Word [15:8] 0x00 [23:16]/0x3A Frequency Tuning Word [23:16] 0x00 [31:24]/0x3B Frequency Tuning Word [31:24] 0x00 [39:32]/0x3C Phase Offset Word [7:0] 0x00 [47:40]/0x3D Open [1:0] Phase Offset Word [13:8] 0x00 Profile 4 (0x0D) [7:0]/0x3E Frequency Tuning Word [7:0] 0x00 [15:8]/0x3F Frequency Tuning Word [15:8] 0x00 [23:16]/0x40 Frequency Tuning Word [23:16] 0x00 [31:24]/0x41 Frequency Tuning Word [31:24] 0x00 [39:32]/0x42 Phase Offset Word [7:0] 0x00 [47:40]/0x43 Open [1:0] Phase Offset Word [13:8] 0x00 Profile 5 (0x0E) [7:0]/0x44 Frequency Tuning Word [7:0] 0x00 [15:8]/0x45 Frequency Tuning Word [15:8] 0x00 [23:16]/0x46 Frequency Tuning Word [23:16] 0x00 [31:24]/0x47 Frequency Tuning Word [31:24] 0x00 [39:32]/0x48 Phase Offset Word [7:0] 0x00 [47:40]/0x49 Open [1:0] Phase Offset Word [13:8] 0x00 Profile 6 (0x0F) [7:0]/0x4A Frequency Tuning Word [7:0] 0x00 [15:8]/0x4B Frequency Tuning Word [15:8] 0x00 [23:16]/0x4C Frequency Tuning Word [23:16] 0x00 [31:24]/0x4D Frequency Tuning Word [31:24] 0x00 [39:32]/0x4E Phase Offset Word [7:0] 0x00 [47:40]/0x4F Open Open Phase Offset Word [13:8] 0x00 Profile 7 (0x10) [7:0]/0x50 Frequency Tuning Word [7:0] 0x00 [15:8]/0x51 Frequency Tuning Word [15:8] 0x00 [23:16]/0x52 Frequency Tuning Word [23:16] 0x00 [31:24]/0x53 Frequency Tuning Word [31:24] 0x00 [39:32]/0x54 Phase Offset Word [7:0] 0x00 [47:40]/0x55 Open Open Phase Offset Word [13:8] 0x00 1 These bits are active immediately following the write sequence of the byte in which they reside in. As a result, they do not require an I/O_UPDATE to enable/disable.

unused, yielding a total of 16 available registers. number of bytes necessary for its particular function. binary word and described in aggregate. number of bytes assigned to the register. Address 0x00; 4 bytes are assigned to this register. Table 10. Bit Description for CFR1 31:29 Open Leave these bits at their default values. 28 Modulus Enable This bit is ignored if linear sweep is disabled. 0 = the auxiliary accumulator is used for linear sweep generation. 1 = the auxiliary accumulator is used for programmable modulus. 27 Use Internal Profile 0 = profiles are controlled by profile pins; only valid in serial mode. 1 = profiles are controlled by CFR1 [22:20]. accumulator are not matched. 25:24 Open Leave these bits at the default values. 23 LSB First 0 = MSB first format is used. 1 = LSB first format is used. Switch Mode section for details on how to program these registers in direct switch mode. 19 Sync Clock Disable 0 = the SYNC_CLK pin is active. logic is shut down, minimizing the noise generated by the digital circuitry. 18:17 Open Leave these bits in their default values. 16 Direct Switch Mode Active 0 = direct switch mode is disabled. 1 = direct switch mode is enabled. 15 Clear Auxiliary Accumulator 0 = normal oper ation of the auxiliary accumulator (default). profile change and the next rising edge of SYNC_CLK. 14 Clear Phase Accumulator 0 = normal operat ion of the DDS phase accumulator (default). 1 = asynchronous, static reset of the DDS phase accumulator.

Rev. E | Page 29 of 32 Bit(s) Bit Name Description 13:12 Destination 00 = In direct switch mode, use this setting for FSK. In linear sweep mode, the auxiliary accumulator is used for frequency sweeping. In programmable modulus mode, these bits must be 00. 01 = In direct switch mode, use this setting for PSK. In linear sweep mode, the auxiliary accumulator is used for phase sweeping. 11 Auxiliary Accumulator Enable 0 = auxiliary accumulator is inactive. 1 = auxiliary accumulator is active. 10 DC Output Active This bit is ignored if linear sweep is disabled (see CFR1 [11]). 0 = normal operating state. 1 = the output of the DAC is driven to full-scale and the DDS output is disabled.

9 Linear Sweep State Trigger

0 = edge triggered mode active. 1 = state triggered mode active. 8 Linear Sweep No-Dwell Active This bit is ignore d if linear sweep is disabled (see CFR1[11]). 0 = when a sweep is completed, the device holds at the final state. 1 = when a sweep is completed, the device reverts to the initial state. 7 External Power-Down Mode 0 = the external power-down mode selected is the fast recovery power-down mode. In this mode, when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered down. 1 = the external power-down mode selected is the full power-down mode. In this mode, when the PWR_DWN_CTL pin is high, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up. 6 Digital Power-Down 0 = the digital core is enabled for operation. 1 = the digital core is disabled and is in a low power dissipation state. 5 DAC Power-Down 0 = the DAC is enabled for operation. 1 = the DAC is disabled and is in its lowest power dissipation state. 4 Clock Input Power-Down 0 = normal operation. 1 = shut down all clock generation including the system clock signal going into the digital section. 3 LOAD SRR @ IO_UPDATE 0 = every time the linear sweep rate register is updated, the ramp rate timer keeps its operation until it times out and then loads the update value into the timer. 1 = the timer is interrupted immediately upon the assertion of IO_UPDATE and the value is loaded.

2 Autoclear Auxiliary

0 = normal operation. 1 = the auxiliary accumulator is synchronously cleared (zero is loaded) for one cycle upon receipt of the IO_UPDATE sequence indicator. 1 Autoclear Phase Accumulator 0 = normal operation. 1 = the phase accumulator is synchronously cleared for one cycle upon receipt of the IO_UPDATE sequence indicator. 0 Enable Sine Output 0 = the angle-to-amplitude conversion logic employs a cosine function. 1 = the angle-to-amplitude conversion logic employs a sine function.

Address 0x01; 2 bytes are assigned to this register. Table 11. Bit Descriptions for CFR2 15 PLL Output Div by 2 See Table 7 for details on multiplication factor configuration. 8 Open Leave this bit at the default state. 7 CMOS Clock Mode See Table 6 for di rections on programming this bit. 6 Crystal Clock Mode See Table 6 for directions on programming this bit.

5 PLL Power-Down 0 = PLL is active

4 PLL LO Range 0 = use this setting for PLL if the PLL reference frequency is >5 MHz. 1 = use this setting for PLL if the PLL reference frequency is <5 MHz. 3 PLL Input Div by 2 0 = the PLL reference fr equency = the REF_CLK input frequency. 1 = the PLL reference frequency = ½ the REF_CLK input frequency.

2 VCO2 Sel 0 = use this setting for VCO frequencies below 100 MHz and/or to optimize for power

PLL power-down bit (CFR2 [5]) going low. 1 PLL Reset 0 = the PLL logic is reset and non-operational until this bit is set. 1 = the PLL logic operates normally. 0 PLL Lock This read-only bit is set when the REF_CLK PLL is locked. Address 0x02; 4 bytes are assigned to this register. Table 12. Bit Descriptions for DAC Control Register 15:14, 10 Open Leave these bits at their default state. 9:0 FSC This 10-bit number controls the full-scale output current of the DAC. 31:16,13:11 Reserved Leave these bits at their default state. Address 0x03, 4 bytes are assigned to this register. Table 13. Bit Descriptions for FTW Register 31:0 Frequency Tuning Word 32-bit frequency tuning word. Address 0x04, 2 bytes are assigned to this register. Table 14. Bit Descriptions for POW Register 15:14 Open Leave these bits at their default state. 13:0 Phase Offset Word 14-bit phase offset word.

Table 15. Bit Descriptions for Linear Sweep Limit Register to set the B value found in the AN-953 Application Note. to set the X value found in the AN-953 Application Note. Table 16. Bit Descriptions for Linear Sweep Step Size Register 63:32 Falling Delta Word 32-bit linear sweep decrement step size value. are used to set the A value found in the AN-953 Application Note. Table 17. Bit Descriptions for Linear Sweep Rate Register using the external profile select pins. Address 0x09 to Address 0x10, 6 bytes are assigned to these registers. Table 18. Bit Descriptions for Profile 0 to Profile 7 Single Tone Register 47:46 Open Leave these bits at their default state. 45:32 Phase Offset Word This 14-bit nu mber controls the DDS phase offset. 31:0 Frequency Tuning Word This 32-bit number controls the DDS frequency.

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

Figure 36. 32-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the prop erty of their respective owners.