AD9911BCPZ

AD9911 AD | Alldatasheet

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Technical content

500 MSPS Direct Digital Synthesizer

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

Patented SpurKiller technology Multitone generation Test-tone modulation Up to 800 Mbps data throughput Matched latencies for frequency/phase/amplitude changes Linear frequency/phase/amplitude sweeping capability Up to 16 levels of FSK, PSK, ASK Programmable DAC full-scale current 32-bit frequency tuning resolution 14-bit phase offset resolution 10-bit output amplitude-scaling resolution Software-/hardware-controlled power-down Multiple device synchronization Selectable 4× to 20× REF_CLK multiplier (PLL) Selectable REF_CLK crystal oscillator 56-lead LFCSP

APPLICATIONS

Test and measurement equipment Commercial and amateur radio exciter Radar and sonar Test-tone generation Fast frequency hopping Clock generation GENERAL DESCRIPTION The AD9911 is a complete direct digital synthesizer (DDS). This device includes a high speed DAC with excellent wideband and narrowband spurious-free dynamic range (SFDR) as well as three auxiliary DDS cores without assigned digital-to-analog converters (DACs). These auxiliary channels are used for spur reduction, multitone generation, or test-tone modulation. The AD9911 is the first DDS to incorporate SpurKiller technology and multitone generation capability. Multitone mode enables the generation up to four concurrent carriers; frequency, phase and amplitude can be independently programmed. Multitone generation can be used for system tests, such as inter-modulation distortion and receiver blocker sensitivity. SpurKilling enables customers to improve SFDR performance by reducing the magnitude of harmonic components and/or the aliases of those harmonic components. Test-tone modulation efficiently enables sine wave modulation of amplitude on the output signal using one of the auxiliary DDS cores. The AD9911 can perform modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is implemented by storing profiles in the register bank and applying data to the profile pins. In addition, the AD9911 supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation. (continued on Page 3) 500MSPS DDS CORE REF CLOCK INPUT CIRCUITRY TIMING AND CONTROL 10-BIT DAC RECONSTRUCTED SINE WAVE MODULATION CONTROL SYSTEM CLOCK SOURCE USER INTERFACE 05785-002 SPUR REDUCTION/ MULTITONE Figure 1. Basic Block Diagram

Rev. 0 | Page 2 of 44 TABLE OF CONTENTS I/O_Update, SYNC_CLK, and System Clock

REVISION HISTORY

5/06—Revision 0: Initial Version

combination with the REF_CLK multiplier. found in earlier Analog Devices DDS products. programmable modes of I/O operation. different full-scale currents.

3.3 V and requires that the Pin DVDD_I/O (Pin 49) be

32 PHASE/

Figure 2. Functional Block Diagram

Rev. 0 | Page 4 of 44 SPECIFICATIONS AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; RSET = 1.91 kΩ; external reference clock frequency = 500 MSPS (REF_CLK multiplier bypassed), unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments REF CLOCK INPUT CHARACTERISTICS Frequency Range REF_CLK Multiplier Bypassed 1 500 MHz REF_CLK Multiplier Enabled 10 125 MHz Internal VCO Output Frequency Range VCO Gain Bit Set1 255 500 MHz Internal VCO Output Frequency Range VCO Gain Bit Cleared 100 160 MHz Crystal REF_CLK Source Range 20 30 MHz Input Power Sensitivity −5 +3 dBm Measured at the pin (single-ended) Input Voltage Bias Level 1.15 V Input Capacitance 2 pF Input Impedance 1500 Ω Duty Cycle with REF_CLK Multiplier Bypassed 45 55 % Duty Cycle with REF_CLK Multiplier Enabled 35 65 % CLK Mode Select (Pin 24) Logic 1 V 1.25 1.8 V 1.8 V digital input logic CLK Mode Select (Pin 24) Logic 0 V 0.5 V 1.8 V digital input logic DAC OUTPUT CHARACTERISTICS Must be referenced to AVDD Full-Scale Output Current 10 mA 10 mA is set by RSET = 1.91 kΩ Gain Error −10 +10 %FS Output Current Offset 1 25 μA Differential Nonlinearity ±0.5 LSB Integral Nonlinearity ±1.0 LSB Output Capacitance 3 pF Voltage Compliance Range AVDD – 0.50 AVDD + 0.50 V WIDEBAND SFDR The frequency range for wideband SFDR is defined as dc to Nyquist

1 MHz to 20 MHz Analog Output −65 dBc

20 MHz to 60 MHz Analog Output −62 dBc

60 MHz to 100 MHz Analog Output −59 dBc

100 MHz to 150 MHz Analog Output −56 dBc

150 t MHz to 200 MHz Analog Output −53 dBc WIDEBAND SFDR Improvement Spur Reduction Enabled Programs devices on an individual basis to enable spur reduction. See the SpurKiller/Multitone Mode section.

60 MHz to 100 MHz Analog Output 8 dBc

100 MHz to 150 MHz Analog Output 15 dBc

150 MHz to 200 MHz Analog Output 12 dBc

Rev. 0 | Page 5 of 44 Parameter Min Typ Max Unit Test Conditions/Comments NARROWBAND SFDR

1.1 MHz Analog Output (±10 kHz) −90 dBc

1.1 MHz Analog Output (±50 kHz) −88 dBc

1.1 MHz Analog Output (±250 kHz) −86 dBc

1.1 MHz Analog Output (±1 MHz) −85 dBc

15.1 MHz Analog Output (±10 kHz) −90 dBc

15.1 MHz Analog Output (±50 kHz) −87 dBc

15.1 MHz Analog Output (±250 kHz) −85 dBc

15.1 MHz Analog Output (±1 MHz) −83 dBc

40.1 MHz Analog Output (±10 kHz) −90 dBc

40.1 MHz Analog Output (±50 kHz) −87 dBc

40.1 MHz Analog Output (±250 kHz) −84 dBc

40.1 MHz Analog Output (±1 MHz) −82 dBc

75.1 MHz Analog Output (±10 kHz) −87 dBc

75.1 MHz Analog Output (±50 kHz) −85 dBc

75.1 MHz Analog Output (±250 kHz) −83 dBc

75.1 MHz Analog Output (±1 MHz) −82 dBc

100.3 MHz Analog Output (±10 kHz) −87 dBc

100.3 MHz Analog Output (±50 kHz) −85 dBc

100.3 MHz Analog Output (±250 kHz) −83 dBc

100.3 MHz Analog Output (±1 MHz) −81 dBc

200.3 MHz Analog Output (±10 kHz) −87 dBc

200.3 MHz Analog Output (±50 kHz) −85 dBc

200.3 MHz Analog Output (±250 kHz) −83 dBc

200.3 MHz Analog Output (±1 MHz) −81 dBc

PHASE NOISE CHARACTERISTICS Residual Phase Noise @ 15.1 MHz (fOUT) 1 kHz Offset –150 dBc/Hz 10 kHz Offset –159 dBc/Hz 100 kHz Offset –165 dBc/Hz

1 MHz Offset –165 dBc/Hz

Residual Phase Noise @ 40.1 MHz (fOUT) 1 kHz Offset –142 dBc/Hz 10 kHz Offset –151 dBc/Hz 100 kHz Offset –160 dBc/Hz

1 MHz Offset –162 dBc/Hz

Residual Phase Noise @ 75.1 MHz (fOUT) 1 kHz Offset –135 dBc/Hz 10 kHz Offset –146 dBc/Hz 100 kHz Offset –154 dBc/Hz

1 MHz Offset –157 dBc/Hz

Residual Phase Noise @ 100.3 MHz (fOUT) 1 kHz Offset –134 dBc/Hz 10 kHz Offset –144 dBc/Hz 100 kHz Offset –152 dBc/Hz

1 MHz Offset –154 dBc/Hz

Rev. 0 | Page 6 of 44 Parameter Min Typ Max Unit Test Conditions/Comments Residual Phase Noise @ 15.1 MHz (fOUT) with REF_CLK Multiplier Enabled 5× 1 kHz Offset –139 dBc/Hz 10 kHz Offset –149 dBc/Hz 100 kHz Offset –153 dBc/Hz

1 MHz Offset –148 dBc/Hz

Residual Phase Noise @ 40.1 MHz (fOUT) with REF_CLK Multiplier Enabled 5× 1 kHz Offset –130 dBc/Hz 10 kHz Offset –140 dBc/Hz 100 kHz Offset –145 dBc/Hz

1 MHz Offset –139 dBc/Hz

Residual Phase Noise @ 75.1 MHz (fOUT) with REF_CLK Multiplier Enabled 5× 1 kHz Offset –123 dBc/Hz 10 kHz Offset –134 dBc/Hz 100 kHz Offset –138 dBc/Hz

1 MHz Offset –132 dBc/Hz

Residual Phase Noise @ 100.3 MHz(fOUT) with REF_CLK Multiplier Enabled 5× 1 kHz Offset –120 dBc/Hz 10 kHz Offset –130 dBc/Hz 100 kHz Offset –135 dBc/Hz

1 MHz Offset –129 dBc/Hz

Residual Phase Noise @ 15.1 MHz (fOUT) with REF_CLK Multiplier Enabled 20× 1 kHz Offset –127 dBc/Hz 10 kHz Offset –136 dBc/Hz 100 kHz Offset –139 dBc/Hz

1 MHz Offset –138 dBc/Hz

Residual Phase Noise @ 40.1 MHz (fOUT) with REF_CLK Multiplier Enabled 20× 1 kHz Offset –117 dBc/Hz 10 kHz Offset –128 dBc/Hz 100 kHz Offset –132 dBc/Hz

1 MHz Offset –130 dBc/Hz

Residual Phase Noise @ 75.1 MHz (fOUT) with REF_CLK Multiplier Enabled 20× 1 kHz Offset –110 dBc/Hz 10 kHz Offset –121 dBc/Hz 100 kHz Offset –125 dBc/Hz

1 MHz Offset –123 dBc/Hz

Residual Phase Noise @ 100.3 MHz (fOUT) with REF_CLK Multiplier Enabled 20× 1 kHz Offset –107 dBc/Hz 10 kHz Offset –119 dBc/Hz 100 kHz Offset –121 dBc/Hz

1 MHz Offset –119 dBc/Hz

Rev. 0 | Page 7 of 44 Parameter Min Typ Max Unit Test Conditions/Comments I/O PORT TIMING CHARACTERISTICS Maximum Frequency Clock (SCLK) 200 MHz Minimum SCLK Pulse Width Low (tPWL) 1.6 ns Minimum SCLK Pulse Width High (tPWH) 2.2 ns Minimum Data Set-Up Time (tDS) 2.2 ns Minimum Data Hold Time 0 ns Minimum CSB Set-Up Time (tPRE) 1.0 ns Minimum Data Valid Time for Read Operation 12 ns MISCELLANEOUS TIMING CHARACTERISTICS Master_Reset Minimum Pulse Width 1 Minimum pulse width = 1 sync clock period I/O_Update Minimum Pulse Width 1 Minimum pulse width = 1 sync clock period Minimum Set-Up Time (I/O_Update to SYNC_CLK) 4.8 ns Rising edge to rising edge Minimum Hold Time (I/O_Update to SYNC_CLK) 0 ns Rising edge to rising edge Minimum Set-Up Time (Profile Inputs to SYNC_CLK) 5.4 ns Minimum Hold Time (Profile Inputs to SYNC_CLK) 0 ns Minimum Set-Up Time (SDIO Inputs to SYNC_CLK) 2.5 ns Minimum Hold Time (SDIO Inputs to SYNC_CLK) 0 ns Propagation Delay Between REF_CLK and SYNC_CLK 2.25 3.5 5.5 ns CMOS LOGIC INPUT VIH 2.0 V VIL 0.8 V Logic 1 Current 3 12 μA Logic 0 Current −12 μA Input Capacitance 2 pF CMOS LOGIC OUTPUTS (1 mA Load) VOH 2.7 V VOL 0.4 V POWER SUPPLY Total Power Dissipation—Single-Tone Mode 241 mW Dominated by supply variation Total Power Dissipation—With Sweep Accumulator 241 mW Dominated by supply variation Total Power Dissipation—3 Spur Reduction/Multitone Channels Active 351 mW Dominated by supply variation Total Power Dissipation—Test-Tone Modulation 264 mW Dominated by supply variation Total Power Dissipation—Full Power Down 1.8 mW IAVDD—Single-Tone Mode 73 mA IAVDD— Sweep Accumulator, REF_CLK Multiplier, and 10-Bit Output Scalar Enabled 73 mA IDVDD—Single-Tone Mode 50 mA IDVDD—Sweep Accumulator, REF_CLK Multiplier, and 10-Bit Output Scalar Enabled 50 mA IDVDD_I/O 40 mA IDVDD = read IDVDD_I/O 30 mA IDVDD = write IAVDD Power-Down Mode 0.7 mA IDVDD Power-Down Mode 1.1 mA

Rev. 0 | Page 8 of 44 Parameter Min Typ Max Unit Test Conditions/Comments DATA LATENCY (PIPELINE DELAY) SINGLE- TONE MODE2, 3 Frequency, Phase, and Amplitude Words to DAC Output with Matched Latency Enabled

29 SYSCLK

Frequency Word to DAC Output with Matched Latency Disabled Phase Offset Word to DAC Output with Matched Latency Disabled

25 SYSCLK

Amplitude Word to DAC Output with Matched Latency Disabled

17 SYSCLK

DATA LATENCY (PIPELINE DELAY) MODULATION MODE4 Frequency Word to DAC Output 34 SYSCLK Cycles Phase Offset Word to DAC Output 29 SYSCLK Cycles Amplitude Word to DAC Output 21 SYSCLK Cycles DATA LATENCY (PIPELINE DELAY) LINEAR SWEEP MODE4 Frequency Rising/Falling Delta Tuning Word to DAC Output

41 SYSCLK

Phase Offset Rising/Falling Delta Tuning Word to DAC Output

37 SYSCLK

Amplitude Rising/Falling Delta Tuning Word to DAC Output 1 For the VCO frequency range of 160 MHz to 255 MHz, the appropriate setting for the VCO gain bit is dependent upon supply, temperature and process. Therefore, in a production environment this frequency band must be avoided. 2 Data latency is reference to the I/O_UPDATE pin.

3 Data latency is fixed and the units are system clock (SYSCLK) cycles

4 Data latency is referenced to a profile change.

degradation or loss of functionality.

1. AVOID OVERDRIVING DIGITAL
2. REF_CLK INPUTS ARE INTERNALLY BIASED AND
3. OSC INPUTS ARE DC-COUPLED.

Figure 3. CMOS Digital Inputs Figure 4. DAC Outputs Figure 5. REF_CLK Inputs

35 IOUT

36 IOUT

37 AVDD

38 AGND

39 AVDD

34 AGND

33 AVDD

31 AVDD

30 AVDD

29 AVDD

1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS
2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V.

Figure 6. Pin Configuration Table 3. Pin Function Descriptions state shown in the Register Map section. 4 PWR_DWN_CTL I External Power-Down Control. See the Power Down Functions section for details. AVDD I Analog Power Supply Pins (1.8 V). 18, 20, 25, 34, 38 AGND I Analog Ground Pins. 45, 55 DVDD I Digital Power Supply Pins (1.8 V). 44, 56 DGND I Digital Power Ground Pins. 35 IOUT O Complementary DAC Output. Terminates into AVDD. 36 IOUT O True DAC Output. Terminates into AVDD. connected from Pin 17 to AGND. the network consists of a 0 Ω resistor in series with a 680 pF capacitor tied to AVDD.

Rev. 0 | Page 11 of 44 Pin No. Mnemonic I/O Description 6, 10, 12, 16, 28, 32 NC N/A No Connection. Analog Devices recommends leaving these pins floating. 40, 41, 42, 43 P0, P1, P2, P3 I These data pins are used for modulation (FSK, PSK, ASK), start/stop for the sweep accumulator, and ramping up/down the output amplitude. Any toggle of these data inputs is equivalent to an I/O_UPDATE. The data is synchronous to the SYNC_CLK (Pin 54). The data inputs must meet the set-up and hold time requirements to the SYNC_CLK. This guarantees a fixed pipeline delay of data to the DAC output; otherwise, a ±1 SYNC_CLK period of uncertainty occurs. The functionality of these pins is controlled by profile pin configuration (PPC) bits in Register FR1 <12:14>. 46 I/O_UPDATE I A rising edge triggers data transfer from the I/O port buffer to active registers. I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the set-up and hold time requirements to the SYNC_CLK to guarantee a fixed pipeline delay of data to DAC output. If not, a ±1 SYNC_CLK period of uncertainty occurs. The minimum pulse width is one SYNC_CLK period. 47 CS I The active low chip select allows multiple devices to share a common I/O bus (SPI). 48 SCLK I Data Clock for I/O Operations. Data bits are written on the rising edge of SCLK and read on the falling edge of SCLK. 49 DVDD_I/O I 3.3 V Digital Power Supply for SPI Port and Digital I/O. 50 SDIO_0 I/O Data pin SDIO_0 is dedicated to the I/O port only. 51, 52, 53 SDIO_1, SDIO_2, SDIO_3 I/O Data pins SDIO_1:3 can be used for the I/O port or to initiate a ramp up/ramp down (RU/RD) of the DAC output amplitude. 54 SYNC_CLK O The SYNC_CLK, which runs at ¼ the system clock rate, can be disabled. I/O_UPDATE and profile changes (Pin 40 to Pin 43) are synchronous to the SYNC_CLK. To guarantee a fixed pipeline delay of data to DAC output, I/O_UPDATE and profile changes (Pin 40 to Pin 43) must meet the set-up and hold time requirements to the rising edge of SYNC_CLK. If not, a ±1 SYNC_CLK period of uncertainty exists.

Figure 31. Primary Channel (62 MHz) 100% Amplitude Modulated

amplitude information by a cos (θ) operation. FTW = the frequency tuning word. 232 represents the capacity of the phase accumulator’ . maximum amplitude to prevent overdriving the DAC input. achieve equal amplitude for all carriers. spur may be impossible to match frequency. function is programmed using internal registers. Figure 35. Typical DAC Output Termination Configuration

Rev. 0 | Page 19 of 44 MODES OF OPERATION SINGLE-TONE MODE To configure the AD9911 in single-tone mode, the auxiliary DDS cores (CH0, CH2, and CH3) must be disabled by using the channel enable bits and digital powering down (CSR bit <7>) the three auxiliary DDS cores. Only CH1 remains enabled. See the Register Maps section for a description of the channel enable bits in the channel select register or CSR (Register 0x00). The channel enable bits are enabled or disabled immediately after the CSR data byte is written. An I/O_UPDATE is not required for channel enable bits. The two main registers used in this mode, Register 0x04 and Register 0x05, contain the frequency tuning word and the phase offset word for CH1. The following is a basic protocol to program a frequency tuning word and/or phase offset word for CH1. 1. Power up the AD9911 and issue a master reset. A master reset places the part in single-bit mode for serial programming operations (refer to the I/O Modes of Operation section). The frequency tuning word and phase offset word for CH1 defaults to 0. 2. Disable CH0, CH2, CH3 and enable CH1 using the channel enable bits in Register 0x00. 3. Using the I/O port, program the desired frequency tuning word (Register 0x04) and/or the phase offset word (Register 0x05) for CH1. 4. Send an I/O update signal. CH1 should output its programmed frequency and/or phase offset value, after a pipeline delay (see Table 1). Single-Tone Mode—Matched Pipeline Delay In single-tone mode, the AD9911 offers matched pipeline delay to the DAC input for all frequency, phase, and amplitude changes. The result is that frequency, phase, and amplitude changes arrive at the DAC input simultaneously. The feature is enabled by asserting the match pipeline delay bit found in the channel function register (CSR) (Register 0x03). This feature is available in single-tone mode only. SPURKILLER/MULTITONE MODE For both SpurKiller and multitone mode, the frequency, phase and amplitude settings of the auxiliary channels and the primary channel use Register 0x04 Bits <31:0> for frequency and Register 0x05 Bits <13:0> for phase. Note the channel enable bits in the CSR register must be use to distinguish the content of each channel. See the I/O Port section for details. For multitone mode, the digital content of the three auxiliary DDS channels are summed with the primary channel. Each tone can be individually programmed for frequency, phase and amplitude as well as individually modulated using the profile pins in shift-keying modulation. See Figure 24 and Figure 27 for examples. Note the data align bits in Register 0x03 Bits <18:16>, provide a coarse amplitude adjust setting for the auxiliary channels. These bits default to clear; for multitone mode these bit should typically be set. For SpurKiller mode, the digital contents of the three auxiliary DDS channels are attenuated and summed with the primary channel. In this manner, harmonic spurs from the DAC can be reduced. This is accomplished by matching the frequency of the harmonic component, the amplitude, and the phase (180° offset) of the desired spur on one of the SpurKiller channels. Bench level observations and manipulation are required to establish the optimal parameter settings for the SpurKiller channel(s). The parameters are dependent on the fundamental frequency and system clock frequency. The repeatability of these settings on a unit-to-unit basis depends directly on the SFDR variation of the DAC. The DAC on the AD9911 has enough part-to-part SFDR variation that using a set of fixed programming values across multiple devices will not consistently improve SFDR. Spur reduction performance on an individual device is stable over supply and temperature. The SpurKiller/multitone mode configuration is illustrated in Figure 36. The amplitude of the auxiliary channels uses coarse and fine adjustments to match the amplitude of the targeted spur. The coarse adjust is implemented via the data align bits in Register 0x03 Bits <18:16>. The approximate amplitude of the auxiliary channel is programmable between −60 dB and −12 dB com- pared to the full-scale fundamental, per the following equation: AMP = −60 dB + (D × 6 dB) where AMP is the amplitude and D is the decimal value (0-7) of the data align bits For fine amplitude adjustments, the 10-bit output scalar (multiplier) of the auxiliary channel in Register 0x06 Bit <0:9> is used. The multiplier is enabled by Register 0x06 Bit <12>. A single active SpurKiller channel targeting the second harmonic is expressed as fOUT = A × cos(ωt + Φ1) + B × cos(2ωt + Φ2) + B × cos(2ωt + Φ2 + 180°) + (all other spurious components) where B × cos(2ωt + Φ2 + 180°) represents the fundamental tone of the SpurKiller channel.

1 0 Profile Pin 3 configured for RU/RD operation. indicates that it does not matter. disabled. Table 9 displays how the profile pins are assigned. Table 9. 2-Level Modulation—No RU/RD (Register 0x0A) frequency is chosen. disabled. Table 10 displays how the profile pins are assigned. Table 10. 4-Level Modulation—No RU/RD Register 3 (Register 0x0C) are presented to CH1 output. Table 11. 8-Level Modulation—No RU/RD Profile Register 7 (Register 0x10) are presented to CH1 output. Table 12. 16-Level Modulation—No RU/RD Register 14 (Register 0x17) are presented to CH1 output.

Rev. 0 | Page 23 of 44 Table 13. 2-Level Modulation—RU/RD Table 14. 8-Level Modulation—RU/RD Table 15. 2-Level Modulation Using SDIO Pins for RU/RD Table 16. SDIO Pins assignments, including SDIO pin assignments. CH1 output. SDIO Pin 1 and Pin 2 provide the RU/RD function. set to 16. See the pin assignment shown in Table 18. Profile Register 13 (Register 0x16) are presented to CH1 output. The SDIO_1 pin provides the RU/RD function. down (CSR bit <7>) of the auxiliary channels is recommended. Figure 41 depicts the linear sweep block diagram. Table 19). The modulation level bits must be set to 00 (2-level).

Description

0 MUX 1

Figure 41. Linear Sweep Capability overflow, an uncontrolled, continuous sweep operation occurs. Linear Sweep No Dwell Mode section. Figure 42. Linear Sweep Mode grammed during the transition. minimum time interval between steps is 1/125 MHz × 1 = 8 ns. The maximum time interval is (1/125 MHz) × 255 = 2.04 μs. enable CFR<14> = 1, linear sweep no-dwell CFR<15> = 0. lator and the RSRR register is loaded into the sweep rate timer. register is loaded into the sweep rate timer.

Figure 45. Linear Sweep Enabled-No Dwell Bit Cleared and CFR <2> is the automatic clear phase accumulator bit. programmed low, the respective accumulator is released. RU/RD) are described in this section. bypassed by clearing the multiplier enable bit (ACR <12> = 0). controlled using either the profile pins or the SDIO1:3 pins. Table 21. Manual mode is selected by programming ACR control register (Register 0x06 Bits <9:0>). step size is selected using the ACR<15:14>. step size options available. a value less than full scale.

Figure 46. Output Amplitude Control Configurations Where x is the decimal value in Register 00x06 Bits <23:16>. minimum time interval between steps is 1/125 MHz × 1 = 8 ns. The maximum time interval is (1/125 MHz) × 255 = 2.04 μs. the timer is forced to load before reaching a count of 1.

Rev. 0 | Page 28 of 44 SYNCHRONIZING MULTIPLE AD9911 DEVICES The AD9911 allows easy synchronization of multiple AD9911 devices. At power-up, the phase of SYNC_CLK may be offset between multiple devices. There are three options (one automatic mode and two manual modes) to compensate for this offset and align the SYNC_CLK edges. These modes force the internal state machines of multiple devices to a common state, which aligns SYNC_CLKs. Any mismatch in REF_CLK phase between devices results in a corresponding phase mismatch on the SYNC_CLKs. OPERATION The first step is to program the master and slave devices for their respective roles. Configure the master device by setting its master enable bit (FR2 <6>). This causes the SYNC_OUT of the master device to output a pulse whose pulse width equals one system clock period and whose frequency equals ¼ of the system clock frequency. Configuring device(s) as slaves is performed by setting the slave enable bit (FR2 <7>). AUTOMATIC MODE SYNCHRONIZATION In automatic mode, synchronization is achieved by connecting the SYNC_OUT pin on the master device to the SYNC_IN pin of the slave device(s). Devices are configured as master or slave through programming bits, accessible via the I/O port. A configuration for synchronizing multiple AD9911 devices in automatic mode is shown in the Application Circuits section. In this configuration, the AD9510 provides coincident REF_CLK and SYNC_IN to all devices. In this mode, slave devices sample SYNC_OUT pulses from the master device and a comparison of all state machines is made by the auto-synchronization circuitry. If the slave device(s) state machines are not identical to the master, the slave device(s) state machines stall for one system clock cycle. This procedure synchronizes the slave device(s) within three SYNC_CLK periods. Delay Time Between SYNC_OUT and SYNC_IN When the delay between SYNC_OUT and SYNC_IN exceeds one system clock period, phase offset bits (FR2 <1:0>) are used to compensate. Without the compensation factor, a phase error of 90°, 180°, or 270° might exist. The default state of these bits is 00, which implies that the SYNC_OUT of the master and the SYNC_IN of the slave have a propagation delay of less than one system clock period. If the propagation time is greater than one system clock period, the time should be measured and the appropriate offset programmed. Table 21 describes the delays required per system clock offset value. Table 21. System Clock Offset Value SYNC_OUT/SYNC_IN Propagation Delay 00 0 ≤ delay ≤ 1 01 1 ≤ delay ≤ 2 10 2 ≤ delay ≤ 3 11 3 ≤ delay ≤ 4 Automatic Synchronization Status Bit If a slave device falls out of sync, the sync status bit is set. This bit can be read through the I/O port bit (FR2 <5>). It clears automatically when read. If the device reacquires sync before the bit is read, the alarm will remain high. The bit does not necessarily reflect the current state of the device. The status bit can be masked by writing Logic 1 to the synchronization status mask bit (FR2 <4>). When masked, the bit is held low. MANUAL SOFTWARE MODE SYNCHRONIZATION The manual software mode is enabled by setting the manual synchronization bit (FR1 <0>). In this mode, the I/O update that resets the Manual SW synchronization bit stalls the state machine of the clock generator for one system clock cycle. Stalling the clock generation state machine by one cycle changes the phase relationship of SYNC_CLK between devices by one system clock period (90°). Note that the user may repeat this process until the devices have the corresponding SYNC_CLK signals in the desired phase relationship. The SYNC_IN input can be left floating since this input has an internal pull-up. The SYNC_OUT is not used. MANUAL HARDWARE MODE SYNCHRONIZATION Manual hardware mode is enabled by setting the manual SW synchronization bit (FR1 <1>). In this mode, the SYNC_CLK stalls by one system clock cycle each time a rising edge is detected on the SYNC_IN input. Stalling the SYNC_CLK state machine by one cycle changes the phase relationship of SYNC_CLK between devices by one system clock period (90°). Note that the process can be repeated until the devices have SYNC_CLK signals in the desired phase relationship. The SYNC_IN input can be left floating since this input has an internal pull-up. The SYNC_OUT is not used.

data from the I/O buffer to the active registers in the device. Data in the I/O buffer is inactive. hardware to the AD9911 internal clocks. pulse width greater than one SYNC_CLK period. the I/O buffer is transferred to the active registers. SYNC_CLK and has zero hold time and 4.8 ns setup time. THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B. Figure 47. I/O_UPDATE Timing

indicates a read operation; Cleared indicates a write operation. internal state machines of the AD9911. I/O Modes of Operation section for more information. The SDO function is available in single-bit (3-wire) mode only. function is not available in 2-bit and 4-bit I/O modes. The SYNC_I/O function is available in 1-bit and 2-bit modes. machines without affecting the addressable register contents. function is not available in 4-bit I/O mode. must be written in the manner selected by CSR <0>. byte is considered an instruction byte. byte is considered an instruction byte.

• Single-bit serial 2-wire mode (default mode).
• Single-bit, 3-wire mode.
• 2-bit mode.
• 4-bit mode (SYNC_I/O not available). Table 23 displays the function of all six I/O interface pins, depending on the mode of I/O operation selected.

Table 23. I/O Port Pin Function vs. I/O Mode 1In this mode, these pins can be used for RU/RD operation.

Rev. 0 | Page 35 of 44 REGISTER MAPS CONTROL REGISTER MAP Table 24. Register Name (Address) Bit Range Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value Channel Select Register (CSR) (0x00) <7:0> Auxiliary Channel 3 (W/R enable 1 ) Auxiliary Channel 2 (W/R enable Primary Channel 1 (W/R enable Auxiliary Channel 0 (W/R enable Must be 0 I/0 mode select <2:1> LSB first 0xF0 Function Register 1 (FR1) (0x01) <7:0> Reference clock input power down External power down mode Sync clock disable DAC reference power down Open Test- tone enable Manual hardware synchronization Manual software synchronization 0x00 <15:8> Open Profile pin configuration <14:12> Ramp up/ramp down <11:10> Modulation Level <9:8> 0x00 <23:16> VCO gain control PLL divider ratio <22:18> Charge pump control <17:16> 0x00 Function Register 2 (FR2) (0x02) <7:0> Multidevice synchronization slave enable Multidevice synchronization master enable Multidevice synchronization status Multidevice synchronization mask Open <3:2> System clock offset <1:0> 0x00 <15:8> All channels auto clear sweep accumulator All channels clear sweep accumulator All channels auto clear phase accumulator All channels clear phase accumulator Open <11:10> Open <9:8> 0x00 1 Channel enable bits do not require an I/O update to be activated. These bits are active immediately after the byte containing the bits is written. All other bits need an I/O update to become active. The channel enable bits determine if the channel registers and/or profile registers are written to or not.

Rev. 0 | Page 36 of 44 CHANNEL REGISTER MAP Table 25. Register Name (Address) Bit Range Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 Default Value Channel Function1 (CFR) (0x03) <7:0> Digital power- down DAC power down Matched pipe delays active Auto clear sweep accumulator Clear sweep accumulator Auto clear phase accumulator Clear phase accumulator Sine wave output enable 0x02 <15:8> Linear sweep no-dwell Linear sweep enable Load SRR at I/O Update Open Open Must be 0 DAC full-scale current control <9:8> 0x03 <23:16> Amplitude frequency phase select <23:22> Open <21:19> Data align bits for SpurKiller mode <18:16> 0x00 <7:0> Frequency Tuning Word 0 <7:0> 0x00 <15:8> Frequency Tuning Word 0 <15:8> <23:16> Frequency Tuning Word 0 <23:16> Channel Frequency Tuning Word 0 1 (CTW0) (0x04) <31:24> Frequency Tuning Word 0 <31:24> <7:0> Phase Offset Word 0 0x00 Channel Phase1 Offset Word 0 (CPOW0) (0x05) <15:8> Open <15:14> Phase Offset Word 0 <13:8> 0x00 <7:0> Amplitude scale factor 0x00 <15:8> Increment/decrement step size <15:14> Open Amplitude multiplier enable Ramp-up/ ramp-down enable Load ARR at I/O update Amplitude scale factor <9:8> 0x00 Amplitude Control (ACR) (0x06) <23:16> Amplitude ramp rate <23:16> – <7:0> Linear sweep rising ramp rate (RSRR) <7:0> – Linear Sweep Ramp Rate1 (LSR) (0x07) <15:8> Linear sweep falling ramp rate (FSRR) <15:8> – LSR Rising Delta1 (RDW) (0x08) <7:0> Rising delta word <7:0> – <15:8> Rising delta word <15:8> – <23:16> Rising delta word <23:16> – <31:24> Rising delta word <31:24> – LSR Falling Delta1 (FDW) (0x09) <7:0> Falling delta word <7:0> – <15:8> Falling delta word <15:8> – <23:16> Falling delta word <23:16> – <31:24> Falling delta word <31:24> – 1 There are four sets of channel registers and profile registers, one per channel. This is not shown in the channel or profile register maps because the addresses of all channel registers and profile registers are the same for each channel. Therefore, the channel enable bits determine if the channel registers and/or profile registers are written to or not. 2 The clear accumulator bit is set after a master reset. It self clears when an I/O update is asserted.

Rev. 0 | Page 37 of 44 PROFILE REGISTER MAP Table 26. Register Name (address) Bit Range MSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 0 Default Value Channel Word 1 (CTW1) (0x0A) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 2 (CTW2) (0x0B) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 3 (CTW3) (0x0C) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 4 (CTW4) (0x0D) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 5 (CTW5) (0x0E) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 6 (CTW6) (0x0F) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 7 (CTW7) (0x10) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 8 (CTW8) (0x11) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 9 (CTW9) (0x12) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 10 (CTW10) (0x13) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 11 (CTW11) (0x14) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 12 (CTW12) (0x15) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 13 (CTW13) (0x16) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 14 (CTW14) (0x17) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> – Channel Word 15 (CTW15) (0x18) <31:0> Frequency tuning word <31:0> or phase word <31:18> or amplitude word <31:22> –

Rev. 0 | Page 38 of 44 CONTROL REGISTER DESCRIPTIONS CHANNEL SELECT REGISTER (CSR) The CSR register determines if channels are enabled or disabled by the status of the channel enable bits. Channels are enabled by default. The CSR register also determines which mode and format (MSB-first or LSB-first) of operation is active. The CSR is comprised of one byte located in Register 0x00. CSR <0> LSB-first CSR <0> = 0 (default), the serial interface, accepts data in MSB- first format. CSR <0> = 1, the interface, accepts data in LSB- first format. CSR <2:1> I/O mode select CSR <2:1> 00 = single bit serial (2-wire mode). 01 = single bit serial (3-wire mode). 10 = 2-bit mode. 11 = 4-bit mode. See the I/O Modes of Operation section for more details. CSR <3> = must be cleared to 0. CSR <7:4> channel enable bits. CSR <7:4> bits are active immediately once written. They do not require an I/O update to take effect. There are four sets of channel registers and profile registers, one per channel. This is not shown in the channel or profile register map. The addresses of all channel registers and profile registers are the same for each channel. Therefore, the channel enable bits distinguish the channel registers and profile registers values for each channel. For example, CSR <7:4> = 0010, only primary Channel 1 receives commands from the channel and profile registers. CSR <7:4> = 0000, only auxiliary Channel 0 receives commands from the channel registers and profile registers. CSR <7:4> = 0011, both Channel 0 and Channel 1 receive commands from the channel registers and profile registers. Function Register 1 (FR1) Description FR1 is comprised of three bytes located in Register 0x01. The FR1 is used to control the mode of operation of the chip. The functionality of each bit is detailed as follows: FR1 <0> manual software synchronization bit. FR1 <0> = 0 (default), the software manual synchronization feature is inactive. FR1 <0> = 1.The manual software synchronization feature is active. See Synchronizing Multiple AD9911 Devices section for details. FR1 <1> Manual hardware synchronization bit. FR1 <1> = 0 (default), the manual hardware synchronization feature is inactive. FR1 <1> = 1, the manual hardware synchronization feature is active. See the Synchronizing Multiple AD9911 Devices +section for details. FR1 <2> Test-tone modulation enable. FR1 <2> = 0 (default) disables and 1 enables. FR1 <3> open. FR1 <4> DAC reference power-down. FR1 <4> = 0 (default). The DAC reference is enabled. FR1 <4> = 1. DAC reference is disabled and powered down. FR1 <5> SYNC_CLK disable. FR1 <5> = 0 (default), the SYNC_CLK pin is active. FR1 <5> = 1. The SYNC_CLK pin assumes a static Logic 0 state (disabled). The pin drive logic is shut down. The synchronization circuitry remains active internally (necessary for normal device operation.) FR1 <6> external power-down mode. FR1 <6> = 0 (default). The external power-down mode is in the fast recovery power-down mode. When the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital logic are powered down. The DACs bias circuitry, PLL, oscillator, and clock input circuitry are not powered down. FR1 <6> = 1. The external power down mode is in the full power-down mode. When the PWR_DWN_CTL input pin is high, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up. FR1 <7> clock input power-down. FR1 <7> = 0 (default). The clock input circuitry is enabled for operation. FR1 <7> = 1. The clock input circuitry is disabled and is in a low power dissipation state. FR1 <9:8> modulation level bits. The modulation (FSK, PSK, and ASK) level bits control the level (2/4/8/16) of modulation to be performed. See Table 7 for settings. FR1 <11:10> RU/RD bits. The RU/RD bits control how the profile pins and SDIO_1:3 pins are assigned. See Table 8 for settings

Rev. 0 | Page 39 of 44 FR1 <12:14> profile pin configuration bits. The profile pin configuration bits assign the profile and SDIO pins for the different tasks. See the Shift Keying Modulation section for examples. FR1 <15> inactive. FR1 <17:16> charge pump current control. FR1 <17:16> = 00 (default), the charge pump current is 75 μA. = 01 charge pump current is 100 μA. = 10 charge pump current is 125 μA. = 11 charge pump current is 150 μA. FR1 <22:18> PLL divider values. FR1 <22:18>, if the value is > 3 and < 21, the PLL is enabled and the value sets the multiplication factor. If the value is < 4 or >20 the PLL is disabled. FR1 <23> PLL VCO gain. FR1 <23> = 0 (default), the low range (system clock below 160 MHz). FR1 <23> = 1, the high range (system clock above 255 MHz). Function Register 2 (FR2) Description The FR2 is comprised of two bytes located in Address 0x02. The FR2 is used to control the various functions, features, and modes of the AD9911. The functionality of each bit is as follows: FR2<1:0> system clock offset. See the Synchronizing Multiple AD9911 Devices section for more details. FR2 <3:2> inactive. FR2 <4:7>. Multidevice synchronization bits. See the Synchronizing Multiple AD9911 Devices section for more details. FR2 <11:8> inactive. FR2 <12> Clear phase accumulator. FR2 <12> = 0 (default), the phase accumulator functions as normal. FR2 <12> = 1, the phase accumulator memory elements are asynchronously cleared. FR2 <13> Auto clear phase accumulator. FR2 <13> = 0 (default). A new frequency tuning word is applied to the inputs of the phase accumulator, but not loaded into the accumulator. FR2 <13> = 1. This bit automatically synchronously clears (loads zeros into) the phase accumulator for one cycle upon reception of the I/O update sequence indicator on both channels. FR2 <14> Clear sweep accumulator. FR2 <14> = 0 (default), the sweep accumulator functions as normal. FR2 <14> = 1, the sweep accumulator memory elements are asynchronously cleared. FR2 <15> Auto clear sweep accumulator. FR2 <15> = 0 (default). A new delta word is applied to the input, as in normal operation, but not loaded into the accumu- lator. FR2 <15> = 1. This bit automatically synchronously clears (loads 0s) the sweep accumulator for one cycle upon reception of the I/O_UPDATE sequence indicator on both channels. CHANNEL FUNCTION REGISTER (CFR) CFR <0> Enable sine function. CFR <0> = 0 (default). The angle-to-amplitude conversion logic employs a cosine function. CFR <0> = 1. The angle-to- amplitude conversion logic employs a sine function. CFR <1> Clear phase accumulator. CFR <1> = 0 (default). The phase accumulator functions as normal. CFR <1> = 1. The phase accumulator memory elements are asynchronously cleared. CFR <2> auto clear phase accumulator. CFR <2> = 0 (default). A new frequency tuning word is applied to the inputs of the phase accumulator, but not loaded into the accumulator. CFR <2> = 1. This bit automatically synchro- nously clears (loads 0s) the phase accumulator for one cycle upon reception of the I/O_UPDATE sequence indicator. CFR <3> clear sweep accumulator. CFR <3> = 0 (default). The sweep accumulator functions as normal. CFR <3> = 1. The sweep accumulator memory elements are asynchronously cleared. CFR <4> auto clear sweep accumulator. CFR <4> = 0 (default). A new delta word is applied to the input, as in normal operation, but not loaded into the accumulator. CFR <4> = 1. This bit automatically synchronously clears (loads 0s) the sweep accumulator for one cycle upon reception of the I/O_UPDATE sequence indicator. CFR <5> match pipe delays active. CFR <5> = 0 (default), match pipe delay mode is inactive. CFR <5> = 1, match pipe delay mode is active. See the Single- Tone Mode—Matched Pipeline Delay section for details. CFR <6> DAC power-down.

Rev. 0 | Page 40 of 44 CFR <6> = 0 (default). The DAC is enabled for operation. CFR <6> = 1. The DAC is disabled and held in its lowest power dissipation state. CFR <7> digital power-down. CFR <7> = 0 (default). The digital core is enabled for operation. CFR <7> = 1. The digital core is disabled and is in its lowest power dissipation state. CFR <9:8>. DAC LSB control (see Table 5). CFR <9:8> = 00 (default). CFR <10> must be cleared to 0. CFR <13> linear sweep ramp rate load at I/O_UPDATE. CFR <13> = 0 (default). The linear sweep ramp rate timer is loaded only upon timeout (timer = 1); it is not loaded by the I/O_UPDATE input signal. CFR <13> = 1. The linear sweep ramp rate timer is loaded upon timeout (timer = 1) or at the time of an I/O_UPDATE input signal. CFR <14> linear sweep enable. CFR <14> = 0 (default). The linear sweep capability of the AD9911 is inactive. CFR <14> = 1. The linear sweep capability of the AD9911 is active. The delta frequency tuning word is applied to the frequency accumulator at the programmed ramp rate. CFR <15> linear sweep no-dwell. CFR <15> = 0 (default). The linear sweep no-dwell function is inactive. CFR <15> = 1. The linear sweep no-dwell function is active. See the Linear Sweep (Shaped) Modulation Mode section for details. If CFR <14> is clear, this bit is ignored. CFR <18:16> Data align bits for SpurKiller mode. See the SpurKiller/Multitone Mode section for details. CFR <21:19> inactive. CFR <23:22> amplitude/frequency/phase select controls, the type of modulation is to be performed for that channel. See the Shift Keying Mode section for examples. Channel Frequency Tuning Word 0 (CFTW0) Description CFTW0 <32:0> Frequency Tuning Word 0 for each channel. Channel Phase Offset Word 0 (CPOW0) Description CPOW0 <13:0> Phase Offset Word 0 for each channel. CPOW0 <15:14> inactive. Amplitude Control Register (ACR) Description ACR <9:0> amplitude scale factor. ACR <10> amplitude ramp rate load control bit. ACR <10> = 0 (default). The amplitude ramp rate timer is loaded only upon timeout (timer = 1) and is not loaded by an I/O_UPDATE input signal (or change in the profile select bits). ACR <10> = 1. The amplitude ramp rate timer is loaded upon timeout (timer =1) or at the time of an I/O_UPDATE input signal (or change in profile select bits). ACR <11> auto RU/RD enable (only valid when ACR <12> is active high). ACR <11> = 0 (default). When ACR <12> is active, Logic 0 on ACR <11> enables the manual RU/RD operation. See the Output Amplitude Control section of this document for details. ACR <11> = 1. If ACR <12> is active, a Logic 1 on ACR <11> enables the AUTO RU/RD operation. See the Output Amplitude Control section for details. ACR <12> amplitude multiplier enable. ACR <12> = 0 (default). Amplitude multiplier is disabled. The associated clocks are stopped for power saving; the data from the DDS core is routed around the multipliers. ACR <12> = 1, amplitude multiplier is enabled. ACR <13> inactive. ACR <15:14> amplitude increment/decrement step size. See Table 20 for details. ACR <23:16> amplitude ramp rate value. Channel Linear Sweep Register (LSR) Description LSR <15:0> linear sweep rising ramp rate. Channel Linear Sweep Rising Delta Word Register (RDW) RDW <31:0> 32-bit rising delta tuning word. Channel Linear Sweep Falling Delta Word Register (FDW) Description FDW <31:0> 32-bit falling delta tuning word.

0.50 BSC

0.20 REF

0.65 TYP

0.60 MAX

0.60 MAX PIN 1

0.05 MAX

0.02 NOM

0.25 MIN

Figure 57. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 42 of 44 NOTES

Rev. 0 | Page 43 of 44 NOTES

Rev. 0 | Page 44 of 44 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05785-0-5/06(0)