AD9845AJST

AD9845A AD | Alldatasheet

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REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9845A Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 Complete 12-Bit 30 MSPS CCD Signal Processor FUNCTIONAL BLOCK DIAGRAM DATACLKSHDSHP BANDGAP REFERENCE 2:1 MUX DOUT AUX2IN CLPDM CCDIN OFFSET DAC PBLK AUX1IN VRT VRB INTERNAL TIMING INTERNAL BIAS 2dB~36dB AVDD DVDD DVSS AVSS DRVDD DRVSS CML DIGITAL INTERFACE SDATASCKSL CLPOB CDS VGA CLP BUF2:1 MUX CLP AD9845A CONTROL REGISTERS CLP ADC 4dB /H11550 6dB COLOR STEERING HD VD PxGA

FEATURES

30 MSPS Correlated Double Sampler (CDS)

4 dB /H11550 6 dB 6-Bit Pixel Gain Amplifier ( PxGA®) 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Analog Preblanking Function 12-Bit 30 MSPS A/D Converter Auxiliary Inputs with VGA and Input Clamp 3-Wire Serial Digital Interface

3 V Single Supply Operation

Low Power: 140 mW @ 3V Supply 48-Lead LQFP Package

APPLICATIONS

The AD9845A is a complete analog signal processor for CCD applications. It features a 30 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9845A’s signal chain consists of an input clamp, correlated double sampler (CDS), Pixel Gain Amplifier ( PxGA), digitally controlled variable gain amplifier (VGA), black level clamp, and a 12-bit A/D converter. Additional input modes are provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input configuration, and power-down modes. The AD9845A operates from a single 3 V power supply, typi- cally dissipates 140 mW, and is packaged in a 48-lead LQFP. PxGA is a registered trademark of Analog Devices, Inc.

REV. 0–2– AD9845A–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter Min Typ Max Unit TEMPERATURE RANGE Operating –20 +85 °C Storage –65 +150 °C POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver 2.7 3.6 V POWER CONSUMPTION Normal Operation (Specified Under Each Mode of Operation) Power-Down Modes Fast Recovery Mode 90 mW Standby 5 mW Total Power-Down 1 mW MAXIMUM CLOCK RATE 30 MHz A/D CONVERTER Resolution 12 Bits Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB No Missing Codes 12 Bits Guaranteed Full-Scale Input Voltage 2.0 V Data Output Coding Straight Binary VOLTAGE REFERENCE Reference Top Voltage (VRT) 2.0 V Reference Bottom Voltage (VRB) 1.0 V Specifications subject to change without notice. DIGITAL SPECIFICATIONS Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage V IH 2.1 V Low Level Input Voltage V IL 0.6 V High Level Input Current I IH 10 µA Low Level Input Current I IL 10 µA Input Capacitance C IN 10 pF LOGIC OUTPUTS High Level Output Voltage, I OH = 2 mA V OH 2.2 V Low Level Output Voltage, I OL = 2 mA V OL 0.5 V Specifications subject to change without notice. (DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.) (TMIN to TMAX, AVDD = DVDD = 3.0 V, f DATACLK = 30 MHz, unless otherwise noted.)

REV. 0 –3– AD9845A Parameter Min Typ Max Unit Notes POWER CONSUMPTION 140 mW See TPC 1 for Power Curves MAXIMUM CLOCK RATE 30 MHz CDS Gain 0 dB Allowable CCD Reset Transient 1 500 mV See Input Waveform in Footnote 1 Max Input Range Before Saturation 1 1.0 V p-p PxGA Gain at 4 dB Max CCD Black Pixel Amplitude 1 200 mV PIXEL GAIN AMPLIFIER ( PxGA) Max Input Range 1.0 V p-p Max Output Range 1.6 V p-p Gain Control Resolution 64 Steps Gain Monotonicity Guaranteed Gain Range (Two’s Complement Coding) See Figure 28 for PxGA Gain Curve Min Gain (PxGA Gain Code 32) –2 dB Max Gain (PxGA Gain Code 31) 10 dB VARIABLE GAIN AMPLIFIER (VGA) Max Input Range 1.6 V p-p Max Output Range 2.0 V p-p Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range See Figure 29 for VGA Gain Curve Low Gain (VGA Gain Code 91) 2 dB Max Gain (VGA Gain Code 1023) 36 dB BLACK LEVEL CLAMP Clamp Level Resolution 256 Steps Clamp Level Measured at ADC Output Min Clamp Level 0 LSB Max Clamp Level 255 LSB SYSTEM PERFORMANCE Specifications Include Entire Signal Chain Gain Accuracy (VGA Code 91 to 1023) 2 –0.5 +0.5 Use Equations on Page 18 to Calculate Gain PxGA Gain Accuracy Min Gain (PxGA Register Code 32) –1 0 +1 dB VGA Gain Fixed at 2 dB (Code 91) Max Gain (PxGA Code 31) 11 12 13 dB VGA Gain Fixed at 2 dB (Code 91) Peak Nonlinearity, 500 mV Input Signal 0.1 % 12 dB Gain Applied Total Output Noise 0.6 LSB rms AC Grounded Input, 6 dB Gain Applied Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply POWER-UP RECOVERY TIME Normal Clock Signals Applied Fast Recovery Mode 0.1 ms Reference Standby Mode 1 ms Total Shutdown Mode 3 ms Power-Off Condition 15 ms NOTES 1Input Signal Characteristics defined as follows: 200mV MAX OPTICAL BLACK PIXEL 500mV TYP RESET TRANSIENT 1V MAX INPUT SIGNAL RANGE 2PxGA gain fixed at 4 dB (Code 63). Specifications subject to change without notice. CCD-MODE SPECIFICATIONS(TMIN to TMAX, AVDD = DVDD = 3.0 V, f DATACLK = fSHP = fSHD = 30 MHz, unless otherwise noted.)

REV. 0–4– AD9845A–SPECIFICATIONS AUX1-MODE SPECIFICATIONS Parameter Min Typ Max Unit POWER CONSUMPTION 100 mW MAXIMUM CLOCK RATE 30 MHz INPUT BUFFER Gain 0d B Max Input Range 1.0 V p-p VGA Max Output Range 2.0 V p-p Gain Control Resolution 1023 Steps Gain (Selected Using VGA Gain Register) Min Gain 0 dB Max Gain 36 dB Specifications subject to change without notice. AUX2-MODE SPECIFICATIONS Parameter Min Typ Max Unit POWER CONSUMPTION 100 mW MAXIMUM CLOCK RATE 30 MHz INPUT BUFFER (Same as AUX1-MODE) VGA Max Output Range 2.0 V p-p Gain Control Resolution 512 Steps Gain (Selected Using VGA Gain Register) Min Gain 0 dB Max Gain 18 dB ACTIVE CLAMP Clamp Level Resolution 256 Steps Clamp Level (Measured at ADC Output) Min Clamp Level 0 LSB Max Clamp Level 255 LSB Specifications subject to change without notice. (TMIN to TMAX, AVDD = DVDD = 3.0 V, f DATACLK = 30 MHz, unless otherwise noted.) (TMIN to TMAX, AVDD = DVDD = 3.0 V, f DATACLK = 30 MHz, unless otherwise noted.)

REV. 0 AD9845A –5– TIMING SPECIFICATIONS Parameter Symbol Min Typ Max Unit SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period t CONV 32 33 ns DATACLK Hi/Low Pulsewidth t ADC 13 16.7 ns SHP Pulsewidth t SHP 5 8.3 ns SHD Pulsewidth t SHD 5 8.3 ns CLPDM Pulsewidth t CDM 4 10 Pixels CLPOB Pulsewidth1 tCOB 2 20 Pixels SHP Rising Edge to SHD Falling Edge t S1 0 8.3 ns SHP Rising Edge to SHD Rising Edge t S2 13 16.7 ns Internal Clock Delay t ID 3.0 ns Inhibited Clock Period t INH 10 ns DATA OUTPUTS Output Delay t OD 14.5 16 ns Output Hold Time t H 7.0 7.6 ns Pipeline Delay 9 Cycles SERIAL INTERFACE Maximum SCK Frequency f SCLK 10 MHz SL to SCK Setup Time t LS 10 ns SCK to SL Hold Time t LH 10 ns SDATA Valid to SCK Rising Edge Setup t DS 10 ns SCK Falling Edge to SDATA Valid Hold t DH 10 ns SCK Falling Edge to SDATA Valid Read t DV 10 ns NOTES 1Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp perf ormance. Specifications subject to change without notice. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9845A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE (CL = 20 pF, fSAMP = 30 MHz, CCD-Mode Timing in Figures 10 and 11, AUX-Mode Timing in Figure 7. Serial Timing in Figures 26 –29.) ABSOLUTE MAXIMUM RATINGS With Respect Parameter To Min Max Unit AVDD1, AVDD2 AVSS –0.3 +3.9 V DVDD1, DVDD2 DVSS –0.3 +3.9 V DRVDD DRVSS –0.3 +3.9 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V SHP, SHD, DATACLK DVSS –0.3 DVDD + 0.3 V CLPOB, CLPDM, PBLK DVSS –0.3 DVDD + 0.3 V SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V VRT, VRB, CMLEVEL AVSS –0.3 A VDD + 0.3 V BYP1-4, CCDIN AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 °C Lead Temperature 300 °C (10 sec) ORDERING GUIDE Temperature Package Package Model Range Description Option AD9845AJST –20°C to +85°C Thin Plastic ST-48 Quad Flatpack (LQFP) THERMAL CHARACTERISTICS Thermal Resistance 48-Lead LQFP Package θ JA = 92°C

REV. 0 AD9845A –6– PIN FUNCTION DESCRIPTIONS Pin Number Name Type Description 1–12 D0–D11 DO Digital Data Outputs

13 DRVDD P Digital Output Driver Supply

14 DRVSS P Digital Output Driver Ground

15, 41 DVSS P Digital Ground

16 DATACLK DI Digital Data Output Latch Clock

17 DVDD1 P Digital Supply

18 HD DI Horizontal Drive. Used with VD for Color Steering Control

19 PBLK DI Preblanking Clock Input

20 CLPOB DI Black Level Clamp Clock Input

21 SHP DI CDS Sampling Clock for CCD’s Reference Level

22 SHD DI CDS Sampling Clock for CCD’s Data Level

23 CLPDM DI Input Clamp Clock Input

24 VD DI Vertical Drive. Used with HD for Color Steering Control 25, 26, 35 AVSS P Analog Ground

27 AVDD1 P Analog Supply

28 BYP1 AO Internal Bias Level Decoupling

29 BYP2 AO Internal Bias Level Decoupling

30 CCDIN AI Analog Input for CCD Signal

31 NC NC Internally Not Connected

32 BYP4 AO Internal Bias Level Decoupling

33 AVDD2 P Analog Supply

34 AUX2IN AI Analog Input

36 AUX1IN AI Analog Input

37 CML AO Internal Bias Level Decoupling

38 VRT AO A/D Converter Top Reference Voltage Decoupling

39 VRB AO A/D Converter Bottom Reference Voltage Decoupling

40 DVDD2 P Digital Supply

42 THREE-STATE DI Digital Output Disable. Active High 43 NC NC May be tied high or low. Do not leave floating. 44 STBY DI Standby Mode, Active High. Same as Serial Interface 45 NC NC Internally Not Connected. May be Tied High or Low

46 SL DI Serial Digital Interface Load Pulse

47 SDATA DI Serial Digital Interface Data

48 SCK DI Serial Digital Interface Clock

TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power. PIN CONFIGURATIONS 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 39 38 3743 42 41 40 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) AUX1IN AVSS AUX2IN AVDD2 BYP4 NC CCDIN (LSB) D0 NC = NO CONNECT D10 BYP2 BYP1 AVDD1 AVSS AD9845A (MSB) D11 AVSS SCK SDATA SL NC STBY NC THREE-STATE DVSS DVDD2 VRB VRT CML DRVDD DRVSS DVSS DATACLK DVDD1 HD PBLK CLPOB SHP SHD CLPDM VD

REV. 0 AD9845A –8– –Typical Performance Characteristics SAMPLE RATE – MHz 160 130 100 10 30 20 POWER DISSIPATION – mW 110 120 140 150 VDD = 3.3V VDD = 3.0V VDD = 2.7V TPC 1. Power vs. Sample Rate 0 1000500 1500 2000 2500 3000 3500 4000 –0.5 0.5 –0.25 0.25 TPC 2. Typical DNL Performance VGA GAIN CODE – LSB 0 1000 400 OUTPUT NOISE – LSB 200 600 800 TPC 3. Output Noise vs. VGA Gain

Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence

1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.

5 PIXEL MIN

Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101.

Figure 11. PxGA Mode 2 (Interlace) Detailed Timing

Figure 12. PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 012012.

Figure 13. PxGA Mode 3 (3-Color) Detailed Timing Figure 14. PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 01230123.

Figure 15. PxGA Mode 4 (4-Color) Detailed Timing

Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101...

Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence

1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.

Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. VD = 0 AND HD = 0 SELECTS GAIN0.
3. VD = 0 AND HD = 1 SELECTS GAIN1.
4. VD = 1 AND HD = 0 SELECTS GAIN2.
5. VD = 1 AND HD = 1 SELECTS GAIN3.

Figure 20. PxGA Mode 7 (User-Specified) Detailed Timing

0 A2 0A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.

Figure 21. Serial Write Operation

1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON

Figure 22. Serial Readback Operation *Internal use only. Must be set to zero.

00 D9000 D0

10 BITS

1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.

8 BITS

11 BITS

6 BITS

Figure 23. Continuous Serial Write Operation to All Registers Figure 24. Continuous Serial Write Operation to All PxGA Gain Registers

1 Disable Clamping 1 Reset All Registers 0 1 Fast Recovery 0 1 AUX1 Mode

REV. 0 AD9845A –16– Table IV. Clamp Level Register Contents (Default Value x080) MSB LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Clamp Level (LSB) X X X 0000 0 000 0 0000 0 001 1 0000 0 010 2

• •
• •
• • 11111110 2 5 4 11111111 2 5 5 Table V. Control Register Contents (Default Value x000) Data Out DATACLK CLP/PBLK SHP/SHD PxGA Color Steering Modes D10 D9 D8 D7 D6 D5 D4 D3 ** D2 D1 D0 X 0 Enable 0 * 0* 0 Rising Edge Trigger 0 Active Low 0 Active Low 0 Disable 0 0 0 Steering Disabled

1 Three-State 1 Falling Edge Trigger 1 Active High 1 Active High 1 Enable 0 0 1 Mosaic Separate

1 1 1 User Specified *Must be set to zero. **When D3 = 0 ( PxGA disabled) the PxGA gain is fixed to 4 dB. Table VI. PxGA Gain Registers for Gain0, Gain1, Gain2, Gain3 (Default Value x000) MSB LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB) * XXXXX0 1 1111 +10.0 000000+ 4 . 3 111111+ 4 . 0 100000 –2.0 *Control Register Bit D3 must be set High ( PxGA Enable) to use the PxGA Gain Registers.

The AD9845A signal processing chain is shown in Figure 25. image from the raw CCD pixel data. signals is critical in achieving the best performance from the CCD. the internal circuitry when higher VGA gain settings are used. that the CLPDM pulse be used during valid CCD dark pixels. be a minimum of 4 pixels wide. values are switched according to the “Color Steering” circuitry. Figure 25. CCD-Mode Block Diagram

43 in the AD9845A will have no effect. ing is recommended to reduce digital code transition noise. put pins may also help reduce noise.

8 CLOCK

Figure 33. Recommended Circuit Configuration for CCD-Mode

REV. 0 AD9845A –22– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) TOP VIEW (PINS DOWN) 3748 0.019 (0.5) BSC 0.276 (7.00) BSC SQ 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) BSC SQ 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0/H11543 MIN COPLANARITY 0.003 (0.08) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 7/H11543 0/H11543 0.057 (1.45) 0.053 (1.35) PRINTED IN U.S.A.