AD9840AJSTZ

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9840A Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 Complete 10-Bit 40 MSPS CCD Signal Processor FUNCTIONAL BLOCK DIAGRAM DATACLKSHDSHP BANDGAP REFERENCE 2:1 MUX DOUT AUX2IN CLPDM CCDIN OFFSET DAC PBLK AUX1IN VRT VRB INTERNAL TIMING INTERNAL BIAS 2dB TO 36dB AVDD DVDD DVSS AVSS DRVDD DRVSS CML DIGITAL INTERFACE SDATASCKSL CLPOB CDS VGA CLP BUF2:1 MUX CLP AD9840A 4dB/H115506dB INTERNAL REGISTERS CLP 10-BIT ADC

FEATURES

40 MSPS Correlated Double Sampler (CDS)

4dB /H11550 6 dB Variable CDS Gain with 6-Bit Resolution 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Analog Preblanking Function 10-Bit 40 MSPS A/D Converter Auxiliary Inputs with VGA and Input Clamp 3-Wire Serial Digital Interface

3 V Single Supply Operation

Low Power: 155 mW @ 3.0 V Supply 48-Lead LQFP Package

APPLICATIONS

The AD9840A is a complete analog signal processor for CCD applications. It features a 40 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9840A’s signal chain consists of an input clamp, correlated double sampler (CDS), digitally controlled variable gain amplifier (VGA), black level clamp, and 10-bit A/D converter. Additional input modes are provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable feat ures include gain adjustment, black level adjustment, input configuration, and power-down modes. The AD9840A operates from a 3 V power supply, typically dissipates 155 mW, and is packaged in a 48-lead LQFP.

–2– REV. 0 AD9840A–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter Min Typ Max Unit TEMPERATURE RANGE Operating –20 +85 °C Storage –65 +150 °C POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver 2.7 3.6 V POWER CONSUMPTION Normal Operation (Specified Under Each Mode of Operation) Power-Down Modes Fast Recovery Mode 90 mW Standby 5 mW Total Power-Down 1 mW MAXIMUM CLOCK RATE 40 MHz A/D CONVERTER Resolution 10 Bits Differential Nonlinearity (DNL) ± 0.5 ± 1.0 LSB No Missing Codes 10 Bits Guaranteed Full-Scale Input Voltage 2.0 V Data Output Coding Straight Binary VOLTAGE REFERENCE Reference Top Voltage (VRT) 2.0 V Reference Bottom Voltage (VRB) 1.0 V Specifications subject to change without notice. DIGITAL SPECIFICATIONS Parameter Symbol Min Typ Max Unit LOGIC INPUTS High Level Input Voltage V IH 2.1 V Low Level Input Voltage V IL 0.6 V High Level Input Current I IH 10 µA Low Level Input Current I IL 10 µA Input Capacitance C IN 10 pF LOGIC OUTPUTS High Level Output Voltage, I OH = 2 mA V OH 2.2 V Low Level Output Voltage, I OL = 2 mA V OL 0.5 V Specifications subject to change without notice. (TMIN to TMAX, AVDD = DVDD = 3.0 V, f DATACLK = 40 MHz, unless otherwise noted.) (DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.)

–3–REV. 0 AD9840A Parameter Min Typ Max Unit Notes POWER CONSUMPTION 155 mW MAXIMUM CLOCK RATE 20 MHz CDS Allowable CCD Reset Transient 1 500 mV See Input Waveform in Note 1 Max CCD Black Pixel Amplitude 1 200 mV Max Input Range before Saturation 1 1.0 V p-p With 4 dB CDS Gain Max Input Range before Saturation 1.5 V p-p With –2 dB CDS Gain Max Input Range before Saturation 0.5 V p-p With 10 dB CDS Gain Max Output Range 1.6 V p-p At Any CDS Gain Setting Gain Resolution 64 Steps Gain Range (Two’s Complement Coding) See Figure 15 for CDS Gain Curve Min Gain (CDS Gain Register Code 32) –2 dB Medium Gain (CDS Gain Code 63) 4 dB 4 dB is Default with CDS Gain Disabled Max Gain (CDS Gain Code 31) 10 dB VARIABLE GAIN AMPLIFIER (VGA) Max Input Range 1.6 V p-p Max Output Range 2.0 V p-p Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range See Figure 13 for VGA Gain Curve Low Gain (VGA Register Code 91) 2 dB See Page 12 for Gain Equations Max Gain (VGA Code 1023) 36 dB BLACK LEVEL CLAMP Clamp Level Resolution 256 Steps Clamp Level Measured at ADC Output Min Clamp Level 0 LSB Max Clamp Level 63.75 LSB SYSTEM PERFORMANCE Specifications Include Entire Signal Chain Gain Accuracy, VGA Code 91 to 1023 –1.0 +1.0 dB Use Equations on Page 12 to Calculate Gain Peak Nonlinearity, 500 mV Input Signal 0.4 % 12 dB Gain Applied (4 dB CDS Gain) Total Output Noise 0.25 LSB rms AC Grounded Input, 6 dB Gain Applied Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply POWER-UP RECOVERY TIME Clocks Must Be Applied, as in Figures 8 and 9 From Fast Recovery Mode 0.1 ms From Reference Standby Mode 1 ms From Total Shutdown Mode 3 ms From Power-Off Condition 15 ms NOTES 1Input Signal Characteristics defined as follows, with 4 dB CDS gain: 1V MAX INPUT SIGNAL RANGE 200mV MAX OPTICAL BLACK PIXEL 500mV TYP RESET TRANSIENT Specifications subject to change without notice. CCD-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, f DATACLK = fSHP = fSHD = 40 MHz, unless otherwise noted.)

–4– REV. 0 AD9840A–SPECIFICATIONS AUX1-MODE SPECIFICATIONS Parameter Min Typ Max Unit POWER CONSUMPTION 105 mW MAXIMUM CLOCK RATE 40 MHz INPUT BUFFER Gain 0d B Max Input Range 1.0 V p-p VGA Max Output Range 2.0 V p-p Gain Control Resolution 1023 Steps Gain (Selected Using VGA Gain Register) Min Gain 0 dB Max Gain 36 dB Specifications subject to change without notice. AUX2-MODE SPECIFICATIONS Parameter Min Typ Max Unit POWER CONSUMPTION 105 mW MAXIMUM CLOCK RATE 40 MHz INPUT BUFFER (Same as AUX1-MODE) VGA Max Output Range 2.0 V p-p Gain Control Resolution 512 Steps Gain (Selected Using VGA Gain Register) Min Gain 0 dB Max Gain 18 dB ACTIVE CLAMP Clamp Level Resolution 256 Steps Clamp Level (Measured at ADC Output) Min Clamp Level 0 LSB Max Clamp Level 63.75 LSB Specification subject to change without notice. (TMIN to TMAX, AVDD = DVDD = 3.0 V, f DATACLK = 40 MHz, unless otherwise noted.) (TMIN to TMAX, AVDD = DVDD = 3.0 V, f DATACLK = 40 MHz, unless otherwise noted.)

–5–REV. 0 TIMING SPECIFICATIONS Parameter Symbol Min Typ Max Unit SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period t CP 25 ns DATACLK Hi/Low Pulsewidth t ADC 10 12.5 ns SHP Pulsewidth t SHP 56 n s SHD Pulsewidth t SHD 56 n s CLPDM Pulsewidth t CDM 4 10 Pixels CLPOB Pulsewidth1 tCOB 2 20 Pixels SHP Rising Edge to SHD Falling Edge t S1 06 n s SHP Rising Edge to SHD Rising Edge t S2 10 12.5 ns Internal Clock Delay t ID 3.0 ns Inhibited Clock Period t INH 10 ns DATA OUTPUTS Output Delay t OD 14.5 16 ns Output Hold Time t H 7.0 7.6 ns Pipeline Delay 9 Cycles SERIAL INTERFACE Maximum SCK Frequency f SCLK 10 MHz SL to SCK Setup Time t LS 10 ns SCK to SL Hold Time t LH 10 ns SDATA Valid to SCK Rising Edge Setup t DS 10 ns SCK Falling Edge to SDATA Valid Hold t DH 10 ns SCK Falling Edge to SDATA Valid Read t DV 10 ns NOTES 1Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp perf ormance. Specifications subject to change without notice. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9840A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. (CL = 20 pF, fSAMP = 40 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7. Serial Timing in Figures 8–10.) ABSOLUTE MAXIMUM RATINGS With Respect Parameter To Min Max Unit AVDD1, AVDD2 AVSS –0.3 +3.9 V DVDD1, DVDD2 DVSS –0.3 +3.9 V DRVDD DRVSS –0.3 +3.9 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V SHP, SHD, DATACLK DVSS –0.3 DVDD + 0.3 V CLPOB, CLPDM, PBLK DVSS –0.3 DVDD + 0.3 V SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V VRT, VRB, CMLEVEL AVSS –0.3 A VDD + 0.3 V BYP1-4, CCDIN AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 °C Lead Temperature 300 °C (10 sec) ORDERING GUIDE Temperature Package Package Model Range Description Option AD9840AJST –20 °C to +85°C Thin Plastic ST-48 Quad Flatpack (LQFP) THERMAL CHARACTERISTICS Thermal Resistance 48-Lead LQFP Package θJA = 92°C WARNING! ESD SENSITIVE DEVICE

–6– REV. 0 PIN CONFIGURATION 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 39 38 3743 42 41 40 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) AUX1IN AVSS AUX2IN AVDD2 BYP4 NC CCDIN DRVSS DRVSS (LSB) D0 NC = NO CONNECT BYP2 BYP1 AVDD1 AVSS AD9840A AVSS SCK SDATA SL NC STBY NC THREE-STATE DVSS DVDD2 VRB VRT CML DRVDD DRVSS DVSS DATACLK DVDD1 DVSS PBLK CLPOB SHP SHD CLPDM DVSS (MSB) D9 PIN FUNCTION DESCRIPTIONS Pin Number Name Type Description 1, 2 DRVSS P Digital Driver Ground 3–12 D0–D9 DO Digital Data Outputs

13 DRVDD P Digital Output Driver Supply

14 DRVSS P Digital Output Driver Ground

15, 18, 24, 41 DVSS P Digital Ground

16 DATACLK DI Digital Data Output Latch Clock

17 DVDD1 P Digital Supply

19 PBLK DI Preblanking Clock Input

20 CLPOB DI Black Level Clamp Clock Input

21 SHP DI CDS Sampling Clock for CCD’s Reference Level

22 SHD DI CDS Sampling Clock for CCD’s Data Level

23 CLPDM DI Input Clamp Clock Input

25, 26, 35 AVSS P Analog Ground

27 AVDD1 P Analog Supply

28 BYP1 AO Internal Bias Level. Decoupling

29 BYP2 AO Internal Bias Level Decoupling

30 CCDIN AI Analog Input for CCD Signal

31 NC NC Leave Floating or Decouple to Ground with 0.1 /H9262F

32 BYP4 AO Internal Bias Level Decoupling

33 AVDD2 P Analog Supply

34 AUX2IN AI Analog Input

36 AUX1IN AI Analog Input

37 CML AO Internal Bias Level Decoupling

38 VRT AO A/D Converter Top Reference Voltage Decoupling

39 VRB AO A/D Converter Bottom Reference Voltage Decoupling

40 DVDD2 P Digital Supply

42 THREE-STATE DI Digital Output Disable. Active High 43 NC NC May be tied High or Low. Should not be left floating. 44 STBY DI Standby Mode, Active High. Same as Serial Interface Standby Mode 45 NC NC Internally Not Connected. May be tied high or low

46 SL DI Serial Digital Interface Load Pulse

47 SDATA DI Serial Digital Interface Data

48 SCK DI Serial Digital Interface Clock

TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.

*Internal use only, must be set to zero. **Should be set to one.

0 A2 0A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BIT = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.

Figure 8. Serial Write Operation

10 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK

Figure 9. Serial Readback Operation

00 D9000 D0

10 BITS

1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.

8 BITS

11 BITS

Figure 10. Continuous Serial Write Operation to Multiple Registers

–10– REV. 0 Table II. Operation Register Contents (Default Value x000) Optical Black Clamp Reset Power-Down Modes Channel Selection D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0* 0* 0* 1** 0* 0 Enable Clamping 0 Normal 0 0 Normal Power 0 0 CCD-Mode

1 Disable Clamping 1 Reset all 0 1 Fast Recovery 0 1 AUX1-Mode

Registers 1 0 Standby 1 0 AUX2-Mode to Default 1 1 Total Power-Down 1 1 Test Only *Must be set to zero. **Set to one. Table III. VGA Gain Register Contents (Default Value x096) MSB LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB) X 0 0 010111112 . 0 1 1 11111110 35.965 1 1 11111111 36.0 Table IV. Clamp Level Register Contents (Default Value x080) MSB LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Clamp Level (LSB) X X X 0000 0 000 0 0000 0 001 0.25 0000 0 010 0 . 5 11111110 63.5 11111111 63.75 Table V. Control Register Contents (Default Value x000) Data Out DATACLK CLP/PBLK SHP/SHD CDS Gain D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X 0 Enable 0 * 0* 0 Rising Edge Trigger 0 Active Low 0 Active Low 0 Disabled ** 0* 0* 0*

1 Three-State 1 Falling Edge Trigger 1 Active High 1 Active High 1 Enabled

*Must be set to zero. **When D3 = 0 (CDS Gain Disabled), the CDS Gain Register is fixed at 4 dB (code 63 dec). Table VI. CDS Gain Register Contents (Default Value x000) MSB LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB) * X X XX X 000000 +4.3

• •
• •
• • 011110 +10.0 100000– 2 . 0
• •
• •
• • 111111+ 4 . 0 *Control Register Bit D3 must be set high for the CDS Gain Register to be used.

0 TO 64 LSB

Figure 11. CCD-Mode Block Diagram The AD9840A signal processing chain is shown in Figure 11. image from the raw CCD pixel data. signals is critical in achieving the best performance from the CCD. 4 dB. See Tables V and VI for more details. AD9840A to accept CCD signal swings greater than 1 V p-p. CDS output level from exceeding 1.5 V–1.6 V.

1 V p-p 2 dB to 4 dB 53 to 63

1.25 V p-p 0 dB to 2 dB

1.5 V p-p –2 dB to 0 dB 32 to 42

Figure 12. CDS Gain Curve in the internal circuitry when higher VGA gain settings are used. that the CLPDM pulse be used during valid CCD dark pixels.

be a minimum of four pixels wide. mable with 10-bit resolution through the serial digital interface. will match a 1 V input signal with the ADC full-scale range of 2 V. the equivalent gain range is 0 dB to 34 dB.

1. The Gain Accuracy specifications also include a CDS gain

of 4 dB, for a total gain range of 6 dB to 40 dB. Figure 13. VGA Gain Curve (Gain from CDS Not Included) loop can be updated more slowly to suit a particular application. programm able offset adjustment. track low-frequency variations in the black level will be reduced. earity (DNL) performance is typically better than 0.5 LSB. using a larger ADC full-scale range. mately 0.4 V, which is referenced to the midscale code of the ADC. in this mode of operation (see VGA Gain Curve, Figure 13). will be further decreased to a lower ADC code.

6 CLOCK

Figure 17. Recommended Circuit Configuration for CCD-Mode

–16– PRINTED IN U.S.A. AD9840A REV. 0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) TOP VIEW (PINS DOWN) 3748 0.019 (0.5) BSC 0.276 (7.00) BSC SQ 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) BSC SQ 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0/H11543 MIN COPLANARITY 0.003 (0.08) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 7/H11543 0/H11543 0.057 (1.45) 0.053 (1.35)