AD9837ACPZ-RL7

AD9837 AD | Alldatasheet

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Low Power, 8.5 mW, 2.3 V to 5.5 V, Programmable Waveform Generator AD9837 Rev. 0 Informatio responsibi rights of th license is g Trademar U.S.A. .com served. n furnished by Analog Devices is believed to be accurate and reliable. However, no lity is assumed by Analog Devices for its use, nor for any infringements of patents or other ird parties that may result from its use. Specifications subject to change without notice. No ranted by implication or otherwise under any patent or patent rights of Analog Devices. ks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, Tel: 781.329.4700 www.analog Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights re

FEATURES

Digitally programmable frequency and phase 8.5 mW power consumption at 2.3 V MCLK speed: 16 MHz (B grade), 5 MHz (A grade) 28-bit resolution: 0.06 Hz at 16 MHz reference clock Sinusoidal, triangular, and square wave outputs 2.3 V to 5.5 V power supply 3-wire SPI interface Extended temperature range: −40°C to +125°C Power-down option 10-lead LFCSP

APPLICATIONS

Frequency stimulus/waveform generation Liquid and gas flow measurement Sensory applications: proximity, motion, and defect detection Line loss/attenuation Test and medical equipment Sweep/clock generators Time domain reflectometry (TDR) applications GENERAL DESCRIPTION The AD9837 is a low power, programmable waveform generator capable of producing sine, triangular, and square wave outputs. Waveform generation is required in various types of sensing, actuation, and time domain reflectometry (TDR) applications. The output frequency and phase are software programmable, allowing easy tuning. The frequency registers are 28 bits wide: with a 16 MHz clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz clock rate, the AD9837 can be tuned to 0.02 Hz resolution. The AD9837 is written to via a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V . The AD9837 has a power-down (sleep) function. Sections of the device that are not being used can be powered down to minimize the current consumption of the part. For example, the DAC can be powered down when a clock output is being generated. The AD9837 is available in a 10-lead LFCSP_WD package. FUNCTIONAL BLOCK DIAGRAM SERIAL INTERFACE AND CONTROL LOGIC SCLK SDATAFSYNC 16-BIT CONTROL REGISTER 12-BIT PHASE1 REG 12-BIT PHASE0 REG MUX SIN ROM 10-BIT DACMUX ON-BOARD REFERENCE AGND DGND VDD PHASE ACCUMULATOR (28-BIT) REGULATOR CAP/2.5V 2.5V AVDD/ DVDD MUXDIVIDE BY 2 MSB MUX FULL-SCALE CONTROL AD9837 COMP VOUT R 200Ω MCLK 28-BIT FREQ1 REG 28-BIT FREQ0 REG 09070-001 Figure 1.

Rev. 0 | Page 2 of 28 TABLE OF CONTENTS Numerically Controlled Oscillator Plus Phase Modulator ... 12

REVISION HISTORY

4/11—Revision 0: Initial Version

Rev. 0 | Page 3 of 28 SPECIFICATIONS VDD = 2.3 V to 5.5 V , AGND = DGND = 0 V , TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 Min Typ Max Unit Test Conditions/Comments SIGNAL DAC SPECIFICATIONS Resolution 10 Bits Update Rate A Grade 5 MSPS B Grade 16 MSPS VOUT Maximum 0.645 V VOUT Minimum 37 mV Vp-p 0.610 V VOUT TC 200 ppm/°C DC Accuracy Integral Nonlinearity (INL) ±1.0 LSB Differential Nonlinearity (DNL) ±0.5 LSB DDS SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio (SNR) A Grade −64 dB fMCLK = 5 MHz, fOUT = fMCLK/4096 B Grade −64 dB fMCLK = 16 MHz, fOUT = fMCLK/4096 Total Harmonic Distortion (THD) A Grade −68 dBc fMCLK = 5 MHz, fOUT = fMCLK/4096 B Grade −68 dBc fMCLK = 16 MHz, fOUT = fMCLK/4096 Spurious-Free Dynamic Range (SFDR) Wideband (0 to Nyquist) A Grade −65 dBc fMCLK = 5 MHz, fOUT = fMCLK/50 B Grade −65 dBc fMCLK = 16 MHz, fOUT = fMCLK/50 Narrow-Band (±200 kHz) A Grade −94 dBc fMCLK = 5 MHz, fOUT = fMCLK/50 B Grade −97 dBc fMCLK = 16 MHz, fOUT = fMCLK/50 Clock Feedthrough −67 dBc Wake-Up Time 1 ms LOGIC INPUTS Input High Voltage, VINH 1.7 V 2.3 V to 2.7 V power supply 2.0 V 2.7 V to 3.6 V power supply 2.8 V 4.5 V to 5.5 V power supply Input Low Voltage, VINL 0.5 V 2.3 V to 2.7 V power supply 0.7 V 2.7 V to 3.6 V power supply 0.8 V 4.5 V to 5.5 V power supply Input Current, IINH/IINL 10 mA Input Capacitance, CIN 3 pF POWER SUPPLIES fMCLK = 16 MHz, fOUT = fMCLK/4096 VDD 2.3 5.5 V IDD A Grade 3.7 5.0 mA IDD code dependent; see Figure 6 B Grade 4.5 5.5 mA IDD code dependent; see Figure 7 Low Power Sleep Mode 0.5 0.8 mA DAC powered down (SLEEP1 and SLEEP12 bits = 11; see Table 15) 1 Operating temperature range is −40°C to +125°C; typical specifications are at 25°C.

TA = 25°C, unless otherwise noted. soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance

Figure 4. Pin Configuration Table 5. Pin Function Descriptions 1 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage. be connected between VDD and AGND. VDD to bypass the on-board regulator. output frequency accuracy and phase noise are determined by this clock. 6 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input. 7 SCLK Serial Clock Input. Data is clocked into the AD9837 on each falling edge of SCLK. low, the internal logic is informed that a new word is being loaded into the device. resistor is not required because the device has a 200 Ω resistor on board. EP Exposed Pad. Connect the exposed pad to ground.

Figure 17. Test Circuit Used to Test Specifications

Rev. 0 | Page 10 of 28 TERMINOLOGY Integral Nonlinearity (INL) Total Harmonic Distortion (THD) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 … 00 to 000 … 01), and full scale, a point 0.5 LSB above the last code transition (111 … 10 to 111 … 11). The error is expressed in LSBs. T otal harmonic distortion (THD) is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9837, THD is defined as log 20 V V V V V VTHD + + + += Differential Nonlinearity (DNL) where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics. DNL is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified DNL of ±1 LSB maximum ensures monotonicity. Output Compliance Signal-to-Noise Ratio (SNR) Output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compli- ance are generated, the AD9837 may not meet the specifications listed in the data sheet. SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels. Clock Feedthrough There is feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the output spectrum of the AD9837. Spurious-Free Dynamic Range (SFDR) Along with the frequency of interest, harmonics of the funda- mental frequency and images of these frequencies are present at the output of a DDS device. The spurious-free dynamic range (SFDR) refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest spur or harmonic relative to the magnitude of the fundamental frequency in the 0 to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz about the fundamental frequency.

Rev. 0 | Page 12 of 28 CIRCUIT DESCRIPTION The AD9837 is a fully integrated direct digital synthesis (DDS) chip. The chip requires a reference clock and decoupling capa- citors to provide digitally created sine waves up to 8 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain, allowing accurate and simple realization of complex modulation algorithms using DSP techniques. The internal circuitry of the AD9837 consists of the following main sections: a numerically controlled oscillator (NCO), frequency and phase modulators, SIN ROM, a digital-to-analog converter, and a regulator. NUMERICALLY CONTROLLED OSCILLATOR PLUS PHASE MODULATOR The AD9837 consists of two frequency select registers, a phase accumulator, two phase offset registers, and a phase offset adder. The main component of the NCO is a 28-bit phase accumulator. Continuous time signals have a phase range of 0 to 2π. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9837 is implemented with 28 bits. Therefore, in the AD9837, 2π = 2 28. Likewise, the ΔPhase term is scaled into this range of numbers: 0 < ΔPhase < 228 − 1 With these substitutions, Equation 3 becomes f = ΔPhase × fMCLK∕228 (4) where 0 < ΔPhase < 228 − 1. The input to the phase accumulator can be selected from either the FREQ0 register or the FREQ1 register and is controlled by the FSEL bit in the control register. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit phase registers. The contents of one of these phase registers is added to the MSBs of the NCO. The AD9837 has two phase registers; their resolution is 2π/4096. SIN ROM To make the output from the NCO useful, it must be converted from phase information into a sinusoidal value. Because phase information maps directly to amplitude, the SIN ROM uses the digital phase information as an address to a lookup table and converts the phase information into amplitude. Although the NCO contains a 28-bit phase accumulator, the out- put of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary because a lookup table of 2 28 entries would be required. It is only necessary to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bit DAC. Therefore, the SIN ROM must have two bits of phase resolution more than the 10-bit DAC. The SIN ROM is enabled using the MODE bit (Bit D1) in the control register (see Table 16). DIGITAL-TO-ANALOG CONVERTER (DAC) The AD9837 includes a high impedance, current source, 10-bit DAC. The DAC receives the digital words from the SIN ROM and converts them into the corresponding analog voltages. The DAC is configured for single-ended operation. An external load resistor is not required because the device has an on-board 200 Ω resistor. The DAC generates an output voltage of 0.6 V p-p typical. REGULATOR VDD provides the power supply required for the analog section and the digital section of the AD9837. This supply can have a value of 2.3 V to 5.5 V . The internal digital section of the AD9837 is operated at 2.5 V . An on-board regulator steps down the voltage applied at VDD to 2.5 V . When the applied voltage at the VDD pin of the AD9837 is less than or equal to 2.7 V , the CAP/2.5V and VDD pins should be tied together to bypass the on-board regulator.

Table 7. Control Register Bit Descriptions D13 B28 Two write operations are required to load a complete word into either of the frequency registers. to execute consecutive 28-bit writes, you must alternate between the frequency registers. address. Bit D12 (HLB) informs the AD9837 whether the bits to be altered are the 14 MSBs or the 14 LSBs. frequency word separately. When Bit D13 (B28) is set to 1, the HLB bit is ignored. HLB = 1 allows a write to the 14 MSBs of the addressed frequency register. HLB = 0 allows a write to the 14 LSBs of the addressed frequency register. D11 FSEL The FSEL bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator (see Table 8). phase accumulator (see Table 8). D9 Reserved This bit should be set to 0. D8 RESET This bit controls the reset function. RESET = 1 resets internal registers to 0, which corresponds to an analog output of midscale. RESET = 0 disables the reset function (see the Reset Function section). D7 SLEEP1 This bit enables or disables the internal MCLK. SLEEP1 = 0 enables the internal MCLK (see the Sleep Function section). D6 SLEEP12 This bit powers down the on-chip DAC. SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9837 is used to output the MSB of the DAC data. SLEEP12 = 0 implies that the DAC is active (see the Sleep Function section). D5 OPBITEN This bit, in association with the MODE bit (Bit D1), controls the output at the VOUT pin (see Table 16). controls whether the VOUT pin outputs the MSB or the MSB/2. D4 Reserved This bit must be set to 0. D3 DIV2 DIV2 is used in association with Bit D5 (OPBITEN). See Table 16. DIV2 = 1 causes the MSB of the DAC data to be output at the VOUT pin. DIV2 = 0 causes the MSB/2 of the DAC data to be output at the VOUT pin. D2 Reserved This bit must be set to 0. connected to VOUT. This bit should be set to 0 if the OPBITEN bit is set to 1 (see Table 16). MODE = 1 bypasses the SIN ROM, resulting in a triangle output from the DAC. D0 Reserved This bit must be set to 0.

registers, which are described in Table 8. Table 8. Frequency and Phase Registers FREQ0 28 bits Frequency Register 0. as a fraction of the MCLK frequency. FREQ1 28 bits Frequency Register 1. as a fraction of the MCLK frequency. PHASE0 12 bits Phase Offset Register 0. output of the phase accumulator. PHASE1 12 bits Phase Offset Register 1. output of the phase accumulator. frequency and phase registers of the AD9837. Table 9. Frequency Register Bits to 1. An example of a 28-bit write is shown in Table 10. Table 10. Writing 0xFFFC000 to the FREQ0 Register mended that users alternate between the two frequency registers.

14 MSBs of the frequency word can be altered independently

Table 11. Writing 0x3FFF to the 14 LSBs of the FREQ1 Register Table 12. Writing 0x00FF to the 14 MSBs of the FREQ0 Register

1. Bit D13 identifies the phase register that is being loaded.

Table 13. Phase Register Bits

available from the AD9837 (see Table 16). AD9837 section). To reset the AD9837, set the RESET bit to 1. Table 16. Outputs from the VOUT Pin

0 No reset applied

1 Internal registers reset

the frequency of this output from the VOUT pin. function are shown in Table 15. Table 15. Applying the Sleep Function using the SLEEP12 bit to reduce power consumption. can be written to the part when the SLEEP1 control bit is active. the control bits. Setting the SLEEP1 bit to 0 enables the MCLK. Figure 21. Triangle Output until the part is ready to begin generating an output. A reset does not reset the phase, frequency, or control registers.

Figure 24. Flowchart for Data Writes

Figure 30. Evaluation Board Schematic

Figure 31. SDP Connector Schematic

Figure 32. Evaluation Board Layout

0.20 REF

0.05 MAX

0.02 NOM

0.50 BSC

Figure 33. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 2 The evaluation board for the AD9837 requires the system demonstration platform (SDP) board, which is sold separately.

Rev. 0 | Page 26 of 28 NOTES

Rev. 0 | Page 27 of 28 NOTES

Rev. 0 | Page 28 of 28 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D09070-0-4/11(0)