AD9834BRUZ-REEL7

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20 mW Power, 2.3 V to 5.5 V,

75 MHz Complete DDS

Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2003–2011 Analog Devices, Inc. All rights reserved.

FEATURES

Narrow-band SFDR >72 dB 2.3 V to 5.5 V power supply Output frequency up to 37.5 MHz Sine output/triangular output On-board comparator 3-wire SPI® interface Extended temperature range: −40°C to +105°C Power-down option 20 mW power consumption at 3 V 20-lead TSSOP

APPLICATIONS

Frequency stimulus/waveform generation Frequency phase tuning and modulation Low power RF/communications systems Liquid and gas flow measurement Sensory applications: proximity, motion, and defect detection Test and medical equipment GENERAL DESCRIPTION The AD9834 is a 75 MHz low power DDS device capable of producing high performance sine and triangular outputs. It also has an on-board comparator that allows a square wave to be produced for clock generation. Consuming only 20 mW of power at 3 V makes the AD9834 an ideal candidate for power-sensitive applications. Capability for phase modulation and frequency modulation is provided. The frequency registers are 28 bits; with a 75 MHz clock rate, resolution of 0.28 Hz can be achieved. Similarly, with a 1 MHz clock rate, the AD9834 can be tuned to 0.004 Hz resolution. Frequency and phase modulation are affected by loading registers through the serial interface and toggling the registers using software or the FSELECT pin and PSELECT pin, respectively. The AD9834 is written to using a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V . The analog and digital sections are independent and can be run from different power supplies, for example, AVDD can equal 5 V with DVDD equal to 3 V . The AD9834 has a power-down pin (SLEEP) that allows external control of the power-down mode. Sections of the device that are not being used can be powered down to minimize the current consumption. For example, the DAC can be powered down when a clock output is being generated. The part is available in a 20-lead TSSOP . FUNCTIONAL BLOCK DIAGRAM ΣMUX MUX COMPARATOR MSB CAP/2.5VDVDDAGNDAVDD MCLK AD9834 FSYNC SCLK SDATA COMP IOUT IOUTB DGND REGULATOR REFOUT FS ADJUST VIN FSELECT 12-BIT PHASE0 REG 12-BIT PHASE1 REG SLEEP RESETPSELECT MUX MUX MUX SIGN BIT OUT VCC 2.5V ON-BOARD REFERENCE 16-BIT CONTROL REGISTER FULL-SCALE CONTROL 10-BIT DAC DIVIDED BY 2 SIN ROM PHASE ACCUMULATOR (28-BIT) 28-BIT FREQ0 REG 28-BIT FREQ1 REG SERIAL INTERFACE AND CONTROL LOGIC 02705-001 Figure 1.

Rev. C | Page 2 of 36 TABLE OF CONTENTS Numerically Controlled Oscillator Plus Phase Modulator ... 16

Rev. C | Page 3 of 36

REVISION HISTORY

2/11—Rev. B to Rev. C Deleted Using the AD9834 Evaluation Board Section and the Added System Development Platform Section, AD9834 to SPORT Interface Section, Figure 39, and Figure 40; Changes to XO vs. External Clock Section and Power Supply Deleted Bill of Materials, Table 19; Added Evaluation Board Schematics Section and Figure 41 ....30 4/10—Rev. A to Rev. B 8/06—Rev. 0 to Rev. A Added Figure 16 and Figure 17, Figures Renumbered 2/03—Revision 0: Initial Version

Rev. C | Page 4 of 36 SPECIFICATIONS VDD = 2.3 V to 5.5 V , AGND = DGND = 0 V , TA = TMIN to TMAX, RSET = 6.8 kΩ, RLOAD = 200 Ω for IOUT and IOUTB, unless otherwise noted. Table 1. Grade B, Grade C1 Parameter2 Min Typ Max Unit Test Conditions/Comments SIGNAL DAC SPECIFICATIONS Resolution 10 Bits Update Rate 75 MSPS IOUT Full Scale3 3.0 mA VOUT Max 0.6 V VOUT Min 30 mV Output Compliance4 0.8 V DC Accuracy Integral Nonlinearity ±1 LSB Differential Nonlinearity ±0.5 LSB DDS SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio 55 60 dB fMCLK = 75 MHz, fOUT = fMCLK/4096 Total Harmonic Distortion −66 −56 dBc fMCLK = 75 MHz, fOUT = fMCLK/4096 Spurious-Free Dynamic Range (SFDR) Wideband (0 to Nyquist) −60 −56 dBc fMCLK = 75 MHz, fOUT = fMCLK/75 Narrow Band (±200 kHz) B Grade −78 −67 dBc fMCLK = 50 MHz, fOUT = fMCLK/50 C Grade −74 −65 dBc fMCLK = 75 MHz, fOUT = fMCLK/75 Clock Feedthrough −50 dBc Wake-Up Time 1 ms COMPARATOR Input Voltage Range 1 V p-p AC-coupled internally Input Capacitance 10 pF Input High-Pass Cutoff Frequency 4 MHz Input DC Resistance 5 MΩ Input Leakage Current 10 μA OUTPUT BUFFER Output Rise/Fall Time 12 ns Using a 15 pF load Output Jitter 120 ps rms 3 MHz sine wave, 0.6 V p-p VOLTAGE REFERENCE Internal Reference 1.12 1.18 1.24 V REFOUT Output Impedance5 1 kΩ Reference Temperature Coefficient 100 ppm/°C LOGIC INPUTS Input High Voltage, VINH 1.7 V 2.3 V to 2.7 V power supply 2.0 V 2.7 V to 3.6 V power supply 2.8 V 4.5 V to 5.5 V power supply Input Low Voltage, VINL 0.6 V 2.3 V to 2.7 V power supply 0.7 V 2.7 V to 3.6 V power supply 0.8 V 4.5 V to 5.5 V power supply Input Current, IINH/IINL 10 μA Input Capacitance, CIN 3 pF

1 B grade: MCLK = 50 MHz; C grade: MCLK = 75 MHz. For specifications that do not specify a grade, the value applies to both grades. 2 Operating temperature range is as follows: B, C versions: −40°C to +105°C, typical specifications are at 25°C. 3 For compliance, with specified load of 200 Ω, IOUT full scale should not exceed 4 mA. 5 Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current. 6 Measured with the digital inputs static and equal to 0 V or DVDD. Figure 2. Test Circuit Used to Test the Specifications

Rev. C | Page 7 of 36 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Ratings AVDD to AGND −0.3 V to +6 V DVDD to DGND −0.3 V to +6 V AVDD to DVDD −0.3 V to +0.3 V AGND to DGND −0.3 V to +0.3 V CAP/2.5V 2.75 V Digital I/O Voltage to DGND −0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND −0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C θJA Thermal Impedance 143°C/W θJC Thermal Impedance 45°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature 220°C Reflow Soldering (Pb-Free) Peak Temperature 260°C (+0/–5) Time at Peak Temperature 10 sec to 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 6. Pin Configuration Table 4. Pin Function Descriptions FSADJUST = 1.15 V nominal, RSET = 6.8 kΩ typical. 2 REFOUT Voltage Reference Output. The AD9834 has an internal 1.20 V reference that is made available at this pin. 3 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage. OPBITEN and Bit SIGN/PIB in the control register are set to 1, the comparator input is connected to VIN. it can be tied directly to AGND. A 20 pF capacitor to AGND is also recommended to prevent clock feedthrough. capacitor should be connected between AVDD and AGND. capacitor should be connected between DVDD and DGND. output frequency accuracy and phase noise are determined by this clock. used to select the frequency register, the FSELECT pin should be tied to CMOS high or low. controlled by Bit PSEL, the PSELECT pin should be tied to CMOS high or low. of midscale. RESET does not affect any of the addressable registers.

Rev. C | Page 9 of 36 Pin No. Mnemonic Description 13 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input. 14 SCLK Serial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge. 15 FSYNC Active Low Control Input. This is the frame synchronization signal for the input data. When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device.

16 SIGN BIT

Logic Output. The comparator output is available on this pin or, alternatively, the MSB from the NCO can be output on this pin. Setting Bit OPBITEN in the control register to 1 enables this output pin. Bit SIGN/PIB determines whether the comparator output or the MSB from the NCO is output on the pin.

Rev. C | Page 14 of 36 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB scale, a point 0.5 LSB above the last code transition (111 . . . 10 to Differential Nonlinearity (DNL) DNL is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified DNL of ±1 LSB maximum ensures monotonicity. Output Compliance The output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output com- pliance are generated, the AD9834 may not meet the specifications listed in the data sheet. Spurious-Free Dynamic Range (SFDR) Along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a DDS device. The SFDR refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz about the fundamental frequency. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9834, THD is defined as 6 5 4 3 2 V V V V V VTHD 2 2 2 2 2 log 20 + + + += where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second harmonic through the sixth harmonic. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels. Clock Feedthrough There is feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the output spectrum of the AD9834.

Figure 27. Sine Wave subcircuits is discussed in the Circuit Description section.

Rev. C | Page 16 of 36 CIRCUIT DESCRIPTION The AD9834 is a fully integrated direct digital synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor, and eight decoupling capacitors to provide digitally created sine waves up to 37.5 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain, allowing accurate and simple realization of complex modulation algorithms using DSP techniques. The internal circuitry of the AD9834 consists of the following main sections: a numerically controlled oscillator (NCO), frequency and phase modulators, SIN ROM, a DAC, a comparator, and a regulator. NUMERICALLY CONTROLLED OSCILLATOR PLUS PHASE MODULATOR This consists of two frequency select registers, a phase accumulator, two phase offset registers, and a phase offset adder. The main component of the NCO is a 28-bit phase accumulator. Continuous time signals have a phase range of 0 π to 2π. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9834 is implemented with 28 bits. Therefore, in the AD9834, 2π = 2 28. Likewise, the ΔPhase term is scaled into this range of numbers: 0 < ΔPhase < 228 − 1. Making these substitutions into the previous equation f = ΔPhase × fMCLK/228 where 0 < ΔPhase < 228 − 1. The input to the phase accumulator can be selected either from the FREQ0 register or FREQ1 register and is controlled by the FSELECT pin or the FSEL bit. NCOs inherently generate con- tinuous phase signals, thus avoiding any output discontinuity when switching between frequencies. Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit phase registers. The contents of one of these phase registers is added to the MSBs of the NCO. The AD9834 has two phase registers, the resolution of these registers being 2π/4096. SIN ROM To make the output from the NCO useful, it must be converted from phase information into a sinusoidal value. Phase informa- tion maps directly into amplitude; therefore, the SIN ROM uses the digital phase information as an address to a look-up table and converts the phase information into amplitude. Although the NCO contains a 28-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolu- tion of the phase accumulator is impractical and unnecessary because it requires a look-up table of 2 28 entries. It is necessary only to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bit DAC. This requires the SIN ROM to have two bits of phase resolution more than the 10-bit DAC. The SIN ROM is enabled using the OPBITEN and MODE bits in the control register. This is explained further in Table 18. DIGITAL-TO-ANALOG CONVERTER (DAC) The AD9834 includes a high impedance current source 10-bit DAC capable of driving a wide range of loads. The full-scale output current can be adjusted for optimum power and external load requirements using a single external resistor (RSET). The DAC can be configured for either single-ended or differential operation. IOUT and IOUTB can be connected through equal external resistors to AGND to develop complementary output voltages. The load resistors can be any value required, as long as the full-scale voltage developed across it does not exceed the voltage compliance range. Because full-scale current is controlled by RSET, adjustments to RSET can balance changes made to the load resistors. COMPARATOR The AD9834 can be used to generate synthesized digital clock signals. This is accomplished by using the on-board self-biasing comparator that converts the sinusoidal signal of the DAC to a square wave. The output from the DAC can be filtered externally before being applied to the comparator input. The comparator reference voltage is the time average of the signal applied to V IN. The comparator can accept signals in the range of approximately 100 mV p-p to 1 V p-p. As the comparator input is ac-coupled, to operate correctly as a zero crossing detector, it requires a minimum input frequency of typically 3 MHz. The comparator output is a square wave with an amplitude from 0 V to DVDD.

sampled spectrum, with aliased images, is shown in Figure 28. can be operated at 3 V , or vice versa. The internal digital section of the AD9834 is operated at 2.5 V . within the AD9834 to make them 2.5 V compatible. be tied together, thus bypassing the on-board regulator. guaranteed with an RSET of 6.8 kΩ and an RLOAD of 200 Ω. Figure 28. The DAC Output Spectrum

for this operation is given in Figure 5. AD9834 devices, refer to the AN-1070 Application Note.

16 SCLK pulses and then brought high at the end of the data

after the 16th SCLK falling edge of the last word is loaded. DAC output eight MCLK cycles after RESET is set to 0. rising edge when the data is loaded into the destination register. also have a latency associated with them. MODE, are sampled on the internal negative edge of MCLK. Table 5. Control Register

Figure 29. Function of Control Bits Table 6. Description of Bits in the Control Register DB13 B28 Two write operations are required to load a complete word into either of the frequency registers. Control Bit DB12 (HLB) informs the AD9834 whether the bits to be altered are the 14 MSBs or 14 LSBs. frequency register. DB13 (B28) must be set to 0 to be able to change the MSBs and LSBs of a frequency word separately. When DB13 (B28) = 1, this control bit is ignored. HLB = 1 allows a write to the 14 MSBs of the addressed frequency register. HLB = 0 allows a write to the 14 LSBs of the addressed frequency register. select a frequency register. accumulator. See Table 9 to select a phase register. implemented using either software or hardware. PIN/SW selects the source of control for these functions. PIN/SW = 1 implies that the functions are being controlled using the appropriate control pins. PIN/SW = 0 implies that the functions are being controlled using the appropriate control bits. DB8 RESET RESET = 1 resets internal registers to 0, this corresponds to an analog output of midscale. RESET = 0 disables RESET. This function is explained in the RESET Function section. SLEEP1 = 0, MCLK is enabled. This function is explained in the SLEEP Function section. DB6 SLEEP12 SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9834 is used to output the MSB of the DAC data. SLEEP12 = 0 implies that the DAC is active. This function is explained in the SLEEP Function section.

user is not using the SIGN BIT OUT pin. OPBITEN = 1 enables the SIGN BIT OUT pin. DB4 SIGN/PIB The function of this bit is to control what is output at the SIGN BIT OUT pin. DAC, the waveform can be applied to the comparator to generate a square waveform. Refer to Table 17. the MSB or MSB/2 that is output. DB3 DIV2 DIV2 is used in association with SIGN/PIB and OPBITEN. Refer to Table 17. DIV2 = 1, the digital output is passed directly to the SIGN BIT OUT pin. DIV2 = 0, the digital output/2 is passed directly to the SIGN BIT OUT pin. DB2 Reserved This bit must always be set to 0. MODE = 1, the SIN ROM is bypassed, resulting in a triangle output from the DAC. signal at the output. See Table 18. DB0 Reserved This bit must always be set to 0. registers. These are described in Table 7. Table 7. Frequency/Phase Registers avoid unwanted output anomalies. function; whereas, if PIN/SW = 0, the bits control the function. Table 8. Selecting a Frequency Register

0 X 1 FREQ0 REG

1 X 1 FREQ1 REG

Table 9. Selecting a Phase Register

0 X 1 PHASE0 REG

1 X 1 PHASE1 REG

to the other frequency/phase register.

give the address of the frequency register. Table 10. Frequency Register Bits between the two frequency registers. Table 11. Writing FFFC000 to FREQ0 REG

14 MSBs = 3FFF

are altered; though with fine tuning only the 14 LSBs are altered. this are shown in Table 12 and Table 13. Table 12. Writing 3FFF to the 14 LSBs of FREQ1 REG Table 13. Writing 00FF to the 14 MSBs of FREQ0 REG to 11. Bit DB13 identifies which phase register is being loaded. Table 14. Phase Register Bits phase, frequency, or control registers. output seven MCLK cycles after RESET is set to 0. RESET pin controls the function. Table 15. Applying RESET

0 X 1 No reset applied

1 X 1 Internal registers reset

on the internal falling edge of MCLK. the SLEEP function are outlined in Table 16.

Table 16. Applying the SLEEP Function

0 X X 1 No power-down

1 X X 1 DAC powered

can be powered down to reduce power consumption. can be written to the part when the SLEEP1 control bit is active. on the internal falling edge of MCLK. to generate a square waveform. controls the frequency of this output from the SIGN BIT OUT pin. Table 17. Various Outputs from SIGN BIT OUT

0 X X X High impedance

output or a triangle output. and IOUTB pins, set Bit MODE (DB1) to 1. DAC is enabled) when using the IOUT and IOUTB pins. Table 18. Various Outputs from IOUT and IOUTB Figure 30. Triangle Output

Figure 34. Selecting Data Sources

Rev. C | Page 26 of 36 GROUNDING AND LAYOUT The printed circuit board (PCB) that houses the AD9834 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can easily be separated. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD9834 is the only device requiring an AGND-to-DGND connection, the ground planes should be connected at the AGND and DGND pins of the AD9834. If the AD9834 is in a system where multiple devices require AGND-to-DGND connections, the connection should be made at one point only, establishing a star ground point as close as possible to the AD9834. Avoid running digital lines under the device because these couple noise onto the die. The analog ground plane should be allowed to run under the AD9834 to avoid noise coupling. The power supply lines to the AD9834 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feed- through through the board. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes and signals are placed on the other side. Good decoupling is important. The analog and digital supplies to the AD9834 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND, respectively, with 0.1 μF ceramic capacitors in parallel with 10 μF tantalum capacitors. To achieve the best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD of the AD9834, it is recommended that the system’s AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the AD9834 and AGND, and the recommended digital supply decoupling capacitors between the DVDD pins and DGND. Proper operation of the comparator requires good layout strategy. The strategy must minimize the parasitic capacitance between VIN and the SIGN BIT OUT pin by adding isolation using a ground plane. For example, in a multilayered board, the VIN signal could be connected to the top layer, and the SIGN BIT OUT could be connected to the bottom layer so that isolation is provided by the power and ground planes between them.

Figure 41. AD9834 Evaluation Board Schematic, Part A

Figure 42. AD9834 Evaluation Board Schematic, Part B—J1 Header Connector

Figure 43. AD9834 Evaluation Board Component Side

Figure 44. AD9834 Evaluation Board Silkscreen

Figure 45. AD9834 Evaluation Board Solder Side

6.40 BSC

Figure 46. 20-Lead Thin Shrink Small Outline Package [TSSOP] 2 For the EVAL-AD9834SDZ, a SDP board is required.

Rev. C | Page 36 of 36 NOTES ©2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02705-0-2/11(C)