AD9830

AD9830 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 16

Technical content

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9830 © Analog Devices, Inc., Tel: 617/329-4700 Fax:

FEATURES

+5 V Power Supply

50 MHz Speed

On-Chip SINE Look-Up Table On-Chip 10-Bit DAC Parallel Loading Power-Down Option 72 dB SFDR 250 mW Power Consumption 48-Pin QFP

APPLICATIONS

This DDS device is a numerically controlled oscillator em- ploying a phase accumulator, a sine look-up table and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for phase modulation and frequency modulation. Clock rates up to 50 MHz are supported. Frequency accu- racy can be controlled to one part in 4 billion. Modulation is effected by loading registers through the parallel micro- processor interface. A power-down pin allows external control of a power-down mode. The part is available in a 48-pin QFP package. FUNCTIONAL BLOCK DIAGRAM RESET SLEEP IOUT IOUT COMP REFINFS ADJUSTREFOUTAGNDAVDDDGNDDVDD MCLK FSELECT D15 WR A0 A1 A2 PSEL0 PSEL1 AD9830 ON-BOARD REFERENCE FULL SCALE CONTROL 10-BIT DACSIN ROM PHASE ACCUMULATOR (32-BIT) MUX MUX FREQ0 REG FREQ1 REG PHASE0 REG PHASE1 REG PHASE2 REG PHASE3 REG PARALLEL REGISTER TRANSFER CONTROL MPU INTERFACE Σ REV. B

1Operating temperature range is as follows: A Version: –40 °C to +85 °C. 2All dynamic specifications are measured using IOUT. 100% production tested. 3fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, f OUT = 2.11 MHz. 4Measured with the digital inputs static and equal to 0 V or DVDD. not tied from REFOUT to AGND. load capacitance equals 250 pF. Specifications subject to change without notice. Figure 1. Test Circuit with Which Specifications Are

–4– ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) Operating Temperature Range QFP θ Lead Temperature, Soldering *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATION NC AVDD FS ADJUST AGND NC AGND AGND NC 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 39 38 3743 42 41 40 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) AGND RESET DB0 DB1 DB11 DGND DB15 DB14 DB13 DB12 DB10 REFIN REFOUT SLEEP DVDD DVDD DGND MCLK NC = NO CONNECT WR DVDD FSELECT PSEL0 DGND DB2 DB3 DB4 DB9 DB8 DB7 DB6 COMP AD9830 DB5 PSEL1 DVDD AVDD IOUT IOUT REV. B

–5– PIN DESCRIPTION Mnemonic Function POWER SUPPLY AVDD Positive power supply for the analog section. A 0.1 µF capacitor should be connected between AVDD and AGND. AVDD has a value of +5 V ± 5%. AGND Analog Ground. DVDD Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between DVDD and DGND. DVDD has a value of +5 V ± 5%. DGND Digital Ground. ANALOG SIGNAL AND REFERENCE IOUT, IOUT Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND. IOUT should be either tied directly to AGND or through an external load resistor to AGND. FS ADJUST Full-Scale Adjust Control. A resistor (R SET) is connected between this pin and AGND. This determines the mag- nitude of the full-scale DAC current. The relationship between R SET and the full-scale current is as follows: IOUTFULL-SCALE = 16 VREFIN/RSET VREFIN = 1.21 V nominal, RSET = 1 kΩ typical REFIN Voltage Reference Input. The AD9830 can be used with either the on-board reference, which is available from pin REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9830 ac- cepts a reference of 1.21 V nominal. REFOUT Voltage Reference Output. The AD9830 has an on-board reference of value 1.21 V nominal. The reference is made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND. COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic capacitor should be connected between COMP and AVDD. DIGITAL INTERFACE AND CONTROL MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase ac- cumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an MCLK rising edge occurs. If FSELECT changes value when an MCLK rising edge occurs, there is an uncertainty of one MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a change on FSELECT should not coincide with an MCLK rising edge. WR Write, Edge-Triggered Digital Input. The WR pin is used when writing data to the AD9830. The data is loaded into the AD9830 on the rising edge of the WR pulse. This data is then loaded into the destination register on the MCLK rising edge. The WR pulse rising edge should not coincide with the MCLK rising edge as there will be an uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The WR ris- ing edge should occur before an MCLK rising edge. The data will then be transferred into the destination register on the MCLK rising edge. Alternatively, the WR rising edge can occur after the MCLK rising edge and the desti- nation register will be loaded on the next MCLK rising edge. D0–D15 Data Bus, Digital Inputs for destination registers. A0–A2 Address Digital Inputs. These address bits are used to select the destination register to which the digital data is to be written. PSEL0, PSEL1 Phase Select Input. The AD9830 has four phase registers. These registers can be used to alter the value being in- put to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, the inputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, the AD9830 samples the PSEL0 and PSEL1 inputs on the MCLK rising edge. Therefore, these inputs should be in steady state at the MCLK rising edge or, there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase register. SLEEP Low Power Control, active low digital input. SLEEP puts the AD9830 into a low power mode. Internal clocks are disabled and the DAC’s current sources and REFOUT are turned off. The AD9830 is re-enabled by taking SLEEP high. RESET Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog output of midscale. REV. B

–6– TERMINOLOGY Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 and full scale, a point 0.5 LSB above the last code transition Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between two adjacent codes in the DAC. Signal to (Noise + Distortion) Signal to (Noise + Distortion) is measured signal to noise at the output of the DAC. The signal is the rms magnitude of the fun- damental. Noise is the rms sum of all the nonfundamental sig- nals up to half the sampling frequency (f MCLK/2) but excluding the dc component. Signal to (Noise + Distortion) is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical Signal to (Noise + Distortion) ratio for a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB where N is the number of bits. Thus, for an ideal 10-bit con- verter, Signal to (Noise + Distortion) = 61.96 dB. Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9830, THD is defined as THD = 20log (V2 +V3 +V4 +V5 +V6 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonic. Output Compliance The output compliance refers to the maximum voltage which can be generated at the output of the DAC to meet the specifi- cations. When voltages greater than that specified for the out- put compliance are generated, the AD9830 may not meet the specifications listed in the data sheet. For the AD9830, the maximum voltage which can be generated by the DAC is 1V. Spurious Free Dynamic Range Along with the frequency of interest, harmonics of the funda- mental frequency and images of the MCLK frequency will be present at the output of a DDS device. The spurious free dy- namic range (SFDR) refers to the largest spur or harmonic which is present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the bandwidth ± 2 MHz about the fundamental frequency. The narrowband SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ± 200 kHz and ± 50 kHz about the fundamental frequency. Clock Feedthrough There will be feedthrough from the MCLK input to the analog output. The clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the AD9830’s output spectrum. REV. B

Digital-to-Analog Converter on a single integrated circuit. modulation algorithms using DSP techniques. the other hand, the angular information is linear in nature. Figure 22. Sine Wave The AD9830 builds the output based on this simple equation. the sinusoid functions repeat themselves in a periodic manner. frequency modulation schemes, such as GMSK. of the phase registers equals 2 π/4096.

adjustments to RSET can balance changes made to the load resistor. than 20 mA, the linearity of the DAC may degrade. loaded during each write cycle. 4 MSBs of the 16 bit word do not have to contain valid data. fications should be complied with. WR have latencies of six MCLK cycles. tain invalid data and, therefore, should be set to zero by the user. reacts to the change on these inputs. Figure 23. Flow Chart for AD9830 Initialization and Operation

–12– The AD9830 contains functions which make it suitable for modulation applications. The part can be used to perform simple modulation such as FSK. More complex modulation schemes such as GMSK and QPSK can also be implemented using the AD9830. In a FSK application, the two frequency reg- isters of the AD9830 are loaded with different values, one fre- quency will represent the space frequency while the other will represent the mark frequency. The digital data stream is fed to the FSELECT pin which will cause the AD9830 to modulate the carrier frequency between the two values. The AD9830 has four phase registers which enable the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount which is related to the bit str eam being input to the modulat or. The presence of four shift registers eases the interaction ne eded between the DSP and the AD9830. The frequency and phase registers can be written to continuously, if required. The maximum update rate equals the frequency of the MCLK. However, if a selected register is loaded with a new word, there will be a delay of 6 MCLK cycles before the analog output will change accordingly. The AD9830 is also suitable for signal generator applications. With its low current consumption, the part is suitable for mobile applications in which it can be used as a local oscillator. Figure 24 shows the interface between the AD9830 and AD6459 which is a down converter used on the receive side of mobile phones or basestations. BANDPASS FILTER IFIP IFIM MXOP MXOM MIDPOINT BIAS GENERATOR BIAS CIRCUIT LOIP FILTER 51Ω51Ω

10 BITS R SET

1kΩ AD9830 AD6459 PLL 90° GAIN TC COMPENSATION IRxP IRxN FREF FLTR QRxP QRxN GAIN GREF RFHI RFLO VPS1 VPS2 PRUP COM1 COM2 0.1µF ANTENNA Figure 24. AD9830 and AD6459 Receiver Circuit

–13– Grounding and Layout The printed circuit board that houses the AD9830 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A mini- mum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD9830 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD9830. If the AD9830 is in a system where mul- tiple devices require AGND to DGND connections, the con- nection should be made at one point only, a star ground point that should be established as close as possible to the AD9830. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD9830 to avoid noise coupling. The power supply lines to the AD9830 should use as large a track as is pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the ef- fects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. Good decoupling is important. The analog and digital supplies to the AD9830 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND respectively with 0.1 µF ceramic capacitors in parallel with 10 µF tantalum capacitors. To achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD of the AD9830, it is recommended that the system’s AVDD supply be used. This supply should have the recom- mended analog supply decoupling between the AVDD pins of the AD9830 and AGND and the recommended digital supply decoupling capacitors between the DVDD pins and DGND. REV. B

Rev. B | Page 14 of 16 OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MS-026-BBC TOP VIEW (PINS DOWN) 3748 0.27 0.22 0.17 0.50 BSC LEAD PITCH 1.60 MAX 0.75 0.60 0.45 VIEW A PIN 1 0.20 0.09 1.45 1.40 1.35 0.08 COPLANARITY VIEW A ROTATED 90° CCW SEATING PLANE 3.5° 0°0.15 0.05 9.20 9.00 SQ 8.80 7.20 7.00 SQ 6.80 051706-A Figure 1. 48-Lead Low Profile Quad Flat Package [LQFP]

REVISION HISTORY

11/11—Rev. A to Rev. B Changed Title from CMOS Complete DDS to Direct Digital Deleted AD9830 Evaluation Board Section, Using the AD9830 Evaluation Board Section, Prototyping Area Section, XO vs.

Rev. B | Page 15 of 16 NOTES

Rev. B | Page 16 of 16 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D10308-0-11/11(B)