AD9801

AD9801 AD | Alldatasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9801 Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 CCD Signal Processor For Electronic Cameras FUNCTIONAL BLOCK DIAGRAM SHP AD9801 PGA PGACONT1 PGACONT2 CLAMP CLPDM CDS PBLK PIN DIN SHD ADCCLK TIMING GENERATOR 23 29 3019 21 22 16 37 48 47 18 CMLEVEL VRT VRB STBY REFERENCE S/H CLPOB CLAMP A/D DOUT ACVDD ADVDD DVDD

12 DRVDD

FEATURES

10-Bit, 18 MSPS A/D Converter

18 MSPS Full-Speed CDS

Low Noise, Wideband PGA Internal Voltage Reference No Missing Codes Guaranteed +3 V Single Supply Operation Low Power CMOS: 185 mW 48-Pin TQFP Package PRODUCT DESCRIPTION The AD9801 is a complete CCD signal processor developed for electronic cameras. It is well suited for both video conferencing and consumer level still camera applications. The signal processing chain is comprised of a high speed CDS, variable gain PGA and 10-bit ADC. Required clamping circuitry and an onboard voltage reference are also provided. The AD9801 operates from a single +3 V supply with a typical power consumption of 185 mW. The AD9801 is packaged in a space saving 48-pin thin-quad flatpack (TQFP) and is specified over an operating temperature range of 0°C to +70°C. PRODUCT HIGHLIGHTS 1. On-Chip Input Clamp and CDS Clamp circuitry and high speed correlated double sampler allow for simple ac coupling to interface a CCD sensor at full 18 MSPS conversion rate. 2. On-Chip PGA The AD9801 includes a low noise, wideband amplifier with analog variable gain from 0 dB to 31.5 dB (linear in dB). 3. 10-Bit, High Speed A/D Converter A linear 10-bit ADC is capable of digitizing CCD signals at the full 18 MSPS conversion rate. (Typical DNL is ± 0.5 LSB and no missing code performance is guaranteed.) 4. Low Power At 185 mW, the AD9801 consumes a fraction of the power of presently available multichip solutions. The part’s power- down mode (15 mW) further enhances its desirability in low power, battery operated applications. 5. Digital I/O Functionality The AD9801 offers three-state digital output control. 6. Small Package Packaged in a 48-pin, surface-mount thin-quad flatpack, the AD9801 is well suited to very tight, low headroom designs.

–2– REV. 0 AD9801–SPECIFICATIONS (TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise noted) Parameter Min Typ Max Units TEMPERATURE RANGE Operating 0 70 °C Storage –65 150 °C POWER SUPPLY VOLTAGE (For Functional Operation) ACVDD 3.00 3.15 3.50 V ADVDD 3.00 3.15 3.50 V DVDD 3.00 3.15 3.50 V DRVDD 3.00 3.15 3.50 V POWER SUPPLY CURRENT ACVDD 39.5 mA ADVDD 14.6 mA DVDD 4.7 mA DRVDD 0.07 mA POWER CONSUMPTION Normal Operation 185 mW Power-Down Mode 15 mW MAXIMUM SHP, SHD, ADCCLK RATE 18 MHz ADC Resolution 10 Bits Differential Nonlinearity ± 0.5 LSB No Missing Codes GUARANTEED ADCCLK Rate 18 MHz Reference Top Voltage 1.75 V Reference Bottom Voltage 1.25 V Input Range 1.0 V p-p CDS Maximum Input Signal 500 mV p-p Pixel Rate 18 MHz PGA1 Maximum Gain 31.5 dB High Gain 15 19 23 dB Medium Gain 0.5 3.5 6.5 dB Minimum Gain –5 –1 +3 dB CLAMP Average Black Level (During CLPOB. Only Stable Over PGA Range 0.3 V to 2.7 V) 32 LSB 1PGA test conditions: max gain PGACONT1 = 2.7 V, PGACONT2 = 1.5 V; high gain PGACONT1 = 2.0 V, PGACONT2 = 1.5 V; medium gain PGACONT1 = Specifications subject to change without notice. DIGITAL SPECIFICATIONS Parameter Symbol Min Typ Max Units LOGIC INPUTS High Level Input Voltage V IH 2.4 V Low Level Input Voltage V IL 0.6 V High Level Input Current I IH 10 µA Low Level Input Current I IL 10 µA Input Capacitance C IN 10 pF LOGIC OUTPUTS High Level Output Voltage V OH 2.4 V Low Level Output Voltage V OL 0.6 V IOH 50 µA IOL 50 µA Specifications subject to change without notice. (TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise noted)

–3–REV. 0 TIMING SPECIFICATIONS Parameter Min Typ Max Units ADCCLK CLOCK PERIOD 55.6 ns ADCCLK High Level Period 24.8 27.8 ns ADCCLK Low Level Period 24.8 27.8 ns SHP, SHD Clock Period 55.6 ns Digital Output Delay 20 ns Digital Output Data Control Mode1 Mode2 Digital Output Data (D9–D0) 0 0 Normal Operation 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 1 High Impedance (TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise noted) ABSOLUTE MAXIMUM RATINGS* Parameter With Respect To Min Max Units ADVDD ADVSS, SUBST –0.3 6.5 V ACVDD ACVSS, SUBST –0.3 6.5 V DVDD DVSS, DSUBST –0.3 6.5 V DRVDD DRVSS, DSUBST –0.3 6.5 V SHP, SHD DSUBST –0.3 DVDD + 2.0 V ADCCLK, CLOB, CLPDM DSUBST –0.3 DVDD + 0.3 V PGACONT1, PGACONT2 SUBST –0.3 ACVDD + 0.3 V PIN, DIN SUBST –0.3 ACVDD + 0.3 V DOUT DSUBST –0.3 DRVDD + 0.3 V VRT, VRB SUBST –0.3 ADVDD + 0.3 V CLAMP_BIAS SUBST –0.3 ACVDD + 0.3 V CCDBYP1, CCDBYP2 SUBST –0.3 ACVDD + 0.3 V STBY DSUBST –0.3 DVDD + 0.3 V MODE1, MODE2 SUBST –0.3 ADVDD + 0.3 V DRVSS, DVSS, ACVSS, ADVSS SUBST, DSUBST –0.3 +0.3 V Junction Temperature +150 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) +300 °C * Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9801 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model Temperature Package Description Package Option* AD9801 0 °C to +70°C 48-Pin TQFP ST-48 *ST = Thin Quad Flatpack Package.

–4– REV. 0 Pin No. Pin Name Type Description

1 ADVSS P Analog Ground

2–11 D0–D9 DO Digital Data Outputs

12 DRVDD P +3 V Digital Driver Supply

13 DRVSS P Digital Driver Ground

14 DSUBST P Digital Substrate

15 DVSS P Digital Ground

16 ADCCLK DI ADC Sample Clock Input

17 DVDD P +3 V Digital Supply

18 STBY DI Power down (Active HIGH)

19 PBLK DI Pixel Blanking (Active LOW)

20 CLPOB DI Black Level Restore Clamp (Active LOW)

21 SHP DI Reference Sample Clock Input

22 SHD DI Data Sample Clock Input

23 CLPDM DI Input Clamp (Active Low)

24 DVSS DI Digital Ground

25 CCDBYP2 AO CCD Bypass (Decouple to Analog Ground Through 0.1 µF) 26 DIN AI CDS Input (Tie to Pin 27 and AC-Couple to CCD Output Through 0.1 µF)

27 PIN AI CDS Input (See Above)

28 CCDBYP1 AO CCD Bypass (Decouple to Analog Ground Through 0.1 µF) 29 PGACONT1 AI Coarse PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1 µF) 30 PGACONT2 AI Fine PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1 µF)

31 ACVSS P Analog Ground

32 CLAMP_BIAS AO Clamp Bias Level (Decouple to Analog Ground Through 0.1 µF)

33 ACVDD P +3 V Analog Supply

34 ACVDD AI +3 V Analog Supply

35 ACVDD AI +3 V Analog Supply

36 INT_BIAS1 AO Internal Bias Level (Decouple to Analog Ground Through 0.1 µF) 37 CMLEVEL AO Common-Mode Level (Decouple to Analog Ground Through 0.1 µF) 38 INT_BIAS2 AO Internal Bias Level (Decouple to Analog Ground Through 0.1 µF)

39 MODE2 DI ADC Test Mode Control (See Digital Output Data Control)

40 MODE1 DI ADC Test Mode Control (See Digital Output Data Control)

41 ADVSS P Analog Ground

42 ADVDD P +3 V Analog Supply

43 ADVDD P +3 V Analog Supply

44 ADVSS P Analog Ground

45 ADVSS P Analog Ground

46 SUBST P Substrate (Connect to Analog Ground)

47 VRB AO Bottom Reference Bypass (Decouple to Analog Ground Through 0.1 µF) 48 VRT AO Top Reference Bypass (Decouple to Analog Ground Through 0.1 µF) PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 1 01 11 2 36 35 34 33 32 27 26 2531 30 29 28 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) AD9801 VRT VRB SUBST ADVSS ADVSS ADVDD ADVDD ADVSS MODE1 MODE2 INT_BIAS2 CMLEVEL DRVSS DSUBST DVSS ADCCLK INT_BIAS1 DVDD STBY PBLK CLPOB SHP SHD CLPDM DVSS ACVDD ACVDD ACVDD CLAMP_BIAS ACVSS PGACONT2 PGACONT1 CCDBYP1 PIN DIN CCDBYP2 ADVSS (LSB) D0 (MSB) D9 DRVDD

Figure 10. Typical Horizontal Interval Timing

–9–REV. 0 The actual implementation of this loop is slightly more compli- cated as shown in Figure 18. Because there are two separate CDS blocks, two black level feedback loops are required and two offset voltages are developed. Figure 18 also shows an additional PGA block in the feedback loop labeled “RPGA.” PGA ADCIN CLPOB NEG REF CONTROL CDS1 RPGA2 INT2 CDS1 RPGA1 INT1 Figure 18. The RPGA uses the same control inputs as the PGA, but has the inverse gain. The RPGA functions to attenuate by the same factor as the PGA amplifies, keeping the gain and bandwidth of the loop constant. Input Bias Level Clamping The buffered CCD output is connected to the AD9801 through an external coupling capacitor. The dc bias point for this coupling capacitor is established during the clamping (CLPDM = LOW) period using the “dummy clamp” loop shown in Figure 19. When closed around the CDS, this loop establishes the desired DC bias point on the coupling capacitor. BLACK LEVEL CLP CCD INPUT CLAMP CDS CLPDM TO ADCPGA Figure 19. Input Blanking In some applications, the AD9801’s input may be exposed to large signals from the CCD. These signals can be very large, relative to the AD9801’s input range, and could thus saturate on-chip circuit blocks. Recovery time from such saturation conditions could be substantial. To avoid problems associated with processing these transients, the AD9801 includes an input blanking function. When active (PBLK = LOW), this function stops the CDS operation and allows the user to disconnect the CDS inputs from the CCD buffer. If the input voltage exceeds the supply rail by more than

0.3 V, protection diodes will be turned on, increasing current

flow into the AD9801 (see Equivalent Input Circuits). Such voltage levels should be externally clamped to prevent device damage or reliability degradation. 10-Bit Analog-to-Digital Converter (ADC) The ADC employs a multibit pipelined architecture, which is well-suited for high throughput rates while being both area and power efficient. The multistep pipeline presents a low input capacitance resulting in lower on-chip drive requirements. A fully differential implementation was used to overcome head- room constraints of the single +3 V power supply. Differential Reference The AD9801 includes a 0.5 V reference based on a differential, continuous-time bandgap cell. Use of an external bypass capacitor reduces the reference drive requirements, thus lowering the power dissipation. The differential architecture was chosen for its ability to reject supply and substrate noise. Recommended decoupling shown in Figure 20. VRT REF VRB 1µF 0.1µF 0.1µF Figure 20. Internal Timing The AD9801’s on-chip timing circuitry generates all clocks necessary for operation of the CDS and ADC blocks. The user needs only to synchronize the SHP and SHD clocks with the CCD waveform, as all other timing is handled internally. The ADCCLK signal is used to strobe the output data, and can be adjusted to accommodate desired timing.

–10– REV. 0

APPLICATION INFORMATION

For best performance, the AD9801 should be driven by 3 V logic levels. As shown in the Equivalent Input Circuits, the use of 5 V logic for ADCCLK will turn on the protection diode to DVDD, increasing the current flow into this pin. As a result, noise and power dissipation will increase. The CDS clock inputs, SHP and SHD, have additional protection and can withstand direct 5 V levels. External clamping diodes or resistor dividers can be used to translate 5 V levels to 3 V levels, but the lowest power dissipa- tion is achieved with a logic transceiver chip. National Semi- conductor’s 74LVX4245 provides a 5 V to 3 V level shift for up to eight clock signals, and features a three-state option and low power consumption. Philips Semiconductor and Quality also manufacture similar devices. Digitally Programmable Gain Control The AD9801’s PGA is controlled by an analog input voltage of 0.3 V to 2.7 V. In some applications, digital gain control is preferable. Figure 21 shows a circuit using Analog Devices’ AD8402 Digital Potentiometer to generate the PGA control voltage. The AD8402 functions as two individual potentiom- eters, with a serial digital interface to program the position of each wiper over 256 positions. The device will operate with 3 V or 5 V supplies, and features a power-down mode and a reset function. To keep external components to a minimum, the ends of the “potentiometers” can be tied to ground and +3 V. One pot is used for the coarse gain adjust, PGACONT1, with steps of about 0.2 dB/LSB. The other pot is used for fine gain control, PGACONT2, and is capable of around 0.01 dB steps if all eight bits are used. The two outputs should be filtered with 1 µF or larger capacitors to minimize noise into the PGACONT pins of the AD9801. The disadvantage of this circuit is that the control voltage will be supply dependent. If additional precision is required, an external op amp can be used to amplify the VREFT (1.75 V) or VREFB (1.25 V) pins on the AD9801 to the desired voltage level. These reference voltages are stable over the operating supply range of the AD9801. Low power, low cost, rail-to-rail output amplifiers such as the AD820, OP150 and OP196 are specified for 3 V operation. Alternatively, a precision voltage AD8402-10 +3V +3V CS SDI CLKSHDN RS 1µF PGACONT2 1µF0.1µF +3V PGACONT1 Figure 21. Digital Control of PGA 3 V output with a minimum 3.1 V supply when lightly loaded. parasitics) from the digital circuitry to the analog circuitry. the output risetimes, reducing the kickback effect.

40 PIN HEADER

Figure 22. AD9801EB Schematic AD9801, and the extensive supply and reference decoupling.

–12– REV. 0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C2975–12–1/97PRINTED IN U.S.A. 48-Terminal Plastic Thin Quad Flatpack (ST-48) 0.354 (9.00) BSC 0.276 (7.0) BSC 3748 TOP VIEW (PINS DOWN) 0.276 (7.0) BSC 0.354 (9.00) BSC 0.011 (0.27) 0.006 (0.17) 0.019 (0.5) BSC SEATING PLANE 0.063 (1.60) MAX 0° MIN 0° – 7° 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09)