AD9734_06 AD | Alldatasheet

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10-/12-/14-Bit, 1200 MSPS DACS AD9734/AD9735/AD9736 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

Excellent dynamic performance AD9736: SFDR = 82 dBc at fOUT = 30 MHz AD9736: SFDR = 69 dBc at fOUT = 130 MHz AD9736: IMD = 87 dBc at fOUT = 30 MHz AD9736: IMD = 82 dBc at fOUT = 130 MHz LVDS data interface with on-chip 100 Ω terminations Built-in self test LVDS sampling integrity LVDS-to-DAC data transfer integrity Low power: 380 mW (I FS = 20 mA; fOUT = 330 MHz) 1.8/3.3 V dual-supply operation Adjustable analog output 8.66 mA to 31.66 mA (RL = 25 Ω to 50 Ω) On-chip 1.2 V reference 160-lead chip scale ball grid array (CSP_BGA) package

APPLICATIONS

Broadband communications systems Cellular infrastructure (digital predistortion) Point-to-point wireless CMTS/VOD Instrumentation, automatic test equipment Radar, avionics GENERAL DESCRIPTION The AD9736, AD9735, and AD9734 are high performance, high frequency DACs that provide sample rates of up to 1200 MSPS, permitting multicarrier generation up to their Nyquist frequency. The AD9736 is the 14-bit member of the family, while the AD9735 and the AD9734 are the 12-bit and 10-bit members, respectively. They include a serial peripheral interface (SPI) port that provides for programming of many internal parameters and enables readback of status registers. A reduced-specification LVDS interface is utilized to achieve the high sample rate. The output current can be programmed over a range of 8.66 mA to 31.66 mA. The AD973x family is manufactured on a 0.18 μm CMOS process and operates from 1.8 V and 3.3 V supplies for a total power consumption of 380 mW in bypass mode. It is supplied in a 160-lead chip scale ball grid array for reduced package parasitics. FUNCTIONAL BLOCK DIAGRAM LVDS RECEIVER SYNCHRONIZER BAND GAP DATACLK_IN+ DATACLK_IN– DB[13:0]– DB[13:0]+ SPI 14-, 12-, 10-BIT DAC CORE IOUTA IOUTB SDO SDIO SCLK CSB LVDS DRIVER CONTROLLER REFERENCE CURRENT DACCLK–IRQ DACCLK+ I120VREF RESET DATACLK_OUT+ DATACLK_OUT– S1S2S3 C1S1 04862-001 CLOCK DISTRIBUTION Figure 1. PRODUCT HIGHLIGHTS 1. Low noise and intermodulation distortion (IMD) features enable high quality synthesis of wideband signals at inter- mediate frequencies up to 600 MHz. 2. Double data rate (DDR) LVDS data receivers support the maximum conversion rate of 1200 MSPS. 3. Direct pin programmability of basic functions or SPI port access offers complete control of all AD973x family functions. 4. Manufactured on a CMOS process, the AD973x family uses a proprietary switching technique that enhances dynamic performance. 5. The current output(s) of the AD9736 family are easily con- figured for single-ended or differential circuit topologies.

Rev. A | Page 2 of 72 TABLE OF CONTENTS AD9735 Static Linearity, 10 mA, 20 mA, 30 mA AD9734 Static Linearity, 10 mA, 20 mA, 30 mA AD9735, AD9734 Dynamic Performance, 20 mA LVDS Controller (LVDS_CNT) Registers SYNC Controller (SYNC_CNT) Registers Cross Controller (CROS_CNT) Registers Analog Control (ANA_CNT) Registers Built-In Self Test Control (BIST_CNT) Registers Controller Clock Predivider (CCLK_DIV) Reading Operating the LVDS Controller in Manual Mode via the

Rev. A | Page 3 of 72 Operating the LVDS Controller in Surveillance and

REVISION HISTORY

9/06—Rev. 0 to Rev. A Replaced Pin Configuration and Function Descriptions 4/05—Revision 0: Initial Version

Rev. A | Page 4 of 72 SPECIFICATIONS DC SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V , CVDD18 = DVDD18 = 1.8 V , maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load, unless otherwise noted. Table 1. AD9736 AD9735 AD9734 Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 14 12 10 Bits ACCURACY ANALOG OUTPUTS Gain Error (With Internal Reference) Gain Error (Without Internal Reference) Output Resistance 10 10 10 MΩ Output Capacitance 1 1 1 pF TEMPERATURE DRIFT Offset 0 0 0 ppm/°C Gain 80 80 80 ppm/°C Reference Voltage1 40 40 40 ppm/°C REFERENCE Output Resistance2 5 5 5 kΩ ANALOG SUPPLY VOLTAGES DIGITAL SUPPLY VOLTAGES SUPPLY CURRENTS 1× Mode, 1.2 GSPS IAVDD33 25 25 25 mA ICVDD18 47 47 47 mA IDVDD33 10 10 10 mA IDVDD18 122 122 122 mA FIR Bypass (1×) Mode 380 380 380 mW 2× Mode, 1.2 GSPS IAVDD33 25 25 25 mA ICVDD18 47 47 47 mA IDVDD33 10 10 10 mA IDVDD18 234 234 234 mA FIR 2× Interpolation Filter Enabled 550 550 550 mW

Rev. A | Page 5 of 72 AD9736 AD9735 AD9734 Parameter Min Typ Max Min Typ Max Min Typ Max Unit Static, No Clock IAVDD33 25 25 25 mA ICVDD18 8 8 8 mA IDVDD33 10 10 10 mA IDVDD18 2 2 2 mA FIR Bypass (1×) Mode 133 133 133 mW Sleep Mode, No Clock FIR Bypass (1×) Mode 59 65 59 65 59 65 mW Power-Down Mode3 1 Default band gap adjustment (Reg. 0x0E <2:0> = 0x0). 2 Use an external amplifier to drive any external load. 3 Typical wake-up time is 8 μs with recommended 1 nF capacitor on VREF pin.

Rev. A | Page 6 of 72 DIGITAL SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V , CVDD18 = DVDD18 = 1.8 V , maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load, unless otherwise noted. LVDS drivers and receivers are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter Min Typ Max Unit LVDS DATA INPUT (DB[13:0]+, DB[13:0]−) DB+ = VIA, DB− = VIB Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV Receiver Differential Input Impedance, RIN 80 120 Ω LVDS Input Rate 1200 MSPS LVDS Minimum Data Valid Period (tMDE) 344 ps LVDS CLOCK INPUT (DATACLK_IN+, DATACLK_IN−) DATACLK_IN+ = V IA, DATACLK_IN− = VIB Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold,1 VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV Receiver Differential Input Impedance, RIN 80 120 Ω Maximum Clock Rate 600 MHz LVDS CLOCK OUTPUT (DATACLK_OUT+, DATACLK_ OUT−) DATACLK_OUT+ = Voa, DATACLK_OUT− = Vob 100 Ω Termination Output Voltage High, VOA or VOB 1375 mV Output Voltage Low, VOA or VOB 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, Single-Ended, RO 80 100 120 Ω RO Mismatch Between A and B, ΔRO 10 % Change in |VOD| Between 0 and 1, |ΔVOD| 25 mV Change in VOS Between 0 and 1, ΔVOS 25 mV Output Current—Driver Shorted to Ground, ISA, ISB 20 mA Output Current—Drivers Shorted Together, ISAB 4 mA Power-Off Output Leakage, |IXA|, |IXB| 10 mA Maximum Clock Rate 600 MHz DAC CLOCK INPUT (CLK+, CLK−) Input Voltage Range, CLK− or CLK+ 0 800 Differential Peak-to-Peak Voltage 400 800 1600 mV Common-Mode Voltage 300 400 500 mV Maximum Clock Rate 1200 MHz SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (fSCLK, 1/tSCLK) 20 MHz Minimum Pulse Width High, tPWH 20 ns Minimum Pulse Width Low, tPWL 20 ns Minimum SDIO and CSB to SCLK Setup, tDS 10 ns Minimum SCLK to SDIO Hold, tDH 5 ns Maximum SCLK to Valid SDIO and SDO, tDV 20 ns Minimum SCLK to Invalid SDIO and SDO, tDNV 5 ns

Rev. A | Page 7 of 72 Parameter Min Typ Max Unit INPUT (SDI, SDIO, SCLK, CSB) Voltage in High, VIH 2.0 3.3 V Voltage in Low, VIL 0 0.8 V Current in High, IIH −10 +10 μA Current in Low, IIL −10 +10 μA SDIO OUTPUT Voltage out High, VOH 2.4 3.6 V Voltage out Low, VOL 0 0.4 V Current out High, IOH 4 mA Current out Low, IOL 4 mA 1Refer to the Input Data Timing section for recommended LVDS differential drive levels.

Rev. A | Page 8 of 72 AC SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V , CVDD18 = DVDD18 = 1.8 V , maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load, unless otherwise noted. Table 3. AD9736 AD9735 AD9734 Parameter Min Typ Max Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Update Rate 1200 1200 1200 MSPS SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 800 MSPS fOUT = 20 MHz 75 75 75 dBc fDAC = 1200 MSPS fOUT = 50 MHz 80 76 76 dBc fOUT = 100 MHz 77 74 71 dBc fOUT = 316 MHz 63 63 60 dBc fOUT = 550 MHz 55 54 53 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 1200 MSPS fOUT2 = fOUT + 1.25 MHz fOUT = 40 MHz 88 84 83 dBc fOUT = 50 MHz 85 84 83 dBc fOUT = 100 MHz 84 81 79 dBc fOUT = 316 MHz 70.5 67 66 dBc fOUT = 550 MHz 65 60 60 dBc NOISE SPECTRAL DENSITY (NSD) Single Tone fDAC = 1200 MSPS fOUT = 50 MHz −165 −162 −154 dBm/Hz fOUT = 100 MHz −164 −161 −154 dBm/Hz fOUT = 241MHz −158.5 −160.5 −159.5 −155 dBm/Hz fOUT = 316 MHz −158 −157 −152 dBm/Hz fOUT = 550 MHz −155 −155 −149 dBm/Hz Eight-Tone fDAC = 1200 MSPS, 500 kHz Tone Spacing fOUT = 50 MHz −166.5 −163 −154 dBm/Hz fOUT = 100 MHz −166 −163 −152 dBm/Hz fOUT = 241MHz −163.3 −165 −161.5 −150.5 dBm/Hz fOUT = 316 MHz −164 −162 −151 dBm/Hz fOUT = 550 MHz −162 −160 −150 dBm/Hz

soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance 1θJA measurement in still air. degradation or loss of functionality. Devices will provide a more ESD-hardy product in the near future at which time this warning will be removed from this data sheet.

Figure 2. AD9736 Digital LVDS Input, Clock I/O (Top View) Table 6. AD9736 Pin Function Descriptions A7, B7, C7, D7 IOUTB DAC Negative Output. 10 mA to 30 mA full-scale output current. A8, B8, C8, D8 IOUTA DAC Positive Output. 10 mA to 30 mA full-scale output current. generate a 120 μA reference current. capacitor; output impedance is approximately 5 kΩ. D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4 CVSS Clock Supply Ground. E1, F1 DACCLK−/DACCLK+ Negative/Positive DAC Clock Input (DACCLK). E11, E12, F11, F12, G11, G12 AVSS Analog Supply Ground Shield. Tie to AVSS at the DAC. output, pull up to DVDD33 with 10 kΩ resistor. complement input data format, 1 = unsigned. E14 RESET/PD If PIN_MODE = 0, RESET: 1 resets the AD9736. If PIN_MODE = 1, PD: 1 puts the AD9736 in the power-down state. Operation section for pin description. F14 SDIO/FIFO See the Pin Mode Operation section for pin description. G13 SCLK/FSC0 See the Pin Mode Operation section for pin description. G14 SDO/FSC1 See the Pin Mode Operation section for pin description. DVDD18 1.8 V Digital Supply.

Rev. A | Page 11 of 72 Pin No. Mnemonic Description K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6, L9, L10, L11, L12, M3, M4, M5, M6, M9, M10, M11, M12 DVSS Digital Supply Ground. K13, K14 DB<13>−/DB<13>+ Negative/Positive Data Input Bit 13 (MSB). Conforms to IEEE-1596 reduced range link. L1 PIN_MODE 0 = SPI Mode. SPI is enabled. 1 = PIN Mode. SPI is disabled; direct pin control. L7, L8, M7, M8, N7, N8, P7, P8 DVDD33 3.3 V Digital Supply. L13, L14 DB<12>−/DB<12>+ Negative/Positive Data Input Bit 12. Conforms to IEEE-1596 reduced range link. M2, M1 DB<0>−/DB<0>+ Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596 reduced range link. M13, M14 DB<11>−/DB<11>+ Negative/Positive Data Input Bit 11. Conforms to IEEE-1596 reduced range link. N1, P1 DB<1>−/DB<1>+ Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced range link. N2, P2 DB<2>−/DB<2>+ Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced range link. N3, P3 DB<3>−/DB<3>+ Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced range link. N4, P4 DB<4>−/DB<4>+ Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced range link. N5, P5 DB<5>−/DB<5>+ Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced range link. N6, P6 DATACLK_OUT−/ DATACLK_OUT+ Negative/Positive Data Output Clock. Conforms to IEEE-1596 reduced range link. N9, P9 DATACLK_IN−/ DATACLK_IN+ Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced range link. N10, P10 DB<6>−/DB<6>+ Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced range link. N11, P11 DB<7>−/DB<7>+ Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced range link. N12, P12 DB<8>−/DB<8>+ Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced range link. N13, P13 DB<9>−/DB<9>+ Negative/Positive Data Input Bit 9. Conforms to IEEE-1596 reduced range link. N14, P14 DB<10>−/DB<10>+ Negative/Positive Data Input Bit 10. Conforms to IEEE-1596 reduced range link.

Figure 3. AD9735 Digital LVDS Input, Clock I/O (Top View) Table 7. AD9735 Pin Function Descriptions A7, B7, C7, D7 IOUTB DAC Negative Output. 10 mA to 30 mA full-scale output current. A8, B8, C8, D8 IOUTA DAC Positive Output. 10 mA to 30 mA full-scale output current. generate a 120 μA reference current. capacitor; output impedance approximately 5 kΩ. D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4 CVSS Clock Supply Ground. E1, F1 DACCLK−/DACCLK+ Negative/Positive DAC Clock Input (DACCLK). E11, E12, F11, F12, G11, G12 AVSS Analog Supply Ground Shield. Tie to AVSS at the DAC. output, pull up to DVDD33 with 10 kΩ resistor. complement input data format, 1 = unsigned. E14 RESET/PD If PIN_MODE = 0, RESET: 1 resets the AD9735. If PIN_MODE = 1, PD: 1 puts the AD9735 in the power-down state. Operation section for pin description. F14 SDIO/FIFO See the Pin Mode Operation section for pin description. G13 SCLK/FSC0 See the Pin Mode Operation section for pin description. G14 SDO/FSC1 See the Pin Mode Operation section for pin description. DVDD18 1.8 V Digital Supply.

Rev. A | Page 13 of 72 Pin No. Mnemonic Description K13, K14 DB<11>−/DB<11>+ Negative/Positive Data Input Bit 11 (MSB). Conforms to IEEE-1596 reduced range link. L1 PIN_MODE 0 = SPI Mode. SPI is enabled. 1 = PIN Mode. SPI disabled; direct pin control. L7, L8, M7, M8, N7, N8, P7, P8 DVDD33 3.3 V Digital Supply. L13, L14 DB<10>−/DB<10>+ Negative/Positive Data Input Bit 10. Conforms to IEEE-1596 reduced range link. M1, M2 NC No Connect. M13, M14 DB<9>−/DB<9>+ Negative/Positive Data Input Bit 9. Conforms to IEEE-1596 reduced range link. N1, P1 NC No Connect. N2, P2 DB<0>−/DB<0>+ Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596 reduced range link. N3, P3 DB<1>−/DB<1>+ Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced range link. N4, P4 DB<2>−/DB<2>+ Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced range link. N5, P5 DB<3>−/DB<3>+ Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced range link. N6, P6 DATACLK_OUT−/ DATACLK_OUT+ Negative/Positive Data Output Clock. Conforms to IEEE-1596 reduced range link. N9, P9 DATACLK_IN−/ DATACLK_IN+ Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced range link. N10, P10 DB<4>−/DB<4>+ Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced range link. N11, P11 DB<5>−/DB<5>+ Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced range link. N12, P12 DB<6>−/DB<6>+ Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced range link. N13, P13 DB<7>−/DB<7>+ Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced range link. N14, P14 DB<8>−/DB<8>+ Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced range link.

Figure 4. AD9734 Digital LVDS Input, Clock I/O (Top View) Table 8. AD9734 Pin Function Descriptions A7, B7, C7, D7 IOUTB DAC Negative Output. 10 mA to 30 mA full-scale output current. A8, B8, C8, D8 IOUTA DAC Positive Output. 10 mA to 30 mA full-scale output current. generate a 120 μA reference current. capacitor; output impedance approximately 5 kΩ. D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4 CVSS Clock Supply Ground. E1, F1 DACCLK−/DACCLK+ Negative/Positive DAC Clock Input (DACCLK). E11, E12, F11, F12, G11, G12 AVSS Analog Supply Ground Shield. Tie to AVSS at the DAC. output, pull up to DVDD33 with 10 kΩ resistor. complement input data format, 1 = unsigned. E14 RESET/PD If PIN_MODE = 0, RESET: 1 resets the AD9734. If PIN_MODE = 1, PD: 1 puts the AD9734 in the power-down state. Operation section for pin description. F14 SDIO/FIFO See the Pin Mode Operation section for pin description. G13 SCLK/FSC0 See the Pin Mode Operation section for pin description. G14 SDO/FSC1 See the Pin Mode Operation section for pin description. DVDD18 1.8 V Digital Supply.

Rev. A | Page 15 of 72 Pin No. Mnemonic Description K13, K14 DB<9>−/DB<9>+ Negative/Positive Data Input Bit 9 (MSB). Conforms to IEEE-1596 reduced range link. L1 PIN_MODE 0 = SPI Mode. SPI is enabled. 1 = PIN Mode. SPI is disabled; direct pin control. L7, L8, M7, M8, N7, N8, P7, P8 DVDD33 3.3 V Digital Supply. L13, L14 DB<8>−/DB<8>+ Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced range link. M1, M2 NC No Connect. M13, M14 DB<7>−/DB<7>+ Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced range link. N1, P1 NC No Connect. N2, P2 NC No Connect. N3, P3 NC No Connect. N4, P4 DB<0>−/DB<0>+ Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596 reduced range link. N5, P5 DB<1>−/DB<1>+ Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced range link. N6, P6 DATACLK_OUT−/ DATACLK_OUT+ Negative/Positive Data Output Clock. Conforms to IEEE-1596 reduced range link. N9, P9 DATACLK_IN−/ DATACLK_IN+ Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced range link. N10, P10 DB<2>−/DB<2>+ Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced range link. N11, P11 DB<3>−/DB<3>+ Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced range link. N12, P12 DB<4>−/DB<4>+ Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced range link. N13, P13 DB<5>−/DB<5>+ Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced range link. N14, P14 DB<6>−/DB<6>+ Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced range link.

Rev. A | Page 17 of 72 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) The measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temp er atu re D r i ft Specified as the maximum change from the ambient (25°C) value to the value at either T MIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Multitone Power Ratio The spurious-free dynamic range containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone.

Figure 59. AD9735 SFDR vs. fOUT over fDAC, 1.2 GSPS Figure 60. AD9734 SFDR vs. fOUT over fDAC, 1.2 GSPS Figure 61. AD9735 IMD vs. fOUT over fDAC, 1.2 GSPS Figure 62. AD9734 IMD vs. fOUT over fDAC, 1.2 GSPS

1 TONE

8 TONES

Figure 63. AD9735 NSD vs. fOUT, 1.2 GSPS Figure 64. AD9734 NSD vs. fOUT, 1.2 GSPS

Write 0 to unspecified or reserved bit locations. Reading these bits returns unknown values. Table 9. SPI Register Map

Table 10. Mode Register Bit Descriptions SDIO_DIR WRITE 0, input only per SPI standard. 1, bidirectional per SPI standard. LSB/MSB WRITE 0, MSB first per SPI standard. 1, LSB first per SPI standard. 1, set software reset, write 0 on the next (or any following) cycle to release the reset. LONG_INS WRITE 0, short (single-byte) instruction word. 2×_MODE WRITE 0, disable 2× interpolation filter. 1, enable 2× interpolation filter. FIFO_MODE WRITE 0, disable FIFO synchronization. 1, enable FIFO synchronization. DATAFRMT WRITE 0, signed input DATA with midscale = 0x0000. 1, unsigned input DATA with midscale = 0x2000. PD WRITE 0, enable LVDS Receiver, DAC, and clock circuitry. 1, power down LVDS Receiver, DAC, and clock circuitry. Table 11. Interrupt Register Bit Descriptions READ 0, no active LVDS receiver interrupt. 1, interrupt in LVDS receiver occurred. READ 0, no active SYNC logic interrupt. 1, interrupt in SYNC logic occurred. READ 0, no active CROSS logic interrupt. 1, interrupt in CROSS logic occurred. IE_LVDS WRITE 0, reset LVDS receiver interrupt and disable future LVDS receiver interrupts. 1, enable LVDS receiver interrupt to activate IRQ pin. IE_SYNC WRITE 0, reset SYNC logic interrupt and disable future SYNC logic interrupts. 1, enable SYNC logic interrupt to activate IRQ pin. IE_CROSS WRITE 0, reset CROSS logic interrupt and disable future CROSS logic interrupts. 1, enable CROSS logic interrupt to activate IRQ pin.

Table 12. Full Scale Current Output Register Bit Descriptions SLEEP WRITE 0, enable DAC output. 1, set DAC output current to 0 mA. FSC<9:0> WRITE 0x000, 10 mA full-scale output current. 0x200, 20 mA full-scale output current. 0x3FF , 30 mA full-scale output current. Table 13. LVDS Controller Register Bit Descriptions MSD<3:0> WRITE 0x0, set setup delay for the measurement system. READ If ( LAUTO = 1), the latest measured value for the setup delay. If ( LAUTO = 0), readback of the last SPI write to this bit. MHD<3:0> WRITE 0x0, set hold delay for the measurement system. READ If ( LAUTO = 1), the latest measured value for the hold delay. If ( LAUTO = 0), readback of the last SPI write to this bit. SD<3:0> WRITE 0x0, set sample delay. READ If ( LAUTO = 1), the result of a measurement cycle is stored in this register. If ( LAUTO = 0), readback of the last SPI write to this bit. LCHANGE READ 0, no change from previous measurement. 1, change in value from the previous measurement. NOTE: The average filter and the threshold detection are not applied to this bit. ERR_HI READ One of the 15 LVDS inputs is above the in put voltage limits of the IEEE reduced link specification. ERR_LO READ One of the 15 LVDS inputs is below the in put voltage limits of the IEEE reduced link specification. CHECK READ 0, phase measurement—sampling in the previous or following DATA cycle. 1, phase measurement—sampling in the correct DATA cycle. LSURV WRITE 0, the controller stops after completion of the current measurement cycle. LAUTO WRITE 0, sample delay is not automatically updated. 1, continuously starts measurement cycles and updates the sample delay according to the measurement. NOTE: LSURV (Reg. 6, Bit 7) must be set to 1 and the LVDS IRQ (Reg. 1, Bit 3) must be set to 0 for AUTO mode. LTRH<2:0> WRITE 000, set auto update threshold values.

Table 14. Sync Controller Register Bit Descriptions FIFOSTAT<2:0> READ Position of FIFO read counter ranges from 0 to 7. FIFOSTAT<3> READ 0, SYNC logic OK. VALID READ 0, FIFOSTAT<3:0> is not valid yet. 1, FIFOSTAT<3:0> is valid after a reset. SCHANGE READ 0, no change in FIFOSTAT<3:0>. PHOF<1:0> WRITE 00, change the readout counter. READ Current setting of the readout counter (PHOF<1:0>) in surveillance mode (SSURV = 1) after an interrupt. Current calculated optimal readout counter value in AUTO mode (SAUTO = 1). SSURV WRITE 0, the controller stops after completion of the current measurement cycle. SAUTO WRITE 0, readout counter (PHOF<3:0>) is not automatically updated. STRH<0> WRITE 0, if FIFOSTAT<2:0> = 0 or 7, a sync interrupt is generated. 1, if FIFOSTAT<2:0> = 0, 1, 6 or 7, a sync interrupt is generated. Table 15. Cross Controller Register Description UPDEL<5:0> WRITE 0x00, move the differential output stage switching point up, set to 0 if DNDEL is non-zero. DNDEL<5:0> WRITE 0x00, move the differential output stage switching point down, set to 0 if UPDEL is non-zero.

Table 16. Analog Control Register Bit Descriptions MSEL<1:0> WRITE 00, mirror roll off frequency control = bypass. 01, mirror roll off frequency control = narrowest bandwidth. 10, mirror roll off frequency control = medium bandwidth. 11, mirror roll off frequency control = widest bandwidth. NOTE: See the plot in the Analog Control Registers section. TRMBG<2:0> WRITE 000, band gap temperature characteristic trim. NOTE: See the plot in the Analog Control Registers section. HDRM<7:0> WRITE 0xCA, output stack headroom control. HDRM<7:4> set reference offset from AVDD33 (VCAS centering). HDRM<3:0> set overdrive (current density) trim (temperature tracking). Note: Set to 0xCA for optimum performance. Table 17. BIST Control Register Bit Descriptions SEL<1:0> WRITE 00, write result of the LVDS Phase 1 BIST to BIST<31:0>. 01, write result of the LVDS Phase 2 BIST to BIST<31:0>. 10, write result of the SYNC Phase 1 BIST to BIST<31:0>. 11, write result of the SYNC Phase 2 BIST to BIST<31:0>. SIG_READ WRITE 0, no action. 1, enable BIST signature readback. 1, clear all BIST registers. BIST<31:0> READ Results of the built-in self test.

Table 18. Controller Clock Predivider Register Bit Descriptions CCD<3:0> WRITE 0x0, controller clock = DACCLK/16. 0x1, controller clock = DACCLK/32. 0xF, controller clock = DACCLK/524288.

I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO). Figure 68. AD973x SPI Port is described in the Pin Mode Operation section. a write data transfer occurs after the instruction byte write. transfer cycle. The bit decodes are shown in Table 20. based on the LSBFIRST bit (Reg. 0, Bit 6). Table 20. Byte Transfer Count (0x1F), so always set LONG_INS = 0. the AD973x on the rising edge of SCLK.

between the DACCLK and the DATACLK_IN clock domains.

8 WORD

Figure 82. Sync Logic Block Diagram Figure 82. The relative pointer can be adjusted with the phase offset PHOF<1:0> (Reg. can only adjust the read pointer in steps of 2. timing is not yet critical, but it is not optimal. PHOF<1:0> = 1 effectively increments the read pointer by 2. later, decreasing FIFOSTAT<2:0> from 6 to 4. Bit 7), then enable the sync interrupt (Reg. 1, Bit 2). is read at Reg. 1, Bit 6 at the AD973x IRQ pin. can be set to the maximum value. FIFO read pointer and write pointer plus 4 more clock periods.

Figure 83. Sync Logic Timing Diagram

  1. Set input DATA = 0x0000 for signed (0x2000 for
  2. Enable DATACLK_IN if it is not already running.
  3. Run for at least 16 DATACLK_IN cycles.
  4. Run for at least 16 DATACLK_IN cycles.
  5. Run for at least 16 DATACLK_IN cycles.
  6. Set desired operating mode (1× mode and signed data are

default values and expected for the supplied BIST vectors).

  1. Set CLEAR (Reg. 17, Bit 0), SYNC_EN (Reg. 17, Bit 1),

and LVDS_EN (Reg. 17, Bit 2) high.

  1. Wait 50 DATACLK_IN cycles to allow 0s to propagate

through and clear sync signatures.

  1. Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and

and verify they are all 0x00. SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1). SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1). SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1). SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).

  1. Clock the BIST vector into the AD973x.
  2. After the BIST vector is clocked into the part, hold DATA

additional nonzero data changes the signature.

  1. Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and
  2. Flush the BIST circuitry. This must be done once before

test to obtain the correct result. BIST. The BIST vector is for 1×, no FIFO, and signed data. and verify against the signatures in Table 25. Table 25. Expected BIST Data Readback for All Bits against the values in Table 26. Table 26. Expected BIST Data Readback for Individual Bits

  • The term rise refers to Phase 1 and fall refers to Phase 2.
  • Byte order is Decimal Register Address 21, Address 20, Address 19, and Address 18.
  • SYNC phase should always equal LVDS phase in 1× mode.

Rev. A | Page 46 of 72 GENERATING EXPECTED SIGNATURES The following MATLAB code duplicates the internal logic of the AD973x. To use it, save this code in a file called bist.m. --- begin bist.m --- function [ ret1 , ret2] = bist(vec) ret1 = bist1(vec(1:2:length(vec)-1)); ret2 = bist1(vec(2:2:length(vec))); function ret = bist1(v) sum = zeros(1,32); for i = 1 :length(v) if v(i) ~= 0 su(1) = ~xor(sum(32) ,bitget(v(i),1)); su(2) = ~xor(sum(1) ,bitget(v(i),2)); su(3) = ~xor(sum(2) ,bitget(v(i),3)); su(4) = ~xor(sum(3) ,bitget(v(i),4)); su(5) = ~xor(sum(4) ,bitget(v(i),5)); su(6) = ~xor(sum(5) ,bitget(v(i),6)); su(7) = ~xor(sum(6) ,bitget(v(i),7)); su(8) = ~xor(sum(7) ,bitget(v(i),8)); su(9) = ~xor(sum(8) ,bitget(v(i),9)); su(10) = ~xor(sum(9) ,bitget(v(i),10)); su(11) = ~xor(sum(10) ,bitget(v(i),11)); su(12) = ~xor(sum(11) ,bitget(v(i),12)); su(13) = ~xor(sum(12) ,bitget(v(i),13)); su(14) = ~xor(sum(13) ,bitget(v(i),14)); su(15) = sum(14); su(16) = sum(15); su(17) = sum(16); su(18) = sum(17); su(19) = sum(18); su(20) = sum(19); su(21) = sum(20); su(22) = sum(21); su(23) = sum(22); su(24) = sum(23); su(25) = sum(24); su(26) = sum(25); su(27) = sum(26); su(28) = sum(27); su(29) = sum(28); su(30) = sum(29); su(31) = sum(30); su(32) = sum(31); sum = su; end end % for ret = dec2hex( 2.^[0:31]× sum',8); --- end bist.m --- To generate the expected BIST signatures, follow this procedure: 1. Start MATLAB and type the following at the command prompt: t = round(randn(1,100) × 213/8+213) ; [ b1 b2 ] = bist(t) The first statement creates a random vector of 14-bit words, with a length of 100. 2. Set t equal to any desired vector, or take this random vector and input it to the AD973x. 3. Alter the command randn(1,100) to change the vector length as desired. 4. Type b1 at the command line to see the calculated signature for the LVDS BIST, Phase 1. 5. Type b2 to see the value for LVDS BIST, Phase 2. The values returned for b1 and b2 each are 32-bit hex values. They correspond to Reg. 18, Reg. 19, Reg. 20, and Reg. 21, where b1 is the value read for SEL<1:0> = 0, 0 (see Table 17) and b2 is the value read for SEL<1:0> = 0, 1. When the DAC is in 1× mode, the signature at SYNC BIST, Phase 1 should equal the signature at LVDS BIST, Phase 1. The same is true for Phase 2.

output current mirror headroom adjustments. minimize the drift over temperature, as shown in Figure 86. Figure 86. Band Gap Temperature Characteristic for Various TRMBG Values and Figure 86 may not be representative of all fabrication lots. external nonvolatile memory. 20 mA full-scale current into a 50 Ω resistor. Figure 87. 1/f Noise with Respect to MSEL Bits HDRM<7:0> (Reg. 15, Bits 7:0) are for internal evaluation. Changing the default reset values is not recommended. Figure 88. Voltage Reference Circuit

19272 FSCR

20 IFS (mA)

Figure 89. IFS vs. DAC Gain Code

1.8 V supply, so it is important to maintain the specified 400 mV

Figure 90. LVDS DACCLK Drive Circuit coupled and clamped, as shown in Figure 91. Figure 91. TTL or CMOS DACCLK Drive Circuit Figure 92. It is important to use CVDD18 and CVSS for the degrade the DAC performance. Figure 92. DACCLK VCM Generator Circuit

Figure 103. Simplified Internal Clock Routing

Figure 104. Power Supply Input for AD973x Evaluation Board, Rev. F

FROM THE CONNECTOR BIT ORDER. Figure 105. Circuitry Local to AD973x, Evaluation Board, Rev. F

FROM THE CONNECTOR BIT ORDER. Figure 106. High Speed Digital I/O Connector, AD973x Evaluation Board, Rev. F

T1 PIN 2 ON THE REV. C EVAL BOARD. PERFORMANCE FOR IF SIGNAL GENERATION. TYPICAL SIGNAL LEVELS SHOWN FOR 50Ω LOAD. Figure 107. Clock Input and Analog Output, AD973x Evaluation Board, Rev. F

Figure 108. SPI Port Interface, AD973x Evaluation Board, Rev. F

Figure 109. CB Layout Top Placement, AD973x Evaluation Board, Rev. F

Figure 110. PCB Layout Layer 1, AD973x Evaluation Board, Rev. F

Figure 111. PCB Layout Layer 2, AD973x Evaluation Board, Rev. F

Figure 112. PCB Layout Layer 3, AD973x Evaluation Board, Rev. F

Figure 113. PCB Layout Layer 4, AD973x Evaluation Board, Rev. F

Figure 114. PCB Layout Bottom Placement, AD973x Evaluation Board, Rev. F

  1. MATERIAL: FOUR LAYER, FR4 GLASS –EPOXY LAMINATE
  2. PLATED THRU HOLES AND THE CONDUCTIVE PATTERN

ELECTROPLATED WITH .001 INCH MIN. THICK COPPER. COATED WITH SOLDER AND HOT AIR LEVELED. B. MINIMUM ANNULAR RING SURROUNDING HOLES .002 INCH.

  1. WARP AND TWIST +/– .005 INCH PER INCH.
  2. DIMENTIONS: ARE FOR THE FINISHED PART
  3. SOLDER MASK: LIQUID PHOTO IMAGABLE SOLDER MASK
  4. SCREENING: SCREEN COMPONENT OUTLINES AND

PRIMARY AND SECONDARY SIDES (AS REQUIRED). REGISTRATION +/– .005 INCH TOTAL.

  1. SURFACES: PUNCHED OR MACHINED SURFACES 125 MICRO
  2. BREAK ALL SHARP EDGES .015 R MAX.
  3. FABRICATION VENDOR TO ADD UL VENDOR ID NUMBER
  4. DO NOT DRILL. FOR GOLD PLATED SOCKETED VERSION ONLY.

Figure 115. PCB Fabrication Detail, AD973x Evaluation Board, Rev. F

0.43 MAX

0.25 MIN

0.12 MAX

1.00 MAX

0.85 MIN

1.40 MAX

COMPLIANT TO JEDEC STANDARDS MO-205-AE. Figure 116. 160-Lead Chip Scale Package Ball Grid Array [CSP_BGA]

Rev. A | Page 70 of 72 NOTES

Rev. A | Page 71 of 72 NOTES

Rev. A | Page 72 of 72 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D04862-0-9/06(A)