AD9732

AD9732 Data Sheet

Document overview

• Manufacturer or author: Ernie
• PDF pages: 11

Technical content

REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9732 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 10-Bit, 200 MSPS D/A Converter FUNCTIONAL BLOCK DIAGRAM CONTROL AMPINTERNAL VOLTAGE REFERENCE SWITCH NETWORK DECODERS AND DRIVERS REGISTER AD9732 D10 CLOCK R SET DIGITAL +VS CONTROL AMP IN REF OUT CONTROL AMP OUT REF IN IOUT IOUT ANALOG RETURN TTL DRIVE LOGIC

FEATURES

200 MSPS Throughput Rate

3.3 V PECL Digital Input

65 dB SFDR @ 2 MHz A OUT, 200 MSPS/54 dB @ 40 MHz AOUT, 200 MSPS Low Power: 305 mW Fast Settling: 5 ns to 1/2 LSB Low Glitch Energy: 6 pVs Internal Reference 28-Lead SSOP Packaging

APPLICATIONS

The AD9732 is a 10-bit, 200 MSPS, bipolar D/A converter that is optimized to provide high dynamic performance, yet offers lower power dissipation and a more economical price than pre- vious high speed DAC solutions. The AD9732 was primarily designed for demanding communications systems applications where maximum spurious-free dynamic range (SFDR) is required at high throughput rates. The proliferation of digital communi- cations into base station and high volume subscriber-end mar- kets has created a demand for high performance bipolar DACs delivered at CMOS associated levels of power dissipation and cost. The AD9732 is the answer to that demand. Optimized for direct digital synthesis (DDS) and digital modu- lator waveform reconstruction, the AD9732 provides >50 dB of wideband harmonic suppression over the dc to 80 MHz analog output bandwidth. This signal bandwidth addresses the transmit spectrum in many of the emerging digital communications ap- plications where signal purity is critical. Narrowband ( – 1 MHz window), the AD9732 provides an SFDR of greater than 75 dB. This level of wideband and narrowband ac performance, coupled with its 200 MSPS throughput rate, enables the AD9732 to present outstanding value in the high speed DAC function. The AD9732 is packaged in a 28-lead SSOP and is specified to operate over the extended industrial temperature range of –40 °C to +85°C. Digital inputs and clock are positive-ECL compatible.

–2– REV. A AD9732–SPECIFICATIONS ELECTRICAL CHARACTERISTICS(+VS = +5 V, ENCODE = 125 MSPS, R SET = 1.95 kV (for 20 mA IOUT) unless otherwise noted) Test AD9732BRS Parameter Temp Level Min Typ Max Units THROUGHPUT RATE +25 °C IV 165 200 MHz RESOLUTION 10 Bits DC ACCURACY Differential Nonlinearity +25 °C I 0.25 1 LSB Full VI 0.36 1 LSB Integral Nonlinearity +25 °C I 0.6 1.5 LSB Full VI 0.7 1.5 LSB INITIAL OFFSET ERROR Zero-Scale Offset Error +25 °C I 35 70 mA Full VI 40 100 mA Full-Scale Gain Error1 +25°C I 2.5 5 % FS Full VI 2.5 5 % FS Offset Drift Coefficient V 0.04 mA/°C REFERENCE/CONTROL AMP Internal Reference Voltage 2 +25°C I 3.65 3.75 3.85 V Internal Reference Voltage Drift Full IV 150 mV/°C Internal Reference Output Current 3 Full VI –50 +500 mA Amplifier Input Impedance +25 °CI 5 0 k W Amplifier Bandwidth +25 °C I 2.5 MHz REFERENCE INPUT4 Reference Input Impedance +25 °C V 4.6 k W Reference Multiplying Bandwidth 5 +25°C V 75 MHz OUTPUT PERFORMANCE Output Current4, 6 Full V 20 mA Output Compliance Full IV 2 5.75 V Output Resistance +25 °C V 240 W Output Capacitance +25 °CV 5 p F Voltage Settling Time to 1/2 LSB (t ST)7 +25°C V 4.75 ns Propagation Delay (t PD)8 +25°C V 2.7 ns Glitch Impulse9 Full V 5.9 pVs Output Slew Rate10 Full V 450 V/ ms Output Rise Time10 Full V 1 ns Output Fall Time10 Full V 1 ns DIGITAL INPUTS Logic “1” Voltage Full VI 2.4 V Logic “0” Voltage Full VI 1.6 V Logic “1” Current +25 °C I 1.7 10 mA Logic “0” Current +25 °C I –1 0.01 1 mA Input Capacitance Full V 2 pF Minimum Data Setup Time (t S)11 +25°C IV 0.7 1.5 ns Full IV 1 1.5 ns Minimum Data Hold Time (t H)12 +25°C IV 0.7 1.5 ns Full IV 1 1.5 ns Clock Pulsewidth Low (pw MIN) +25 °CI V 2 n s Clock Pulsewidth High (pw MAX) +25 °CI V 2 n s POWER SUPPLY13 Digital +V Supply Current +25 °C I 15 25 35 mA Full VI 10 40 mA Analog +V Supply Current +25 °C I 10 20 30 mA Full VI 10 30 mA Power Dissipation14 +25°C V 305 mW Full V 350 mW Power Supply Rejection Ratio (PSRR) +25 °C V 200 mA/V

–3–REV. A AD9732 Test AD9732BRS Parameter Temp Level Min Typ Max Units SFDR PERFORMANCE (Wideband) 15

2 MHz AOUT +25°CV 6 6 d B

10 MHz AOUT +25°CV 6 3 d B

20 MHz AOUT +25°CV 5 7 d B

40 MHz AOUT +25°CV 5 2 d B

2 MHz AOUT (Clock = 165 MHz) +25 °CV 6 3 d B

10 MHz AOUT (Clock = 165 MHz) +25 °CV 6 2 d B

20 MHz AOUT (Clock = 165 MHz) +25 °CV 5 6 d B

40 MHz AOUT (Clock = 165 MHz) +25 °CV 5 1 d B

65 MHz AOUT (Clock = 165 MHz) +25 °CV 4 8 d B

65 MHz AOUT (Clock = 200 MHz) +25 °CV 4 5 d B

80 MHz AOUT (Clock = 200 MHz) +25 °CV 4 3 d B

SFDR PERFORMANCE (Narrowband) 15

2 MHz; 2 MHz Span +25 °CV 7 7 d B

25 MHz; 2 MHz Span +25 °CV 6 5 d B

10 MHz; 5 MHz Span (Clock = 200 MHz) +25 °CV 7 0 d B

INTERMODULATION DISTORTION 16 F1 = 800 kHz, F2 = 900 kHz to Nyquist +25 °CV 6 9 d B F1 = 800 kHz, F2 = 900 kHz, Narrowband (2 MHz) +25 °CV 6 1 d B NOTES 1Measured as an error in ratio of full-scale current to current through R SET (640 mA nominal); ratio is nominally 32. DAC load is virtual ground. 2Internal reference voltage is tested under load conditions specified in Internal Reference Output Current specification. 3Internal reference output current defines load conditions applied during Internal Reference Voltage test. 4Full-scale current variations among devices are higher when driving REFERENCE IN directly. 5Frequency at which a 3 dB change in output of DAC is observed; R L = 50 W ; 100 mV modulation at midscale. 6Based on I FS = 32 ([CONTROL AMP IN – (+V S)]/RSET) when using internal control amplifier. DAC load is virtual ground. 7Measured as voltage settling at midscale transition to 0.1%; R L = 50 W . 8Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal. 9Peak glitch impulse is measured as the largest area under a single positive or negative transient. 10Measured with R L = 50 W and DAC operating in latched mode. 11Data must remain stable for a specified time prior to rising edge of CLOCK. 12Data must remain stable for a specified time after rising edge of CLOCK. 13Supply voltages should remain stable with – 5% for nominal operation. 14Power dissipation calculation includes current through a 50 W load. 15SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencie s in the output spectrum window. The frequency span dc to Nyquist unless otherwise noted. 16Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products created will manifest themselves at sum and difference frequencies of the two tones. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level I 100% production tested. II 100% production tested at +25 °C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at +25 °C; guaranteed by design and characterization testing for industrial temperature range. ORDERING GUIDE Temperature Package Package Model Range Description Option AD9732BRS –40 °C to +85°C 28-Lead Small Outline (SSOP) RS-28 AD9732/PCB +25 °C Evaluation Board

–4– REV. A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9732 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS* S *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. PIN FUNCTION DESCRIPTIONS Pin Number Name Function 1 D9 (MSB) Most significant data bit of digital input word. 2–9 D8–D1 Eight bits of 10-bit digital input word. 10 D0 (LSB) Least significant data bit of digital input word. 11 CLOCK TTL-compatible edge-triggered latch enable signal for on-board registers. 12, 13 NC No internal connection to this pin. Recommend tie to ground. 14, 15, 28 DIGITAL +V S +5 V supply voltage for digital circuitry. 16, 22, 27 GND Converter Ground.

18 ANALOG +V

S +5 V supply voltage for analog circuitry. 17 R SET Connection for external reference set resistor; nominal 1.96 k W . Full-scale output current = 32 [Control Amp + V S] (Reset). 19 ANALOG RETURN Analog Return. This point and the reference side of the DAC load resistors should be connected to the same potential (Analog +V S).

20 I OUT Analog current output; full-scale current occurs with a digital word input of all “1s”

with external load resistor, output voltage = I OUT (RLOADiRINTERNAL). RINTERNAL is nominally 240 W .

21 I OUTB Complementary analog current output; full-scale current occurs with a digital word

input of all “0s.” 23 REF IN Normally connected to CONTROL AMP OUT (Pin 24). Direct line to DAC current source network. Voltage changes (noise) at this point have a direct effect on the full- scale output current of the DAC. Full-scale current output = 32 (CONTROL AMP IN/ R SET) when using internal amplifier. DAC load is virtual ground. 24 CONTROL AMP OUT Normally connected to REF IN (Pin 23). Output of internal control amplifier, which provides a reference for the current switch network. 25 REF OUT Normally connected to CONTROL AMP IN (Pin 26). Internal voltage reference, nominally 3.75 V. 26 CONTROL AMP IN Normally connected to REF OUT (Pin 25) if not connected to external reference. PIN CONFIGURATION TOP VIEW (Not to Scale) AD9732 NC = NO CONNECT DIGITAL +VS NC NC CLOCK D0 (LSB) D9 (MSB) DIGITAL +VS GND R SET ANALOG +V S ANALOG RETURN IOUT IOUTB DIGITAL +VS GND CONTROL AMP IN REF OUT GND REF IN CONTROL AMP OUT

Figure 1. Timing Diagrams

30 SFDR – dB50

Figure 2. Narrowband SFDR (Clock = 200 MHz) vs. A OUT Figure 3. Narrowband SFDR (Clock = 125 MHz) vs. A OUT Figure 4. Wideband SFDR (200 MHz Clock) vs. A OUT Figure 5. SFDR vs. IOUT Figure 6. SFDR vs. Clock for f CLK/AOUT = 3.125 Figure 7. Typical Differential Nonlinearity Performance

1 TO 3 ON BOARD XTAL OSCILLATOR

2 TO 4 BNC EXTERNAL PECL CLOCK (50V)

4 TO 6 ADD 50V TERMINATION FOR EXTERNAL CLOCK

27 TO 29

30 TO 28

29 TO 32

31 TO 30 SINGLE-ENDED RESISTIVE TERMINATED

Figure 20. Evaluation Board

–11–REV. A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead SSOP (RS-28) 28 15 141 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) PIN 1 SEATING PLANE 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) BSC 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) PRINTED IN U.S.A. C3365a–0–4/99