AD9717BCPZ

AD9714 AD | Alldatasheet

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Technical content

Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters AD9714/AD9715/AD9716/AD9717 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.

FEATURES

Power dissipation @ 3.3 V, 2 mA output 37 mW @ 10 MSPS 80 mW @ 125 MSPS Sleep mode: <3 mW @ 3.3 V Supply voltage: 1.8 V to 3.3 V SFDR to Nyquist 84 dBc @ 1 MHz output 75 dBc @ 10 MHz output AD9717 NSD @ 1 MHz output, 125 MSPS, 2 mA: −151 dBc/Hz Differential current outputs: 1 mA to 4 mA Two on-chip auxiliary DACs CMOS inputs with single-port operation Output common mode: adjustable 0 V to 1.2 V Small footprint 40-lead LFCSP Pb-free package

APPLICATIONS

Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators GENERAL DESCRIPTION The AD9714/AD9715/AD9716/AD9717 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC® converters are optimized for the transmit signal path of commu- nication systems. All the devices share the same interface, LFCSP package, and pinout, providing an upward or downward compo- nent selection path based on performance, resolution, and cost. The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and dc performance and support update rates up to 125 MSPS. The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9714/AD9715/AD9716/AD9717 make them well-suited for portable and low power applications. PRODUCT HIGHLIGHTS 1. Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 35 mW at 125 MSPS with a 1.8 V supply. Sleep and power-down modes are provided for low power idle periods. 2. CMOS Clock Input. High speed, single-ended CMOS clock input supports 125 MSPS conversion rate. 3. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows for easy interfacing to other components that accept common- mode levels greater than 0 V .

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 2 of 48 TABLE OF CONTENTS Correcting for Nonideal Performance of Quadrature Modifying the Evaluation Board to Use the ADL5370

REVISION HISTORY

8/08—Revision 0: Initial Version

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 3 of 48 FUNCTIONAL BLOCK DIAGRAM I DAC Q DAC AUX1DAC AUX2DAC BAND GAP CLOCK DIST 10kΩ RSET 16kΩ RSET 16kΩ IREF 100µA RCM 1kΩ TO 250Ω RCM 1kΩ TO 250Ω 500Ω 500Ω 500Ω 500Ω SPI INTERFACE

1 INTO 2

Q DATA1.8V LDO 1V AD9714/AD9715/ AD9716/AD9717 07265-001 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN DB11 DB10 DB9 DB8 DVDDIO DVSS DVDD DB7 DB6 DB5 DB12 DB13 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJQ/AUXQ FSADJI/AUXI CMLI DB4 DB3 DB2 DB1 DB0 (LSB) DCLKIO CVDD CLKIN CVSS CMLQ Figure 1.

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 4 of 48 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V , DVDD = 3.3 V , DVDDIO = 3.3 V , CVDD = 3.3 V , IOUTFS = 2 mA, maximum sample rate, unless otherw ise noted. Table 1. Parameter AD9714 AD9715 AD9716 AD9717 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max RESOLUTION 8 10 12 14 Bits A C C U R A C Y @ 3 . 3 V Differential Nonlinearity (DNL) Precalibration ±0.02 ±0.08 ±0.4 ±1.7 LSB Postcalibration ±0.003 ±0.01 ±0.2 ±1.0 LSB Integral Nonlinearity (INL) Precalibration ±0.025 ±0.13 ±0.4 ±1.8 LSB Postcalibration ±0.01 ±0.05 ±0.3 ±1.3 LSB A C C U R A C Y @ 1 . 8 V Differential Nonlinearity (DNL) Precalibration ±0.02 ±0.08 ±0.4 ±1.2 LSB Postcalibration ±0.005 ±0.01 ±0.2 ±1.0 LSB Integral Nonlinearity (INL) Precalibration ±0.025 ±0.12 ±0.4 ±1.5 LSB Postcalibration ±0.02 ±0.05 ±0.25 ±1.1 LSB MAIN DAC OUTPUTS Offset Error −1 0 +1 −1 0 +1 −1 0 +1 −1 0 +1 mV G a i n E r r o r Internal Reference −2 +2 −2 +2 −2 +2 −2 +2 % of FSR Full-Scale Output Current1 VCC = 3.3 V 1 2 4 1 2 4 1 2 4 1 2 4 mA Output Resistance 200 200 200 200 MΩ Crosstalk, Q DAC to I DAC fOUT = 30 MHz 97 97 97 97 dB fOUT = 60 MHz 78 78 78 78 dB MAIN DAC TEMPERATURE DRIFT Offset 0 0 0 0 ppm/°C Gain ±40 ±40 ±40 ±40 ppm/°C Reference Voltage ±25 ±25 ±25 ±25 ppm/°C A U X D A C O U T P U T S Resolution 10 10 10 10 Bits Full-Scale Output Current (Current Sourcing Mode) 125 125 125 125 μA Voltage Output Mode VSS VDD V SS VDD V SS VDD V SS VDD V Output Compliance Range (Sourcing 1 mA) VSS VDD − 0.25 VSS VDD − 0.25 VSS VDD − 0.25 VSS VDD − 0.25 V Output Compliance Range (Sinking 1 mA) VSS + 0.25 V DD V SS + 0.25 V DD V SS + 0.25 V DD V SS + 0.25 V DD V Output Resistance in Current Output Mode VSS to +1 V 1 1 1 1 MΩ AUX DAC Monotonicity Guaranteed 10 10 10 10 Bits REFERENCE OUTPUT Output Resistance 10 10 10 10 kΩ REFERENCE INPUT Input Resistance 1 1 1 1 MΩ

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 5 of 48 Parameter AD9714 AD9715 AD9716 AD9717 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max D A C M A T C H I N G Gain Matching −1 +1 −1 +1 −1 +1 −1 +1 % FSR ANALOG SUPPLY VOLTAGES DIGITAL SUPPLY VOLTAGES POWER CONSUMPTION @ 3.3 V fDAC = 125 MSPS, IF = 12.5 MHz 86 86 86 86 mW IAVDD 10 10 10 10 mA IDVDD 2 0 0 0 0 mA IDVDDIO 3 11 11 11 11 mA ICVDD 3 3 3 3 mA Power-Down Mode with Clock 50 50 50 50 mW Power-Down Mode No Clock 1.5 1.5 1.5 1.5 mW Power Supply Rejection Ratio −0.04 −0.04 −0.04 −0.04 % FSR/V POWER CONSUMPTION @ 1.8 V fDAC = 125 MSPS, IF = 12.5 MHz 35 35 35 35 mW IAVDD 10 10 10 10 mA IDVDD + IDVDDIO 8 8 8 8 mA ICVDD 1.5 1.5 1.5 1.5 mA Power-Down Mode with Clock 12 12 12 12 mW Power-Down Mode No Clock 850 850 850 850 μW Power Supply Rejection Ratio −0.001 −0.001 −0.001 −0.001 % FSR/V OPERATING RANGE –40 +25 +85 –40 +25 +85 –40 +25 +85 –40 +25 +85 °C 1 Based on a 10 kΩ external resistor. 2 Bypass only. 3 LDO on.

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 6 of 48 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V , DVDD = 3.3 V , DVDDIO = 3.3 V , CVDD = 3.3 V , IOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DAC CLOCK INPUT (CLKIN) VIH 2.1 3 V VIL 0 0.9 V Maximum Clock Rate 125 MSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 25 MHz Minimum Pulse Width High 20 ns Minimum Pulse Width Low 20 ns INPUT DATA

1.8 V Q-Channel or DCLKIO Falling Edge

Setup 0.25 ns Hold 1.2 ns I-Channel or DCLKIO Rising Edge Setup 0.13 ns Hold 1.1 ns

3.3 V Q-Channel or DCLKIO Falling Edge

Setup −0.2 ns Hold 1.5 ns I-Channel or DCLKIO Rising Edge Setup −0.2 ns Hold 1.6 ns VIH 2.1 3 V VIL 0 0.9 V

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 7 of 48 AC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V , DVDD = 3.3 V , DVDDIO = 1.8 V , CVDD = 3.3 V , IOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 3. Parameter AD9714 AD9715 AD9716 AD9717 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 125 MSPS, fOUT = 10 MHz 75 82 83 84 dBc fDAC = 125 MSPS, fOUT = 50 MHz 60 61 62 63 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 125 MSPS, fOUT = 10 MHz 86 87 88 89 dBc fDAC = 125 MSPS, fOUT = 50 MHz 71 71 71 71 dBc NOISE SPECTRAL DENSITY (NSD) EIGHT- TONE, 500 kHz TONE SPACING fDAC = 125 MSPS, fOUT = 10 MHz −129 −141 −149 −152 dBc/Hz fDAC = 125 MSPS, fOUT = 50 MHz −123 −135 −137 −141 dBc/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 61.44 MSPS, fOUT = 20 MHz −71 −71 −71 −71 dBc fDAC = 122.88 MSPS, fOUT = 30 MHz −72 −72 −72 −72 dBc TMIN to TMAX, AVDD = 1.8 V , DVDD = 3.3 V , DVDDIO = 1.8 V , CVDD = 3.3 V , IOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter AD9714 AD9715 AD9716 AD9717 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 125 MSPS, fOUT = 10 MHz 75 78 79 80 dBc fDAC = 125 MSPS, fOUT = 50 MHz 55 56 57 58 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 125 MSPS, fOUT = 10 MHz 79 80 84 85 dBc fDAC = 125 MSPS, fOUT = 50 MHz 53 53 53 53 dBc NOISE SPECTRAL DENSITY (NSD) EIGHT- TONE, 500 kHz TONE SPACING fDAC = 125 MSPS, fOUT = 10 MHz −132 −141 −146 −148 dBc/Hz fDAC = 125 MSPS, fOUT = 50 MHz −126 −131 −131 −132 dBc/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 61.44 MSPS, fOUT = 20 MHz −68 −68 −68 −68 dBc fDAC = 122.88 MSPS, fOUT = 30 MHz −68 −68 −68 −68 dBc

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 8 of 48 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS −0.3 V to +3.9 V DVDD to DVSS −0.3 V to +2.1 V AVSS to DVSS, CVSS −0.3 V to +0.3 V DVSS to AVSS, CVSS −0.3 V to +0.3 V CVSS to AVSS, DVSS −0.3 V to +0.3 V VREF, FSADJQ, FSADJI, CMLQ, CMLI to AVSS −0.3 V to AVDD + 0.3 V QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN, RLIP, RLIN to AVSS −1.0 V to AVDD + 0.3 V D13 to D0, CS, SCLK, SDIO, SDO, RESET to DVSS −0.3 V to DVDD + 0.3 V CLKIN to CVSS −0.3 V to CVDD + 0.3 V CS, SCLK, SDIO, SDO to DVSS –0.3 V to DVDD + 0.3 V Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Table 6. Package Type θJA Unit 40-Lead LFCSP (With No Airflow Movement) 29.8 °C/W ESD CAUTION

23 QOUTP

24 RLQP

25 AVSS

26 AVDD

27 RLIP

28 IOUTP

29 IOUTN

30 RLIN

22 QOUTN

21 RLQN

1. THE HEAT SINK PAD IS CONNECTED TO AVSS AND

SHOULD BE SOLDERED TO THE GROUND PLANE. Figure 2. AD9717 Pin Configuration Table 7. AD9717 Pin Function Descriptions 1 to 4 DB[11:8] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). 7 DVDD Digital Core Supply Voltage (1.8 V). Provides a 1.8 V output when the internal LDO regulator is enabled. 8 to 14 DB[7:1] Digital Inputs. 15 DB0 (LSB) Digital Input (LSB). 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. 21 RLQN Load Resistor (500 Ω) to the CMLQ Pin. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP Load Resistor (500 Ω) to the CMLQ Pin. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RLIP Load Resistor (500 Ω) to the CMLI Pin. 28 IOUTP Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 29 IOUTN I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. 31 CMLI I DAC Output Common-Mode Level. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust for Q DAC. Connect to AVSS through a resistor. 33 FSADJI/AUXI Full-Scale Current Output Adjust for I DAC. Connect to AVSS through a resistor. reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 10 of 48 Pin No. Mnemonic Description 35 RESET/PINMD Reset. In SPI mode, pulse RESET high to reset SPI registers to default values. Pin Mode. A constant Logic 1 puts the device into pin mode. 36 SCLK/CLKMD Serial Clock. Clock input for serial port in spi mode Clock Mode. In pin mode, CLKMD determines phase of internal retiming clock. DCLKIO = CLKIN: Tie to 0. DCLKIO ≠ CLKIN: Pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output. Bidirectional data line for serial port in spi mode. Data Format. In pin mode, FORMAT determines data format of digital data. 38 CS/PWRDN Chip Select. Active low chip select in spi mode. Power Down. In pin mode, PWRDN powers down the device except for the SPI port. 39 DB13 (MSB) Digital Input (MSB). 40 DB12 Digital Input. Heat Sink Pad The heat sink pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at package corners is connected to this pad.

27 RL2P

1. THE HEAT SINK PAD IS CONNECTED TO AVSS AND

SHOULD BE SOLDERED TO THE GROUND PLANE. Figure 3. AD9716 Pin Configuration Table 8. AD9716 Pin Function Descriptions 1 to 4 DB[9:6] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). 7 DVDD Digital Core Supply Voltage (1.8 V). Provides a 1.8 V output when in internal LDO regulator is enabled. 8 to 12 DB[5:1] Digital Inputs. 13 DB0 (LSB) Digital Input (LSB). 14,15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input Clock. Used to clock data in from digital source. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. 21 RLQN Load Resistor (500 Ω) to the CMLQ Pin. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP Load Resistor (500 Ω) to the CMLQ Pin. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RL2P Load Resistor (500 Ω) to the CMLI Pin. 28 IOUTP Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 29 IOUTN I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. 31 CMLI I DAC Output Common-Mode Level. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust for Q DAC. Connect to AVSS through a resistor. 33 FSADJI/AUXI Full-Scale Current Output Adjust for I DAC. Connect to AVSS through a resistor. reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 12 of 48 Pin No. Mnemonic Description 35 RESET/PINMD Reset in SPI Mode. Pulse high to reset SPI registers to default values. Pin Mode. A constant Logic 1 puts the device into pin mode. 36 SCLK/CLKMD Serial Clock. Clock input for serial port in spi mode. Clock Mode. In pin mode, CLKMD determines phase of internal retiming clock. DCLKIO = CLKIN: Tie to 0. DCLKIO ≠ CLKIN: Pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output. Bidirectional data line for serial port in spi mode. Data Format. In pin mode, FORMAT determines data format of digital data. 38 CS/PWRDN Chip Select. Active low chip select in spi mode. Power Down. In pin mode, PWRDN powers down the device except for the SPI port. 39 DB11 (MSB) Digital Input (MSB). 40 DB10 Digital Input. Heat Sink Pad The heat sink pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at package corners is connected to this pad.

24 RL1P

27 RL2N

28 IOUTN

29 IOUTP

21 RL1N

1. THE HEAT SINK PAD IS CONNECTED TO AVSS AND

SHOULD BE SOLDERED TO THE GROUND PLANE. Figure 4. AD9715 Pin Configuration Table 9. AD9715 Pin Function Descriptions 1 to 4 DB[7:4] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). 7 DVDD Digital Core Supply Voltage (1.8 V). Provides a 1.8 V output when in internal LDO regulator is enabled. 8 to 10 DB[3:1] Digital Inputs. 11 DB0 (LSB) Digital Input (LSB). 12 to 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input Clock. Used to clock data in from digital source. 17 CVDD Sampling Clock Supply Voltage (1 .8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. 21 RL1N Load Resistor (500 Ω) to the CMLQ Pin. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RL1P Load Resistor (500 Ω) to the CMLQ Pin. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RL2N Load Resistor (500 Ω) to the CMLI Pin. 28 IOUTN Complementary I DAC Current Output. Full-scal e current is sourced when all data bits are 0s. 29 IOUTP I DAC Current Output. Full-scale curren t is sourced when all data bits are 1s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. 31 CMLI I DAC Output Common-Mode Level. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust for Q DAC. Connect to AVSS through a resistor. internal on-chip, RSET, is enabled. 33 FSADJI/AUXI Full-Scale Current Output Adjust for I DAC. Connect to AVSS through a resistor. reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 14 of 48 Pin No. Mnemonic Description 35 RESET/PINMD Reset in SPI Mode. Pulse high to reset SPI registers to default values. Pin Mode. A constant Logic 1 puts device into pin mode. 36 SCLK/CLKMD Serial Clock. Clock input for serial port in spi mode. Clock Mode. In pin mode, CLKMD determines phase of internal retiming clock. DCLKIO = CLKIN: Tie to 0. DCLKIO ≠ CLKIN: Pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output. Bidirectional data line for serial port in spi mode. Data Format. In pin mode, FORMAT determines data format of digital data. 38 CS/PWRDN Chip Select. Active low chip select in spi mode. Power Down. In pin mode, PWRDN powers down the device except for the SPI port. 39 DB9 (MSB) Digital Input (MSB). 40 DB8 Digital Input. Heat Sink Pad The heat sink pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at package corners is connected to this pad.

1. THE HEAT SINK PAD IS CONNECTED TO AVSS AND

SHOULD BE SOLDERED TO THE GROUND PLANE. Figure 5. AD9714 Pin Configuration Table 10. AD9714 Pin Function Descriptions 1 to 4 DB[5:2] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). 7 DVDD Digital Core Supply Voltage (1.8 V). Provides a 1.8 V output when the internal LDO regulator is enabled. 9 DB0 (LSB) Digital Input (LSB). 10 to 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input Clock. Used to clock data in from digital source. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. 20 CMLQ Q DAC Output Common-Mode Level. 21 RL1N Load Resistor (500 Ω) to the CMLQ Pin. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RL1P Load Resistor (500 Ω) to the CMLQ Pin. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RL2N Load Resistor (500 Ω) to the CMLI Pin. 28 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 29 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. 31 CMLI I DAC Output Common-Mode Level. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust for Q DAC. Connect to AVSS through a resistor. internal on-chip, RSET, is enabled. 33 FSADJI/AUXI Full-Scale Current Output Adjust for I DAC. Connect to AVSS through a resistor. reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 16 of 48 Pin No. Mnemonic Description 35 RESET/PINMD Reset in SPI Mode. Pulse high to reset SPI registers to default values. Pin Mode. A constant Logic 1 puts device into pin mode. 36 SCLK/CLKMD Serial Clock. Clock input for serial port in spi mode. Clock Mode. In pin mode, CLKMD determines phase of internal retiming clock. DCLKIO = CLKIN: Tie to 0. DCLKIO ≠ CLKIN: Pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output. Bidirectional data line for serial port in spi mode. Data Format. In pin mode, FORMAT determines data format of digital data. 38 CS/PWRDN Chip Select. Active low chip select in spi mode. Power Down. In pin mode, PWRDN powers down the device except for the SPI port. 39 DB7 (MSB) Digital Input (MSB). 40 DB6 Digital Input. Heat Sink Pad The heat sink pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at package corners is connected to this pad.

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 29 of 48 TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of zero. For I OUTP, 0 mA output is expected when the inputs are all 0. For IOUTN, 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range Output compliant range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temp er atu re D r i ft Temperature drift is specified as the maximum change from the ambient value (25°C) to the value at either T MIN or TMAX. For offset and gain drift, the drift is reported in ppm of full- scale range per degree Celsius (ppm FSR/°C). For reference drift, the drift is reported in parts per million per degree Celsius (ppm/°C). Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

Figure 76. Simplified Block Diagram weighted fractions of the current sources of the middle bits. the high output impedance of the DAC (that is, >200 MΩ). ments to reduce distortion contributed by the switching transient. the differential current switches. SET, connected to its full-scale adjust pin (FSADJ).

instruction byte into the AD9714/AD9715/AD9716/AD9717. or a data transfer cycle, none of the present data is written. last bit of each transfer byte. The instruction byte contains the information shown in Table 11. indicates a read operation. Logic 0 indicates a write operation. number of bytes to be transferred during the data transfer cycle. Table 12. Byte Transfer Count on the LSBFIRST bit (Register 0x00, Bit 6). AD9715/AD9716/AD9717 on the falling edge of SCLK. An active low input starts and gates a communications cycle. should stay low during the entire communications cycle.

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 32 of 48 MSB/LSB TRANSFERS The serial port of the AD9714/AD9715/AD9716/AD9717 can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSBFIRST bit (Register 0x00, Bit 6). The default is MSB first (LSBFIRST = 0). When LSBFIRST = 0 (MSB first), the instruction and data bytes must be written from the most significant bit to the least significant bit. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow in order from a high address to a low address. In MSB first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communications cycle. When LSBFIRST = 1 (LSB first), the instruction and data bytes must be written from the least significant bit to the most signifi- cant bit. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle. The serial port controller data address of the AD9714/AD9715/ AD9716/AD9717 decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB first mode is active. The serial port controller address increments from the data address written toward 0x1F for multibyte I/O operations if the LSB first mode is active. SERIAL PORT OPERATION The serial port configuration of the AD9714/AD9715/AD9716/ AD9717 is controlled by Register 0x00. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register can occur during the middle of the communications cycle. Care must be taken to compensate for this new configu- ration for the remaining bytes of the current communications cycle. The same considerations apply to setting the software reset, RESET (Register 0x00, Bit 5). All registers are set to their default values except Register 0x00, which remains unchanged. Use of single-byte transfers or initiating a software reset is recommended when changing serial port configurations to prevent unexpected device behavior. PIN MODE The AD9714/AD9715/AD9716/AD9717 can also be operated without ever writing to the serial port. With RESET/PINMD pin tied high, the SCLK pin becomes CLKMD to provide for clock mode control (see the Retimer section), the former SDIO pin selects the input data format, and the CS pin serves to power down the device. Operation is otherwise exactly as defined by the default register values in Table 12, therefore external resistors at FSADJI and FSADJQ are needed to set the DAC currents, and both DACs are active. This is also a convenient quick checkout mode. DAC currents can be externally adjusted in pin mode by sourcing or sinking currents at the FSADJI/AUXI and FSADJQ/AUXQ pins as desired with the fixed resistors installed. An op amp output with appropriate series resistance would be one of many possibilities. This has the same effect as changing the resistor value. Place at least 10 kΩ resistors in series right at the DAC to guard against accidental short circuits and noise modulation. The REFIO pin can be adjusted ±25% in a similar manner, if desired.

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 33 of 48 SPI REGISTER MAP Table 13. Name Addr Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Control 0x00 0x00 LSBFIRST RESET LNGINS Power Down 0x01 0x40 LDOOFF LDOSTAT PWRDN Q DACOFF I DACOFF QCLKOFF ICLKOFF EXTREF Data Control 0x02 0x34 TWOS IFIRST IRISING SIMULBIT DCI_EN DCOSGL DCODBL I DAC Gain 0x03 0x00 I DACGAIN[5:0] IRSET 0x04 0x00 IRSETEN IRSET[5:0] IRCML 0x05 0x00 IRCMLEN IRCML[5:0] Q DAC Gain 0x06 0x00 Q DACGAIN[5:0] QRSET 0x07 0x00 QRSETEN QRSET[5:0] QRCML 0x08 0x00 QRCMLEN QRCML[5:0] AUXDAC Q 0x09 0x00 QAUXDAC[7:0] AUX CTLQ 0x0A 0x00 QAUXEN QAUXRNG[1:0] QAUXOFS[2:0] QAUXDAC[9:8] AUXDAC I 0x0B 0x00 IAUXDAC[7:0] AUX CTLI 0x0C 0x00 IAUXEN IAUXRNG[1:0] IAUXOFS[2:0] IAUXDAC[9:8] Reference Resistor 0x0D 0x00 RREF[5:0] Cal Control 0x0E 0x00 PRELDQ PRELDI CALSELQ CALSELI CALCLK DIVSEL[2:0] Cal Memory 0x0F 0x00 CALSTATQ CALSTATI CALMEMQ[1:0] CALMEMI[1:0] Memory Address 0x10 0x00 MEMADDR[5:0] Memory Data 0x11 0x34 MEMDATA[5:0] Memory R/W 0x12 0x00 CALRSTQ CALRSTI CALEN SMEMWR SMEMRD UNCALQ UNCALI CLKMODE 0x14 0x00 CLKMODEQ[1:0] SEARCHING REACQUIRE CLKMODEN CLKMODEI[1:0] Version 0x1F N/A VERSION[7:0]

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 34 of 48 SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 14. Register Address Bit Name Function SPI Control 0x00 6 LSBFIRST 0: MSB first, per SPI standard 1: LSB first, per SPI standard Note that the user must always change the LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit order errors

5 RESET Execute software reset of SPI and controllers, reload default register values except

1: Set software reset; write 0 on the next (or any following) cycle to release the reset

4 LNGINS 0: The SPI instruction word utilizes a 5-bit address

1: The SPI instruction word utilizes a 13-bit address Power Down 0x01 7 LDOOFF 1: turn core LDO voltage regulator off

6 LDOSTAT 0: Indicates core LDO voltage regulator is off

1: Indicates core LDO voltage regulator is on

5 PWRDN 1: Powers down all analog and digital circuitry except for SPI logic

4 Q DACOFF 1: Turns off Q DAC output current

3 I DACOFF 1: Turns off I DAC output current

2 QCLKOFF 1: Turns off Q DAC clock

1 ICLKOFF 1: Turns off I DAC clock

0 EXTREF 1: Powers down internal voltage reference (external reference required)

Data Control 0x02 7 TWOS 0: Unsigned binary input data format 1: Twos complement input data format

5 IFIRST 0: Pairing of data—Q first of pair on data input pads

1: Pairing of data—I first of pair on data input pads (default)

4 IRISING 0: Q data latched on DCLKIO rising edge

1: I data latched on DCLKIO falling edge (default)

3 SIMULBIT 0: Allows simultaneous input and output enable on DCLKIO

1: Disallows simultaneous input and output enable on DCLKIO

2 DCI_EN Controls the use of DCLKIO pad for data clock input

0: Data clock input disabled 1: Data clock input enabled (default)

1 DCOSGL Controls the use of DCLKIO pad for data clock output

0: Data clock output disabled 1: Data clock output enabled; regular strength driver

0 DCODBL Controls the use of DCLKIO pad for data clock output

0: DCOBL data clock output disabled 1: DCOBL data clock output enabled; paralleled with DCOSGL for 2× drive current I DAC Gain 0x03 5:0 I DACGAIN[5:0] DAC I fine gain adjustment; alters the full-scale current as shown in Figure 86 IRSET 0x04 7 IRSETEN 1: Enables the on-chip RSET value to be changed 5:0 IRSET[5:0] Changes the value of the on-chip RSET resistor; this scales the full-scale current of the DAC in ~0.25 dB steps (nonlinear); see Figure 85 000000: RSET = 8 kΩ 100000: RSET = 16 kΩ 111111: RSET = 32 kΩ

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 35 of 48 Register Address Bit Name Function IRCML 0x05 7 IRCMLEN 1: Enables on-chip R CML adjustment 5:0 IRCML[5:0] Changes the value of the on-chip RCML resistor; this adjusts the common-mode level of the DAC output stage 000000: RSET = 250 Ω 100000: RSET = 625 Ω 111111: RSET = 1 kΩ Q DAC Gain 0x06 5:0 Q DACGAIN[5:0] DAC Q fine gain adjust ment; alters the full-scale current as shown in Figure 86 QRSET 0x07 7 QRSETEN 1: Enables on-chip R CML adjustment 5:0 QRSET[5:0] Changes the value of the on-chip RSET resistor; this scales the full-scale current of the DAC in ~0.25 dB steps (nonlinear), see Figure 85 000000: RSET = 8 kΩ 100000: RSET = 16 kΩ 111111: RSET = 32 kΩ QRCML 0x08 7 QRCMLEN 1: Enables on-chip R CML adjustment 5:0 QRCML[5:0] Changes the value of the on-chip RCML resistor; this adjusts the common-mode level of the DAC output stage 000000, R SET = 250 Ω 100000, RSET = 625 Ω 111111, RSET = 1 kΩ AUXDAC Q 0x09 7:0 QAUXDAC[7:0] AUXDAC Q output voltage adjustment word LSBs 0x3FF: Sets AUXDAC Q output to full scale 0x200: Sets AUXDAC Q output to midscale 0x000: Sets AUXDAC Q output to bottom of scale AUX CTLQ 0x0A 7 QAUXEN 1: enables AUXDAC Q 6:5 QAUXRNG[1:0] 00: Sets AUXDAC Q output voltage range to 2 V 01: Sets AUXDAC Q output voltage range to 1.5 V 10: Sets AUXDAC Q output voltage range to 1.0 V 11: Sets AUXDAC Q output voltage range to 0.5 V 4:2 QAUXOFS[2:0] 000: Sets AUXDAC Q top of range to 1.0 V 001: Sets AUXDAC Q top of range to 1.5 V 010: Sets AUXDAC Q top of range to 2.0 V 011: Sets AUXDAC Q top of range to 2.5 V 100: Sets AUXDAC Q top of range to 2.9 V 1:0 QAUXDAC[9:8] AUXDAC Q output voltage adjustment word MSBs AUXDAC I 0x0B 7:0 IAUXDAC[7:0] AUXDAC I output voltage adjustment word LSBs 0x3FF: Sets AUXDAC I output to full scale 0x200: Sets AUXDAC I output to midscale 0x000: Sets AUXDAC I output to bottom of scale AUX CTLI 0x0C 7 IAUXEN 1: enables AUXDAC I 6:5 IAUXRNG[1:0] 00: Sets AUXDAC I output voltage range to 2 V 01: Sets AUXDAC I output voltage range to 1.5 V 10: Sets AUXDAC I output voltage range to 1.0 V 11: Sets AUXDAC I output voltage range to 0.5 V 4:2 IAUXOFS[2:0] 000: Sets AUXDAC I top of range to 1.0 V 001: Sets AUXDAC I top of range to 1.5 V 010: Sets AUXDAC I top of range to 2.0 V 011: Sets AUXDAC I top of range to 2.5 V 100: Sets AUXDAC I top of range to 2.9 V 1:0 IAUXDAC[9:8] AUXDAC I output voltage adjustment word MSBs Reference Resistor 0x0D 5:0 RREF[5:0] Permits an adjustment of the on-chip reference voltage and output at REFIO (see Figure 84) 000000: Sets the value of RREF to 8 kΩ, VREF = 0.8 V 100000: Sets the value of RREF to 10 kΩ, VREF = 1.0 V 111111: Sets the value of RREF to 12 kΩ, VREF = 1.2 V

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 36 of 48 Register Address Bit Name Function Cal Control 0x0E 7 PRELDQ 0: Preload Q DAC calibration reference set to 32 1: Preload Q DAC calibration reference set by user (Cal Address 1)

6 PRELDI 0: Preload I DAC calibration reference set to 32

1: Preload I DAC calibration reference set by user (Cal Address 1)

5 CALSELQ 1: Select Q DAC self-calibration

4 CALSELI 1: Select I DAC self-calibration

3 CALCLK 1: Calibration clock enabled

2:0 DIVSEL[2:0] Calibration clock divide ratio from DAC clock rate 000 = divide by 256; 001 = divide by 128 … 110 = divide by 4; 111 = divide by 2 Cal Memory 0x0F 7 CALSTATQ 1: Calibration of Q DAC complete

6 CALSTATI 1: Calibration of I DAC complete

3:2 CALMEMQ[1:0] Status of Q DAC calibration memory 00: Uncalibrated 01: Self-calibrated 10: User calibrated 1:0 CALMEMI[1:0] Status of I DAC calibration memory 00: Uncalibrated 01: Self-calibrated 10: User calibrated Memory Address 0x10 5:0 MEMADDR[5:0] Address of static memory to be accessed Memory Data 0x11 5:0 MEMDATA[5:0] Data for static memory access Memory R/W 0x12 7 CALRSTQ 1: Clear CALSTATQ

6 CALRSTI 1: Clear CALSTATI

4 CALEN 1: Initiate device self-calibration

3 SMEMWR 1: Write to static memory (calibration coefficients)

2 SMEMRD 1: Read from static memory (calibration coefficients)

1 UNCALQ 1: Reset Q DAC calibration coefficients to default (uncalibrated)

0 UNCALI 1: Reset I DAC calibration coefficients to default (uncalibrated)

CLKMODE 0x14 7:6 CLKMODEQ[1:0] Q datapath retimer clock select output (that is, readback after Q retimer acquires)

4 SEARCHING High indicates internal data path retimer is searching for clock relationship (device

output is not usable while this bit is high)

3 REACQUIRE Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship

2 CLKMODEN 0: CLKMODEI/Q values computed by the two retimers and read back in CLKMODEI[1:0]

and CLKMODEQ[1:0] 1: CLKMODE values set in CLKMODEI[1:0] over-ride both I and Q retimers 1:0 CLKMODEI[1:0] 0: CLKMODEN, read only; clock phase chosen by retimer 1: CLKMODEN, read/write; value in this register sets I and Q clock phases Version 0x1F 7:0 VERSION[7:0] Hardware version of the device

Table 15. Timer Register List CLKMODEQ[1:0] Q datapath retimer clock selected output. Valid after SEARCHING goes low. Searching High indicates the internal data path retimer is searching for clock relationship (DAC is not usable until it is low again). Reacquire Changing this bit from 0 to 1 causes the data path retimer circuit to reacquire the clock relationship. CLKMODEN 0: Uses CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking. 1: Uses CLKMODE value set in CLKMODEI[1:0] for both I and Q retimers (that is, force the retimer). CLKMODEI[1:0] I datapath retimer clock selected output. Valid after searching goes low. If CLKMODEN = 1, a value written to this register overrides both I and Q automatic retimer values. Table 16. CLKMODE Details in the retimer (see Table 16). value is written into CLKMODEI[1:0] and CLKMODEQ[1:0]. synchronizing multiple devices. SCLK pin can be taken low and then high again. and not be allowed to automatically select a phase each time. automatically selected or manually forced.

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 40 of 48 SELF-CALIBRATION The AD9714/AD9715/AD9716/AD9717 have a self-calibration feature that improves the DNL of the device. Performing a self- calibration on the device improves device performance in low frequency applications. The device performance in applications where the analog output frequencies are above 5 MHz are generally influenced more by dynamic device behavior than by DNL, and in these cases, self-calibration is unlikely to provide much benefit. The calibration clock frequency is equal to the DAC clock divided by the division factor chosen by the DIVSEL value. Each calibration clock cycle is between 32 and 2048 DAC input clock cycles, depending on the value of DIVSEL[2:0] (Register 0x0E, Bits[2:0]). The frequency of the calibration clock should be between 0.5 MHz and 4 MHz for reliable calibrations. Best results are obtained by setting DIVSEL[2:0] (Register 0x0E, Bits[2:0]) to produce a calibration clock frequency between these values. Separate self-calibration hardware is included for each DAC. The DACs can be self-calibrated individually or simultaneously. To perform a device self-calibration, the following procedure can be used: 1. Write 0x00 to Register 0x12. This ensures that the UNCALI and UNCALQ bits are reset. 2. Set up a calibration clock between 0.5 MHz and 4 MHz using DIVSEL[2:0] and then enable the calibration clock by setting the CALCLK bit (Register 0x0E, Bit 3). 3. Select the DAC(s) to self-calibrate by setting either Bit 4 (CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Note that each DAC contains independent calibration hardware so they can be calibrated simultaneously. 4. Start self-calibration by setting Bit 4 in Register 0x12. Wait approximately 300 calibration clock cycles. 5. Check if the self-calibration has completed by reading the CALSTATI bit (Bit 6) and CALSTATQ bit (Bit 7) in Register 0x0F. Logic 1 indicates the calibration has completed. 6. When the self-calibration has completed, write 0x00 to Register 0x12. 7. Disable the calibration clock by clearing the CALCLK bit (Register 0x0E, Bit 3). The AD9714/AD9715/AD9716/AD9717 allow reading and writing of the calibration coefficients. There are 32 coefficients in total. The read/write feature of the coefficients can be useful for improving the results of the self-calibration routine by averaging the results of several self-calibration cycles and loading the averaged results back into the device. To read the calibration coefficients, use the following steps: 1. Select which DAC core to read by setting either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Write the address of the first coefficient (0x01) to Register 0x10. 2. Set the SMEMRD bit (Register 0x12, Bit 2 ) by writing 0x04 to Register 0x12. 3. Read the 6-bit value of the first coefficient by reading the contents of Register 0x11. 4. Clear the SMEMRD bit by writing 0x00 to Register 0x12. 5. Repeat Step 2 through Step 4 for each of the remaining 31 coefficients by incrementing the address by one for each read. 6. Deselect the DAC core by clearing either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. To write the calibration coefficients to the device, use the following steps: 1. Select which DAC core to write by setting either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. 2. Set the SMEMWR bit (Register 0x12, Bit 3) by writing 0x08 to Register 0x12. 3. Write the address of the first coefficient (0x01) to Register 0x10. 4. Write the value of the first coefficient to Register 0x11. 5. Repeat Step 2 through Step 4 for each of the remaining 31 coefficients by incrementing the address by one for each write. 6. Clear the SMEMWR bit by writing 0x00 to Register 0x12. 7. Deselect the DAC core by clearing either Bit 4 (CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E.

and/or a low output impedance. cost and low power consumption are primary concerns. Figure 89. Differential Output Using a Transformer imately half the signal power is dissipated across RDIFF. Figure 90. The AD9714/AD9715/AD9716/AD9717 are config-

1 FS FB

Figure 90. Single-Supply Single-Ended Buffer

AD9714/AD9715/AD9716/AD9717 Rev. 0 | Page 47 of 48 MODIFYING THE EVALUATION BOARD TO USE THE ADL5370 ON-BOARD QUADRATURE MODULATOR The evaluation board contains an Analog Devices, Inc., ADL5370 quadrature modulator. The AD9714/AD9715/ AD9716/AD9717 and the ADL5370 provide an easy-to- interface DAC/modulator combination that can be easily characterized on the evaluation board. Solderable jumpers can be configured to evaluate the single-ended or differential outputs of the AD9714/ AD9715/AD9716/AD9717. This is the default configuration from the factory and consists of the following population of the components:

• JP55, JP56, JP76, JP82—unsoldered
• R13, R14, R52, R53—unpopulated
• R50, R57, T1, T2—populated To evaluate the ADL5370 on this board, the population of these same components should be reversed so that they are in the following positions:
• JP55, JP56, JP76, JP82—soldered
• R13, R14, R52, R53—populated
• R50, R57, T1, T2—unpopulated The AUXDAC outputs can be connected to Test Point TP44 and Test Point TP45 if LO feedthrough compensation is necessary.

0.20 REF

0.05 MAX

0.02 NOM

0.80 MAX

0.65 TYP

0.60 MAX

0.25 MIN

Figure 98. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the prop erty of their respective owners.