AD9715

AD9714/AD9715/AD9716/AD9717 (Rev.D)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 54

Technical content

AD9714/AD9715/AD9716/AD9717 Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters Rev. D DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FEATURES

►Power dissipation @ 3.3 V, 2 mA output ►37 mW @ 10 MSPS ►86 mW @ 125 MSPS ►Sleep mode: <3 mW @ 3.3 V ►Supply voltage: 1.8 V to 3.3 V ►SFDR to Nyquist ►84 dBc @ 1 MHz output ►75 dBc @ 10 MHz output ►AD9717 NSD @ 1 MHz output, 125 MSPS, 2 mA: −151 dBc/Hz ►Differential current outputs: 1 mA to 4 mA ►2 on-chip auxiliary DACs ►CMOS inputs with single-port operation ►Output common mode: adjustable 0 V to 1.2 V ►Small footprint 40-lead LFCSP RoHS-compliant package

APPLICATIONS

►Wireless infrastructures ►Picocell, femtocell base stations ►Medical instrumentation ►Ultrasound transducer excitation ►Portable instrumentation ►Signal generators, arbitrary waveform generators GENERAL DESCRIPTION The AD9714/AD9715/AD9716/AD9717 are pin-compatible, dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC® converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and dc performance and support update rates up to 125 MSPS. The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9714/AD9715/AD9716/AD9717 make them well-suited for portable and low power applications. PRODUCT HIGHLIGHTS 1. Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 35 mW at 125 MSPS with a 1.8 V supply. Sleep and power-down modes are provided for low power idle periods. 2. LVCMOS Clock Input. High speed, single-ended LVCMOS clock input supports a 125 MSPS conversion rate. 3. Easy Interfacing to Other Components. Adjustable output com- mon mode from 0 V to 1.2 V allows easy interfacing to other components that accept common-mode levels greater than 0 V.

Data Sheet AD9714/AD9715/AD9716/AD9717 TABLE OF CONTENTS analog.com Rev. D | 2 of 54 Single-Ended Buffered Output Using an Op Differential Buffered Output Using an Op Correcting for Nonideal Performance of Quadrature Modulators on the IF-to-RF

REVISION HISTORY

7/2024—Rev. C to Rev. D 8/2022—Rev. B to Rev. C

Data Sheet AD9714/AD9715/AD9716/AD9717 TABLE OF CONTENTS analog.com Rev. D | 3 of 54

Data Sheet AD9714/AD9715/AD9716/AD9717 FUNCTIONAL BLOCK DIAGRAM analog.com Rev. D | 4 of 54 Figure 1.

Data Sheet AD9714/AD9715/AD9716/AD9717 SPECIFICATIONS analog.com Rev. D | 5 of 54 DC SPECIFICATIONS Table 1. Parameter AD9714 AD9715 AD9716 AD9717 UnitMin Typ Max Min Typ Max Min Typ Max Min Typ Max RESOLUTION 8 10 12 14 Bits ACCURACY, AVDD = DVDDIO = CVDD = 3.3 V Differential Nonlinearity (DNL) Precalibration ±0.02 ±0.08 ±0.4 ±1.7 LSB Postcalibration ±0.003 ±0.01 ±0.2 ±1.0 LSB Integral Nonlinearity (INL) Precalibration ±0.025 ±0.13 ±0.4 ±1.8 LSB Postcalibration ±0.01 ±0.05 ±0.3 ±1.3 LSB ACCURACY, AVDD = DVDDIO = CVDD = 1.8 V Differential Nonlinearity (DNL) Precalibration ±0.02 ±0.08 ±0.4 ±1.2 LSB Postcalibration ±0.005 ±0.01 ±0.2 ±1.0 LSB Integral Nonlinearity (INL) Precalibration ±0.025 ±0.12 ±0.4 ±1.5 LSB Postcalibration ±0.02 ±0.05 ±0.25 ±1.1 LSB MAIN DAC OUTPUTS Offset Error −1 0 +1 −1 0 +1 −1 0 +1 −1 0 +1 mV Gain Error Internal Reference −2 +2 −2 +2 −2 +2 −2 +2 % of FSR Full-Scale Output Current1 AVDD = 3.3 V 1 2 4 1 2 4 1 2 4 1 2 4 mA Output Resistance 200 200 200 200 MΩ Crosstalk, Q DAC to I DAC fOUT = 30 MHz 97 97 97 97 dB fOUT = 60 MHz 78 78 78 78 dB MAIN DAC TEMPERATURE DRIFT Offset 0 0 0 0 ppm/°C Gain ±40 ±40 ±40 ±40 ppm/°C Reference Voltage ±25 ±25 ±25 ±25 ppm/°C AUXDAC OUTPUTS Resolution 10 10 10 10 Bits Full-Scale Output Current (Current Sourcing Mode) 125 125 125 125 µA Voltage Output Mode VSS VDD VSS VDD VSS VDD VSS VDD V Output Compliance Range (Sourcing 1 mA) VSS VDD − 0.25 VSS VDD − 0.25 VSS VDD − 0.25 VSS VDD − 0.25 V

Table 1. (Continued) 1 Based on a 10 kΩ external resistor.

Data Sheet AD9714/AD9715/AD9716/AD9717 SPECIFICATIONS analog.com Rev. D | 7 of 54 DIGITAL SPECIFICATIONS Table 2. Parameter Min Typ Max Unit DAC CLOCK INPUT (CLKIN) VIH 2.1 3 V VIL 0 0.9 V Maximum Clock Rate 125 MSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 25 MHz Minimum Pulse Width High 20 ns Minimum Pulse Width Low 20 ns INPUT DATA

1.8 V Q Channel or DCLKIO Falling Edge

Setup Time, tS 0.25 ns Hold Time, tH 1.2 ns

1.8 V I Channel or DCLKIO Rising Edge

Setup Time, tS 0.13 ns Hold Time, tH 1.1 ns

3.3 V Q Channel or DCLKIO Falling Edge

Setup Time, tS −0.2 ns Hold Time, tH 1.5 ns

3.3 V I Channel or DCLKIO Rising Edge

Setup Time, tS −0.2 ns Hold Time, tH 1.6 ns VIH 2.1 3 V VIL 0 0.9 V AC SPECIFICATIONS Table 3. Parameter AD9714 AD9715 AD9716 AD9717 UnitMin Typ Max Min Typ Max Min Typ Max Min Typ Max SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 125 MSPS, fOUT = 10 MHz 75 82 83 84 dBc fDAC = 125 MSPS, fOUT = 50 MHz 60 61 62 63 dBc TWO TONE INTERMODULATION DISTORTION (IMD) fDAC = 125 MSPS, fOUT = 10 MHz 86 87 88 89 dBc fDAC = 125 MSPS, fOUT = 50 MHz 71 71 71 71 dBc NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING fDAC = 125 MSPS, fOUT = 10 MHz −129 −141 −149 −152 dBc/Hz fDAC = 125 MSPS, fOUT = 50 MHz −123 −135 −137 −141 dBc/Hz

Table 3. (Continued)

Data Sheet AD9714/AD9715/AD9716/AD9717 ABSOLUTE MAXIMUM RATINGS analog.com Rev. D | 9 of 54 Table 5. Parameter Rating AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS−0.3 V to +3.9 V DVDD to DVSS −0.3 V to +2.1 V AVSS to DVSS, CVSS −0.3 V to +0.3 V DVSS to AVSS, CVSS −0.3 V to +0.3 V CVSS to AVSS, DVSS −0.3 V to +0.3 V REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS−0.3 V to AVDD + 0.3 V QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN, RLIP, RLIN to AVSS −1.0 V to AVDD + 0.3 V DBn1 (MSB) to DB0 (LSB), CS, SCLK, SDIO, RESET to DVSS −0.3 V to DVDDIO + 0.3 V CLKIN to CVSS −0.3 V to CVDD + 0.3 V Junction Temperature 125°C Storage Temperature Range −65°C to +150°C 1 n stands for 7 for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13 for the AD9717. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operat- ing conditions for extended periods may affect product reliability. THERMAL RESISTANCE Table 6. Package Type θJA θJB1 θJC1 Unit 40-Lead LFCSP (with No Airflow Movement) 29.8 19.0 3.4 °C/W

1 These calculations are intended to represent the thermal performance of the

indicated packages using a JEDEC multilayer test board. Do not assume the same level of thermal performance in actual applications without a careful inspection of the conditions in the application to determine that they are similar to those assumed in these calculations. ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devi- ces and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Figure 2. AD9714 Pin Configuration Table 7. AD9714 Pin Function Descriptions 1 to 4 DB[5:2] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). capacitor. Do not connect external loads to DVDD. 9 DB0 (LSB) Digital Input (LSB). 10 to 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. recommended value for this external resistor is 0 Ω. 21 RLQN Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RLIP Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. 28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally.

Table 7. AD9714 Pin Function Descriptions (Continued) 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. value for this external resistor is 0 Ω. external resistor is 16 kΩ for a 2 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. resistor is 16 kΩ for a 2 mA output current. Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC output. internal reference mode (a 0.1 μF capacitor to AVSS is required). the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for serial port. binary input data format. A logic high (pull-up to DVDDIO) selects the two complement input data format. powers down the device, except for the SPI port. Power-Down (PWRDN). In pin mode, PWRDN powers down the device except for the SPI port. 39 DB7 (MSB) Digital Input (MSB).

41 Exposed Pad

Figure 3. AD9715 Pin Configuration Table 8. AD9715 Pin Function Descriptions 1 to 4 DB[7:4] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). capacitor. Do not connect external loads to DVDD. 8 to 10 DB[3:1] Digital Inputs. 11 DB0 (LSB) Digital Input (LSB). 12 to 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. recommended value for this external resistor is 0 Ω. 21 RLQN Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RLIP Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. 28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally.

Table 8. AD9715 Pin Function Descriptions (Continued) 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. value for this external resistor is 0 Ω. external resistor is 16 kΩ for a 2 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. resistor is 16 kΩ for a 2 mA output current. Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC output. internal reference mode (a 0.1 μF capacitor to AVSS is required). the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. twos complement input data format. 38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. 39 DB9 (MSB) Digital Input (MSB).

Figure 4. AD9716 Pin Configuration Table 9. AD9716 Pin Function Descriptions 1 to 4 DB[9:6] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). capacitor. Do not connect external loads to DVDD. 8 to 12 DB[5:1] Digital Inputs. 13 DB0 (LSB) Digital Input (LSB). 14, 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. recommended value for this external resistor is 0 Ω. 21 RLQN Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RLIP Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. 28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally.

Table 9. AD9716 Pin Function Descriptions (Continued) 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. value for this external resistor is 0 Ω. external resistor is 16 kΩ for a 2 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. resistor is 16 kΩ for a 2 mA output current. Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC output. internal reference mode (a 0.1 μF capacitor to AVSS is required). the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. 38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. 39 DB11 (MSB) Digital Input (MSB).

Figure 5. AD9717 Pin Configuration Table 10. AD9717 Pin Function Descriptions 1 to 4 DB[11:8] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal). capacitor. Do not connect external loads to DVDD. 8 to 14 DB[7:1] Digital Inputs. 15 DB0 (LSB) Digital Input (LSB). 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. recommended value for this external resistor is 0 Ω. 21 RLQN Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 RLQP Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally. 26 AVDD Analog Supply Voltage (1.8 V to 3.3 V). 27 RLIP Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally. 28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally.

Table 10. AD9717 Pin Function Descriptions (Continued) 31 CMLI I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. value for this external resistor is 0 Ω. external resistor is 16 kΩ for a 2 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. resistor is 16 kΩ for a 2 mA output current. Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC output. internal reference mode (a 0.1 μF capacitor to AVSS is required). the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the Retimer section). 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. 38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. 39 DB13 (MSB) Digital Input (MSB).

Data Sheet AD9714/AD9715/AD9716/AD9717 TERMINOLOGY analog.com Rev. D | 31 of 54 Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of zero. For IOUTP, 0 mA output is expected when the inputs are all 0. For IOUTN, 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and the ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range Output compliance range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or break- down, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient value (25°C) to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range per degree Celsius (ppm FSR/°C). For reference drift, the drift is reported in parts per million per degree Celsius (ppm/°C). Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the peak ampli- tude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels (dB). Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent chan- nel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

Data Sheet AD9714/AD9715/AD9716/AD9717 THEORY OF OPERATION analog.com Rev. D | 33 of 54 Optional on-chip xRSET resistors are provided that can be program- med between a nominal value of 8 kΩ to 32 kΩ (4 mA to 1 mA IxOUTFS, respectively). The AD9714/AD9715/AD9716/AD9717 provide the option of setting the output common mode to a value other than AVSS via the output common-mode pins (CMLI and CMLQ). This facilitates directly interfacing the output of the AD9714/AD9715/AD9716/AD9717 to components that require common-mode levels greater than 0 V.

AD9716/AD9717 is configured as a single I/O pin on the SDIO pin. the present data is written. The instruction byte contains the information shown in Table 11. 1 indicates a read operation. Logic 0 indicates a write operation. number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 12. Table 12. Byte Transfer Count with the beginning of the data in the data transfer cycle. entire communications cycle. bit (Register 0x00, Bit 6). The default is MSB first (LSBFIRST = 0).

Data Sheet AD9714/AD9715/AD9716/AD9717 SPI REGISTER MAP analog.com Rev. D | 36 of 54 Table 13. Name Addr Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Control 0x00 0x00 Reserved LSBFIRST Reset LNGINS Reserved Power-Down 0x01 0x40 LDOOFF LDOSTAT PWRDN Q DACOFFI DACOFF QCLKOFF ICLKOFF EXTREF Data Control 0x02 0x34 TWOS Reserved IFIRST IRISING SIMULBIT DCI_EN DCOSGL DCODBL I DAC Gain 0x03 0x00 Reserved I DACGAIN[5:0] IRSET 0x04 0x00 IRSETEN Reserved IRSET[5:0] IRCML 0x05 0x00 IRCMLEN Reserved IRCML[5:0] Q DAC Gain 0x06 0x00 Reserved Q DACGAIN[5:0] QRSET 0x07 0x00 QRSETEN Reserved QRSET[5:0] QRCML 0x08 0x00 QRCMLEN Reserved QRCML[5:0] AUXDAC I 0x09 0x00 IAUXDAC[7:0] AUX CTL I 0x0A 0x00 IAUXEN IAUXRNG[1:0] IAUXOFS[2:0] IAUXDAC[9:8] AUXDAC Q 0x0B 0x00 QAUXDAC[7:0] AUX CTL Q 0x0C 0x00 QAUXEN QAUXRNG[1:0] QAUXOFS[2:0] QAUXDAC[9:8] Reference Resistor 0x0D 0x00 Reserved RREF[5:0] Cal Control 0x0E 0x00 PRELDQ PRELDI CALSELQ CALSELI CALCLK DIVSEL[2:0] Cal Memory 0x0F 0x00 CALSTATQ CALSTATI Reserved CALMEMQ[1:0] CALMEMI[1:0] Memory Address 0x10 0x00 Reserved MEMADDR[5:0] Memory Data 0x11 0x3F Reserved MEMDATA[5:0] Memory R/W 0x12 0x00 CALRSTQ CALRSTI CALEN SMEMWR SMEMRD UNCALQ UNCALI CLKMODE 0x14 0x00 CLKMODEQ[1:0] Searching Reacquire CLKMODEN CLKMODEI[1:0] Version 0x1F 0x03 Version[7:0]

Data Sheet AD9714/AD9715/AD9716/AD9717 SPI REGISTER DESCRIPTIONS analog.com Rev. D | 37 of 54 Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 14. Register Address Bit Name Description SPI Control 0x00 6 LSBFIRST 0 (default): MSB first, per SPI standard. 1: LSB first, per SPI standard. Note that the user must always change the LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit order errors. 5 Reset Execute software reset of SPI and controllers, reload default register values except Register 0x00. 1: sets software reset; write 0 on the next (or any following) cycle to release reset. 4 LNGINS 0 (default): the SPI instruction word uses a 5-bit address. 1: the SPI instruction word uses a 13-bit address. Power-Down 0x01 7 LDOOFF 0 (default): LDO voltage regulator on. 1: turns core LDO voltage regulator off. 6 LDOSTAT 0: indicates that the core LDO voltage regulator is off. 1 (default): indicates that the core LDO voltage regulator is on. 5 PWRDN 0 (default): all analog and digital circuitry and SPI logic are powered on. 1: powers down all analog and digital circuitry except for SPI logic. 4 Q DACOFF 0 (default): turns on Q DAC output current. 1: turns off Q DAC output current. 3 I DACOFF 0 (default): turns on I DAC output current. 1: turns off I DAC output current. 2 QCLKOFF 0 (default): turns on Q DAC clock. 1: turns off Q DAC clock. 1 ICLKOFF 0 (default): turns on I DAC clock. 1: turns off I DAC clock. 0 EXTREF 0 (default): turns on internal voltage reference. 1: powers down internal voltage reference (external reference required). Data Control 0x02 7 TWOS 0 (default): unsigned binary input data format. 1: twos complement input data format. 5 IFIRST 0: pairing of data—Q first of pair on data input pads. 1 (default): pairing of data—I first of pair on data input pads. 4 IRISING 0: Q data latched on DCLKIO rising edge. 1 (default): I data latched on DCLKIO rising edge. 3 SIMULBIT 0 (default): allows simultaneous input and output enable on DCLKIO. 1: disallows simultaneous input and output enable on DCLKIO. 2 DCI_EN Controls the use of the DCLKIO pad for data clock input. 0: data clock input disabled. 1 (default): data clock input enabled. 1 DCOSGL Controls the use of the DCLKIO pad for data clock output. 0 (default): data clock output disabled. 1: data clock output enabled; regular strength driver. 0 DCODBL Controls the use of the DCLKIO pad for data clock output. 0 (default): DCODBL data clock output disabled. 1: DCODBL data clock output enabled; paralleled with DCOSGL for 2× drive current. I DAC Gain 0x03 5:0 I DACGAIN[5:0] DAC I fine gain adjustment; alters the full-scale current as shown in Figure 101. Default IDACGAIN = 0x00.

Table 14. (Continued) to the FADJI/AUXI pin. Nominal value for this external resistor is 16 kΩ. 1: enables the on-chip IRSET and allows value to be changed for I channel. DAC in ~0.25 dB steps twos complement (nonlinear); see Figure 100. connected to the CMLI pin. Recommended value for this external resistor is 0 Ω. 1: enables on-chip IRCML and allows adjustment for I channel. connected to the FADJQ/AUXQ pin. Recommended value for this external resistor is 16 kΩ. 1: enables on-chip QRSET and allows adjustment for Q channel. DAC in ~0.25 dB steps twos complement (nonlinear); see Figure 100. resistor connected to CMLQ pin. Recommended value for this external resistor is 0 Ω. 1: enables on-chip QRCML adjustment for Q channel. AUXDAC I 0x09 7:0 IAUXDAC[7:0] 8 LSBs for 10-bit AUXDAC I output voltage adjustment word. Set MSBs in Register 0x0A. 0x3FF: sets AUXDAC I output to full scale. 0x200: sets AUXDAC I output to midscale. 0x000 (default): sets AUXDAC I output to bottom of scale. AUX CTL I 0x0A 7 IAUXEN 0 (default): AUXDAC I output disabled. 6:5 IAUXRNG[1:0] 00 (default): sets AUXDAC I output voltage range to 2 V. 01: sets AUXDAC I output voltage range to 1.5 V. 10: sets AUXDAC I output voltage range to 1.0 V.

11: sets AUXDAC I output voltage range to 0.5 V. 4:2 IAUXOFS[2:0] 000 (default): sets AUXDAC I top of range to 1.0 V. 001: sets AUXDAC I top of range to 1.5 V. 010: sets AUXDAC I top of range to 2.0 V. 011: sets AUXDAC I top of range to 2.5 V. 100: sets AUXDAC I top of range to 2.9 V. AUXDAC Q 0x0B 7:0 QAUXDAC[7:0] 8 LSBs for 10-bit AUXDAC Q output voltage adjustment word. Set MSBs in Register 0x0C. 0x3FF: sets AUXDAC Q output to full scale. 0x200: sets AUXDAC Q output to midscale. 0x000 (default): sets AUXDAC Q output to bottom of scale. AUX CTL Q 0x0C 7 QAUXEN 0 (default): AUXDAC Q output disabled. 6:5 QAUXRNG[1:0] 00 (default): sets AUXDAC Q output voltage range to 2 V. 01: sets AUXDAC Q output voltage range to 1.5 V. 10: sets AUXDAC Q output voltage range to 1.0 V. 11: sets AUXDAC Q output voltage range to 0.5 V. 4:2 QAUXOFS[2:0] 000 (default): sets AUXDAC Q top of range to 1.0 V. 001: sets AUXDAC Q top of range to 1.5 V. 010: sets AUXDAC Q top of range to 2.0 V. 011: sets AUXDAC Q top of range to 2.5 V. 100: sets AUXDAC Q top of range to 2.9 V. 000000 (default): sets the value of RREF to 10 kΩ, VREF = 1.0 V. 011111: sets the value of RREF to 12 kΩ, VREF = 1.2 V. 100000: sets the value of RREF to 8 kΩ, VREF = 0.8 V. 111111: sets the value of RREF to 10 kΩ, VREF = 1.0 V. Cal Control 0x0E 7 PRELDQ 0 (default): preload Q DAC calibration reference set to 32. 1: preload Q DAC calibration reference set by user (Cal Address 1). 6 PRELDI 0 (default): preload I DAC calibration reference set to 32. 1: preload I DAC calibration reference set by user (Cal Address 1). 5 CALSELQ 0 (default): Q DAC self-calibration done. 1: select Q DAC self-calibration. 4 CALSELI 0 (default): I DAC self-calibration done. 1: select I DAC self-calibration. 3 CALCLK 0 (default): calibration clock disabled. 1: calibration clock enabled. 2:0 DIVSEL[2:0] Calibration clock divide ratio from DAC clock rate. 000 (default): divide by 256.

Cal Memory 0x0F 7 CALSTATQ 0 (default): Q DAC calibration in progress. 1: calibration of Q DAC complete. 6 CALSTATI 0 (default): I DAC calibration in progress. 1: calibration of I DAC complete. 3:2 CALMEMQ[1:0] Status of Q DAC calibration memory. 1:0 CALMEMI[1:0] Status of I DAC calibration memory. Memory Address 0x10 5:0 MEMADDR[5:0] Address of static memory to be accessed. Memory Data 0x11 5:0 MEMDATA[5:0] Data for static memory access. Memory R/W 0x12 7 CALRSTQ 0 (default): no action. 6 CALRSTI 0 (default): no action. 4 CALEN 0 (default): no action. 1: initiate device self-calibration. 3 SMEMWR 0 (default): no action. 1: write to static memory (calibration coefficients). 2 SMEMRD 0 (default): no action. 1: read from static memory (calibration coefficients). 1 UNCALQ 0 (default): no action. 1: reset Q DAC calibration coefficients to default (uncalibrated). 0 UNCALI 0 (default): no action. 1: reset I DAC calibration coefficients to default (uncalibrated). DCLKIO and CLKIN, as described in Table 16. If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer. synchronize the DACs (see the Retimer section). 4 Searching Data path retimer status bit. 0 (default): clock relationship established. usable while this bit is high). 3 Reacquire Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship.

2 CLKMODEN 0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and read back in CLKMO-

1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers. and CLKIN as described in Table 16.

If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer. synchronize the DACs (see the Retimer section). Version 0x1F 7:0 Version[7:0] Hardware version of the device. This register is set to 0x03 for the latest version of the device.

Table 15. Timer Register List CLKMODEQ[1:0] Q data path retimer clock selected output. Valid after the searching bit goes low. Searching High indicates that the internal data path retimer is searching for the clock relationship (DAC is not usable until it is low again). Reacquire Changing this bit from 0 to 1 causes the data path retimer circuit to reacquire the clock relationship. CLKMODEN 0: uses CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking. 1: uses the CLKMODE value set in CLKMODEI[1:0] to override the bits for both I and Q retimers (that is, force the retimer). CLKMODEI[1:0] I data path retimer clock selected output. Valid after searching goes low. If CLKMODEN = 1, a value written to this register overrides both the I and Q automatic retimer values. Table 16. CLKMODEI/CLKMODEQ Details

to reinitiate phase detection in the I and Q retimers at any time. for synchronizing multiple devices. but CLKIN and DCLKIO are not tied together (that is, not in phase). SCLK pin can be taken low and then high again. be allowed to automatically select a phase each time. phase that is automatically selected or manually forced. reference is shown in Figure 96. Figure 96. Internal Reference Configuration summarizes the reference operation. Table 17. Reference Operation gain control of the DAC output.

Data Sheet AD9714/AD9715/AD9716/AD9717 DIGITAL INTERFACE OPERATION analog.com Rev. D | 47 of 54 A differential pair (IOUTP/IOUTN or QOUTP/QOUTN) typically drives a resistive load directly or via a transformer. If dc coupling is required, the differential pair (IOUTP/IOUTN or QOUTP/QOUTN) must be connected to matching resistive loads, xRLOAD, that are tied to analog common, AVSS. The single-ended voltage output appearing at the positive and negative nodes is VIOUTP = IOUTP × IRLOAD (6) VQOUTP = QOUTP × QRLOAD VIOUTN = IOUTN × IRLOAD (7) VQOUTN = QOUTN × QRLOAD To achieve 1 V p-p at the nominal 4 mA output current, IRLOAD = QRLOAD must be set to 250 Ω. Substituting the values of IOUTP, IOUTN, and IxREF, VIDIFF can be expressed as VIDIFF = {(2 × IDAC CODE – (2N − 1))/2N} × (32 × VREFIO/ IRSET) × IRLOAD (8) Equation 8 highlights some of the advantages of operating the AD9714/AD9715/AD9716/AD9717 differentially. First, the differen- tial operation helps cancel common-mode error sources associated with IOUTP and IOUTN, such as noise, distortion, and dc offsets. Second, the differential code-dependent current and subsequent voltage, VIDIFF, is twice the value of the single-ended voltage output (that is, VIOUTP or VIOUTN), thus providing twice the signal power to the load. Note that the gain drift temperature performance for a single-ended output (VIOUTP and VIOUTN) or differential output (VIDIFF) of the AD9714/AD9715/AD9716/AD9717 can be enhanced by selecting temperature-tracking resistors for xRLOAD and xRSET because of their ratiometric relationship, as shown in Equation 8. ANALOG OUTPUT The complementary current outputs in each DAC, IOUTP/ IOUTN and QOUTP/QOUTN, can be configured for single-ended or dif- ferential operation. IOUTP/IOUTN and QOUTP/ QOUTN can be converted into complementary single-ended voltage outputs, VIOUTP and VIOUTN, as well as VQOUTP and VQOUTN via a load resistor, xRLOAD, as described in the DAC Transfer Function section by Equation 6 through Equation 8. The differential voltages, VIDIFF and VQDIFF, existing between VIOUTP and VIOUTN, and VQOUTP and VQOUTN, can also be converted to a single-ended voltage via a transformer or a differential amplifier configuration. The ac perform- ance of the AD9714/AD9715/AD9716/AD9717 is optimum and is specified using a differential transformer-coupled output in which the voltage swing at IOUTP and IOUTN is limited to ±0.5 V. The distortion and noise performance of the AD9714/AD9715/AD9716/ AD9717 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTP/IOUTN and QOUTP/QOUTN can be significantly reduced by the common- mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also pro- vides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Because the output cur- rents of IOUTP/IOUTN and QOUTP/QOUTN are complementary, they become additive when processed differentially. SELF-CALIBRATION The AD9714/AD9715/AD9716/AD9717 have a self-calibration fea- ture that improves the DNL of the device. Performing a self-calibra- tion on the device improves device performance in low frequency applications. The device performance in applications where the an- alog output frequencies are above 5 MHz are generally influenced more by dynamic device behavior than by DNL and, in these cases, self-calibration is unlikely to provide much benefit. The calibration clock frequency is equal to the DAC clock divided by the division factor chosen by the DIVSEL value. Each calibration clock cycle is between 32 and 2048 DAC input clock cycles, depending on the value of DIVSEL[2:0] (Register 0x0E, Bits[2:0]). The frequency of the calibration clock should be between 0.5 MHz and 4 MHz for reli- able calibrations. Best results are obtained by setting DIVSEL[2:0] (Register 0x0E, Bits[2:0]) to produce a calibration clock frequency between these values. Separate self-calibration hardware is includ- ed for each DAC. The DACs can be self-calibrated individually or simultaneously. To perform a device self-calibration, the following procedure can be used: 1. Write 0x00 to Register 0x12. This ensures that the UNCALI and UNCALQ bits are reset. 2. Set up a calibration clock between 0.5 MHz and 4 MHz using DIVSEL[2:0], and then enable the calibration clock by setting the CALCLK bit (Register 0x0E, Bit 3). 3. Select the DAC(s) to self-calibrate by setting either Bit 4 (CAL- SELI) for the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Note that each DAC contains independent cali- bration hardware so that they can be calibrated simultaneously. 4. Start self-calibration by setting the CALEN bit (Register 0x12, Bit 4). Wait approximately 300 calibration clock cycles. 5. Check if the self-calibration has completed by reading the CALSTATI bit (Bit 6) and CALSTATQ bit (Bit 7) in Register 0x0F. Logic 1 indicates that the calibration has completed. 6. When the self-calibration has completed, write 0x00 to Register 0x12. 7. Disable the calibration clock by clearing the CALCLK bit (Regis- ter 0x0E, Bit 3). The AD9714/AD9715/AD9716/AD9717 allow reading and writing of the calibration coefficients. There are 32 coefficients in total. The read/write feature of the coefficients can be useful for improving the results of the self-calibration routine by averaging the results

Data Sheet AD9714/AD9715/AD9716/AD9717 OUTLINE DIMENSIONS ©2008-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. D | 54 of 54 Package Drawing (Option) Package Type Package Description CP-40-1 LFCSP 40-Lead Lead Frame Chip Scale Package For the latest package outline information and land patterns (footprints), go to Package Index. Updated: August 05, 2022 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity Package Option AD9714BCPZ -40°C to +85°C 40-Lead LFCSP (6mm x 6mm w/ EP) CP-40-1 AD9714BCPZRL7 -40°C to +85°C 40-Lead LFCSP (6mm x 6mm w/ EP) Reel, 750 CP-40-1 AD9715BCPZ -40°C to +85°C 40-Lead LFCSP (6mm x 6mm w/ EP) CP-40-1 AD9715BCPZRL7 -40°C to +85°C 40-Lead LFCSP (6mm x 6mm w/ EP) Reel, 750 CP-40-1 AD9716BCPZ -40°C to +85°C 40-Lead LFCSP (6mm x 6mm w/ EP) CP-40-1 AD9716BCPZRL7 -40°C to +85°C 40-Lead LFCSP (6mm x 6mm w/ EP) Reel, 750 CP-40-1 AD9717BCPZ -40°C to +85°C 40-Lead LFCSP (6mm x 6mm w/ EP) CP-40-1 AD9717BCPZRL7 -40°C to +85°C 40-Lead LFCSP (6mm x 6mm w/ EP) Reel, 750 CP-40-1 1 Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Description AD9714-DPG2-EBZ Evaluation Board AD9715-DPG2-EBZ Evaluation Board AD9716-DPG2-EBZ Evaluation Board AD9717-DPG2-EBZ Evaluation Board 1 Z = RoHS Compliant Part.