AD9713BAP

AD9712B AD | Alldatasheet

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(MSB) (LSB) DIGITAL INPUTS D 1 THRU D12 IOUT CONTROL AMP INTERNAL VOLTAGE REFERENCE REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 12-Bit, 100 MSPS D/A Converters AD9712B/AD9713B Tel: 617/329-4700 Fax: 617/326-8703

FEATURES

100 MSPS Update Rate

SFDR @ 1 MHz: 70 dBc Low Glitch Impulse: 28 pV-s Fast Settling: 27 ns Low Power: 725 mW 1/2 LSB DNL (B Grade)

40 MHz Multiplying Bandwidth

APPLICATIONS

Arbitrary Waveform Generators Digital Synthesizers Signal Generators GENERAL DESCRIPTION The AD9712B and AD9713B D/A converters are replacements for the AD9712 and AD9713 units which offer improved ac and dc performance. Like their predecessors, they are 12-bit, high speed digital-to-analog converters fabricated in an advanced oxide isolated bipolar process. The AD9712B is an ECL- compatible device featuring update rates of 100 MSPS mini- mum; the TTL-compatible AD9713B will update at 80 MSPS minimum. Designed for direct digital synthesis, waveform reconstruction, and high resolution imaging applications, both devices feature low glitch impulse of 28 pV-s and fast settling times of 27 ns. Both units are characterized for dynamic performance and have excellent harmonic suppression. The AD9712B and AD9713B are available in 28-pin plastic DIPs and PLCCs, with an operating temperature range of –25°C to +85°C. Both are also available for extended tempera- ture ranges of –55°C to +125°C in cerdips and 28-pin LCC packages.

AD9712B/AD9713B–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

AD9712B/AD9713B AD9712B/AD9713B AD9712B/AD9713B AD9712B/AD9713B Test AN/AP BN/BP SE/SQ TE/TQ Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 12 12 12 12 Bits DC ACCURACY AD9712B AD9713B Test All Grades All Grades Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Units INITIAL OFFSET ERROR Zero-Scale Offset Error +25 °C I 0.5 2.5 0.5 2.5 µA Full VI 5.0 5.0 µA Full-Scale Gain Error 1 +25°C I 1.0 5 1.0 5 % Full VI 8 8 % Offset Drift Coefficient +25 °C V 0.01 0.01 µA/°C REFERENCE/CONTROL AMP Full VI –1.12 –1.24 –1.12 –1.24 V Internal Reference Voltage Drift Full V 50 50 ppm/ °C Internal Reference Output Current Full IV –50 +500 –50 +500 µA Amplifier Input Impedance +25 °C V 50 50 k Ω Amplifier Bandwidth +25 °C V 300 300 kHz REFERENCE INPUT 2 Reference Input Impedance +25 °CV 3 3 k Ω Reference Multiplying Bandwidth 3 +25°C V 40 40 MHz DYNAMIC PERFORMANCE Full-Scale Output Current 4 +25°C V 20.48 20.48 mA Output Compliance Range +25 °C IV –1.2 +2 –1.2 +2 V Output Capacitance +25 °C V 15 15 pF Output Update Rate 5 +25°C IV 100 110 80 100 MSPS Output Settling Time (t ST)6 +25°C V 27 27 ns Output Propagation Delay (t PD)7 +25°CV 6 7 n s Glitch Impulse 8 +25°C V 28 28 pV-s Output Rise Time 9 +25°CV 2 2 n s Output Fall Time 9 +25°CV 2 2 n s DIGITAL INPUTS Logic “1” Voltage Full VI –1.0 –0.8 2.0 V Logic “0” Voltage Full VI –1.7 –1.5 0.8 V Logic “1” Current Full VI 20 20 µA Logic “0” Current Full VI 10 600 µA Input Capacitance +25 °CV 3 3 p F Input Setup Time (t Full IV 0.8 0.8 ns Input Hold Time (t H)11 +25°C IV 1.8 1.2 1.8 1.2 ns Full IV 2.0 2.0 ns Latch Pulse Width (t LPW) (LOW) +25 °C IV 2.5 1.7 2.5 1.7 ns (Transparent) Full 2.8 2.8 ns AC LINEARITY12 Spurious-Free Dynamic Range (SFDR)

1.23 MHz; 10 MSPS; 2 MHz Span +25 °C V 70 70 dB

5.055 MHz; 20 MSPS; 2 MHz Span +25 °C V 72 72 dB

10.1 MHz; 50 MSPS; 2 MHz Span +25 °C V 68 68 dB

16 MHz; 40 MSPS; 10 MHz Span +25 °C V 68 68 dB

REV. B–2– [–VS = –5.2 V; +V S = +5 V (AD9713B only); Reference Voltage = –1.2 V; RSET = 7.5 kV; VOUT = 0 V (virtual ground); unless otherwise noted]

Test All Grades All Grades Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Units POWER SUPPLY 13 Positive Supply Current (+5.0 V) +25 °CI 6 1 2 m A Full VI 14 mA Negative Supply Current (–5.2 V) 14 +25°C I 140 178 145 184 mA Full VI 183 188 mA Nominal Power Dissipation +25 °C V 728 784 mW Power Supply Rejection Radio (PSRR) 15 +25°C I 30 100 30 100 µA/V NOTES 1Measured as error in ratio of full-scale current to current through R SET (160 µA nominal); ratio is nominally 128. 2Full-scale variations among devices are higher when driving REFERENCE INPUT directly. 3Frequency at which the gain is flat ± 0.5 dB; R L = 50 Ω ; 50% modulation at midscale. 4Based on I FS = 128 (VREF/RSET) when using internal amplifier. 5Data registered into DAC accurately at this rate; does not imply settling to 12-bit accuracy. 6Measured as voltage settling at midscale transition to ± 0.024%, RL = 50 Ω . 7Measured as the time between the 50% point of the falling edge of LATCH ENABLE and the point where the output signal has left a 1 LSB error band around its previous value. 8Peak glitch impulse is measured as the largest area under a single positive or negative transient. 9Measured with R L = 50 Ω and DAC operating in latched mode. 10Data must remain stable for specified time prior to falling edge of LATCH ENABLE signal. 11Data must remain stable for specified time after rising edge of LATCH ENABLE signal. 12SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is centered at the fundamental frequency and covers the indicated span. 13Supply voltages should remain stable within ± 5% for normal operation. 14108 mA typ on Digital –V S, 37 mA typ on Analog –V S. 15Measured at ± 5% of +VS (AD9713B only) and –V S (AD9712B or AD9713B) using external reference. Specifications subject to change without notice. ORDERING GUIDE Temperature Package Package Model Range Description Option AD9712BAN –25 °C to +85°C 28-Pin PDIP N-28 AD9712BBN –25 °C to +85°C 28-Pin PDIP N-28 AD9712BAP –25 °C to +85°C 28-Pin PLCC P-28A AD9712BBP –25 °C to +85°C 28-Pin PLCC P-28A AD9712BSQ/883B –55 °C to +125°C 28-Pin Cerdip Q-28 AD9712BSE/883B –55 °C to +125°C 28-Pin LCC E-28A AD9712BTQ/883B –55 °C to +125°C 28-Pin Cerdip Q-28 AD9712BTE/883B –55 °C to +125°C 28-Pin LCC E-28A AD9713BAN –25 °C to +85°C 28-Pin PDIP N-28 AD9713BBN –25 °C to +85°C 28-Pin PDIP N-28 AD9713BAP –25 °C to +85°C 28-Pin PLCC P-28A AD9713BBP –25 °C to +85°C 28-Pin PLCC P-28A AD9713BSQ/883B –55 °C to +125°C 28-Pin Cerdip Q-28 AD9713BSE/883B –55 °C to +125°C 28-Pin LCC E-28A AD9713BTQ/883B –55 °C to +125°C 28-Pin Cerdip Q-28 AD9713BTE/883B –55 °C to +125°C 28-Pin LCC E-28A EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. II – 100% production tested at +25 °C, and sample tested at specified temperatures. III – Sample tested only. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% tested at +25 °C. 100% production tested at temperature extremes for extended tempera- ture devices; sample tested at temperature extremes for commercial/industrial devices. ABSOLUTE MAXIMUM RATINGS 1 Digital Input Voltages (D 1–D12, LATCH ENABLE) Operating Temperature Range Maximum Junction Temperature 2 NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Typical thermal impedances with parts soldered in place: 28-pin plastic DIP: θJA = 37 °C/W, θJC = 10 °C/W; 28-pin PLCC: θJA = 44 °C/W, θJC = 14 °C/W; Cerdip: θJA = 32°C/W, θJC = 10°C/W; LCC: θJA = 41°C/W, θJC = 13°C/W. No air flow. AD9712B/AD9713B REV. B –3–

REV. B–4– PIN DESCRIPTIONS Pin # Name Function 1–10 D 2–D11 Ten bits of twelve-bit digital input word. 11 D 12 (LSB) Least Significant Bit (LSB) of digital input word. Input Coding vs. Current Output Input Code D1–D12 IOUT (mA) I OUT (mA) 1111111111 –20.475 0 0000000000 0 –20.475 12 DIGITAL –V S One of two negative digital supply pins; nominally –5.2 V. 13 ANALOG RETURN Analog ground return. This point and the reference side of the DAC load resistors should be connected to the same potential (nominally ground). 14 I OUT Analog current output; full-scale output occurs with digital inputs at all “1.” 15 ANALOG –V S One of two negative analog supply pins; nominally –5.2 V. 16 I OUT Complementary analog current output; zero scale output occurs with digital inputs at all “1.” 17 REFERENCE IN Normally connected to CONTROL AMP OUT (Pin 18). Direct line to DAC current source network. Voltage changes at this point have a direct effect on the full-scale output value of unit. Full-scale current output = 128 (Reference voltage/R SET) when using internal amplifier. 18 CONTROL AMP OUT Normally connected to REFERENCE INPUT (Pin 17). Output of internal control amplifier, which provides a temperature-compensated drive level to the current switch network. 19 CONTROL AMP IN Normally connected to REFERENCE OUT (Pin 20) if not connected to external reference. 20 REFERENCE OUT Normally connected to CONTROL AMP IN (Pin 19). Internal voltage reference, nominally –1.18 V.

21 DIGITAL –V

S One of two negative digital supply pins; nominally –5.2 V. 22 REFERENCE GROUND Ground return for the internal voltage reference and amplifier. 23 DIGITAL +V S Positive digital supply pin, used only on the AD9713B; nominally +5 V. No connection to this pin on AD9712B. 24 R SET Connection for external resistance reference. Full-scale current out = 128 (Reference voltage/ RSET) when using internal amplifier. Nominally 7.5 k Ω . 25 ANALOG –V S One of two negative analog supply pins; nominally –5.2 V. 26 LATCH ENABLE Transparent latch control line. Register is transparent when LATCH ENABLE is LOW. 27 DIGITAL GROUND Digital ground return. 28 D 1 (MSB) Most Significant Bit (MSB) of digital input word. PIN CONFIGURATIONS PLCC/LCC ANALOG –V S R SET DIGITAL +VS REFERENCE GROUND DIGITAL –VS REFERENCE OUT CONTROL AMP IN D (MSB)1 DIGITAL GROUND D 6 D 9 D 8 D 7 D 11 D 10 ANALOG RETURN DIGITAL –V S ANALOG –V S IOUT REFERENCE IN CONTROL AMP OUT AD9712B AD9713B D 5 D D 2 LATCH ENABLE (Not to Scale) TOP VIEW 28 27 261234 12 13 14 15 16 17 18 D (LSB)12 D 4 IOUT DIP D 6 D 8 D 7 D11 D 10 D 12 (LSB) D 5 D 3 D 2 ANALOG RETURN IOUT DIGITAL –VS D 1 (MSB0) DIGITAL GROUND LATCH ENABLE R SET REFERENCE GROUND REFERENCE OUT CONTROL AMP IN IOUT REFERENCE IN CONTROL AMP OUT ANALOG –V S DIGITAL +VS DIGITAL –VS ANALOG –V S 6 23 TOP VIEW (Not to Scale) AD9712B AD9713B

REV. B –5– DIE LAYOUT AND METALIZATION INFORMATION S THEORY AND APPLICATIONS The AD9712B and AD9713B high speed digital-to-analog converters utilize Most Significant Bit (MSB) decoding and segmentation techniques to reduce glitch impulse and main- tain 12 -bit linearity without trimming. As shown in the functional block diagram, the design is based on four main subsections: the Decoder/Driver circuits, the Transparent Latches, the Switch Network, and the Control Am- plifier. An internal bandgap reference is also included to allow operation with a minimum of external components. Digital Inputs/Timing The AD9712B employs single-ended ECL-compatible inputs for data inputs D1–D12 and LATCH ENABLE. The internal ECL midpoint reference is designed to match 10K ECL device thresholds. On the AD9713B, a TTL translator is added at each input; with this exception, the AD9712B and AD9713B are identical. In the Decoder/Driver section, the four MSBs (D 1–D4) are decoded to 15 “thermometer code” lines. An equalizing delay is included for the eight Least Significant Bits (LSBs) and LATCH ENABLE. This delay minimizes data skew, and data setup and hold times at the latch inputs; this is important when operating the latches in the transparent mode. Without the delay, skew caused by the decoding circuits would degrade glitch impulse. The latches operate in their transparent mode when LATCH ENABLE (Pin 26) is at logic level “0.” The latches should be used to synchronize data to the current switches by applying a narrow LATCH ENABLE pulse with proper data setup and hold times as shown in the Timing Diagram. An external latch at each data input, clocked out of phase with the Latch Enable, operates the AD9712B/AD9713B in a master slave (edge- triggered) mode. This is the optimum way to operate the DAC because data is always stable at the DAC input. An external latch eases timing constraints when using the converter. Although the AD9712B/AD9713B chip is designed to provide isolation from digital inputs to the outputs, some coupling of digital transitions is inevitable, especially with TTL or CMOS inputs applied to the AD9713B. Digital feedthrough can be re- duced by forming a low-pass filter using a (200 Ω ) series resistor in series with the capacitance of each digital input; this rolls off the slew rate of the digital inputs. References As shown in the functional block diagram, the internal bandgap reference, control amplifier, and reference input are pinned out for maximum user flexibility when setting the reference. When using the internal reference, REFERENCE OUT (Pin 20) should be connected to CONTROL AMP IN (Pin 19). CON- TROL AMP OUT (Pin 18) should be connected to REFER- ENCE IN (Pin 17) through a 20 Ω resistor. A 0.1 µF ceramic capacitor from Pin 17 to –V S (Pin 15) improves settling by decoupling switching noise from the current sink base line. A reference current cell provides feedback to the control amp by sinking current through R SET (Pin 24). tS – INPUT SETUP TIME tLPW – LATCH PULSE WIDTH – OUTPUT PROPAGATION DELAYtPD tH – INPUT HOLD TIME tST – OUTPUT SETTLING TIME OUTPUT ERROR ERROR BAND tPD LATCH ENABLE tST tLPW tS tH VALID DATA tPD DATA INPUTS OUTPUT LATCH ENABLE Timing Diagram

1432 OUTPUT

Figure 6. Direct Digital Synthesizer Block Diagram Figure 7. AD9712B/AD9713B Glitch Impulse Figure 8. Rise and Fall Characteristics waveform, slew rate limitations trans late directly into harmonics.

138 CURRENT SOURCES

16 IOUT

Figure 11. Equivalent Circuits

REV. B–12– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C1635–24–3/92PRINTED IN U.S.A. 28-Pin Plastic DIP (Suffix N) 0.140 (3.56) MIN 0.100 (2.54) BSC 0.550 (13.97) 0.530 (13.46) 1.565 (39.70) 1.380 (35.10) 0.250 (6.35) MAX 0.022 (0.558) 0.014 (0.356) 0.70 (1.77) MAX 0.625 (15.8) 0.600 (15.24) 0.015 (0.381) 0.008 (0.204) 0.060 (1.52) 0.015 (0.38) 28-Pin Cerdip (Suffix Q) 0.590 (14.93) 1.490 (37.84) MAX 0.026 (0.660) 0.014 (0.356) 0.07 (1.78) 0.03 (0.76) 0.610 (15.49) 0.500 (12.70) 0.620 (15.74) 0.018 (0.45) 0.008 (0.20) GLASS SEALANT 0.098 (2.45) 0.110 (2.79) 0.22 (5.59) MAX 0.125 (3.175) MIN 28-Pin Plastic Leaded Chip Carrier (Suffix P) PIN 1 IDENTIFIER 4 26 12 18 0.430 (10.92) 0.390 (9.91) 0.050 (1.27) BSC 0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 0.456 (11.58) 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) 0.180 (4.57) 0.165 (4.19)28-Pin LCC Package (Suffix E) 0.458 (11.63) 0.442 (11.23) 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) 0.055 (1.40) 0.045 (1.14) 0.100 (2.54) 0.064 (1.63) 0.075 (1.91) REF BOTTOM VIEW 1218 123 1314151617 26 27 28