AD9709_09 AD | Alldatasheet
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8-Bit, 125 MSPS, Dual TxDAC+ Digital-to-Analog Converter AD9709 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved.
FEATURES
8-bit dual transmit digital-to-analog converter (DAC)
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc Excellent gain and offset matching: 0.1% Fully independent or single-resistor gain control Dual port or interleaved data On-chip 1.2 V reference Single 5 V or 3.3 V supply operation Power dissipation: 380 mW @ 5 V Power-down mode: 50 mW @ 5 V 48-lead LQFP
APPLICATIONS
Figure 1. GENERAL DESCRIPTION The AD97091 is a dual-port, high speed, 2-channel, 8-bit CMOS DAC. It integrates two high quality 8-bit TxDAC+® cores, a voltage reference, and digital interface circuitry into a small 48-lead LQFP package. The AD9709 offers exceptional ac and dc performance while supporting update rates of up to 125 MSPS. The AD9709 has been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs. A mode control pin allows the AD9709 to interface to two separate data ports, or to a single interleaved high speed data port. In inter- leaving mode, the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate. The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set by using a single external resistor. See the Gain Control Mode section for important date code information on this feature. The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. Each DAC provides differential current output, thus supporting single- ended or differential applications. Both DACs can be simultaneously updated and provide a nominal full-scale current of 20 mA. The full-scale currents between each DAC are matched to within 0.1%. 1 Patent pending. The AD9709 is manufactured on an advanced low-cost CMOS process. It operates from a single supply of 3.3 V or 5 V and consumes 380 mW of power. PRODUCT HIGHLIGHTS 1. The AD9709 is a member of a pin-compatible family of dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution. 2. Dual 8-Bit, 125 MSPS DACs. A pair of high performance DACs optimized for low distortion performance provide for flexible transmission of I and Q information. 3. Matching. Gain matching is typically 0.1% of full scale, and offset error is better than 0.02%. 4. Low Power. Complete CMOS dual DAC function operates at 380 mW from a 3.3 V or 5 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. On-Chip Voltage Reference. The AD9709 includes a 1.20 V temperature-compensated band gap voltage reference. 6. Dual 8-Bit Inputs. The AD9709 features a flexible dual- port interface, allowing dual or interleaved input data.
Rev. B | Page 2 of 32 TABLE OF CONTENTS Quadrature Amplitude Modulation (QAM) Using the
REVISION HISTORY
9/09—Rev. A to Rev. B 1/08—Rev. 0 to Rev. A Replaced Reference Control Amplifier Section with Setting 5/00—Revision 0: Initial Version
Rev. B | Page 3 of 32 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V , DVDD1 = DVDD2 = 3.3 V or 5 V , IOUTFS = 20 mA, unless otherwise noted. Table 1. Parameter Min Typ Max Unit RESOLUTION 8 Bits DC ACCURACY1 Integral Linearity Error (INL) −0.5 ±0.1 +0.5 LSB Differential Nonlinearity (DNL) −0.5 ±0.1 +0.5 LSB ANALOG OUTPUT Offset Error −0.02 +0.02 % of FSR Gain Error Without Internal Reference −2 ±0.25 +2 % of FSR Gain Error with Internal Reference −5 +1 +5 % of FSR Gain Match TMIN to TMAX −1.6 +1.6 % of FSR TMIN to TMAX −0.14 +0.14 dB Full-Scale Output Current2 2.0 20.0 mA Output Compliance Range −1.0 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V Reference Output Current3 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MΩ Small-Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift Without Internal Reference ±50 ppm of FSR/°C Gain Drift with Internal Reference ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD 3 5 5.5 V DVDD1, DVDD2 2.7 5 5.5 V Analog Supply Current (IAVDD) 71 75 mA Digital Supply Current (IDVDD)4 5 7 mA Digital Supply Current (IDVDD)5 15 mA Supply Current Sleep Mode (IAVDD) 8 12 mA Power Dissipation4 (5 V, IOUTFS = 20 mA) 380 410 mW Power Dissipation5 (5 V, IOUTFS = 20 mA) 420 450 mW Power Dissipation6 (5 V, IOUTFS = 20 mA) 450 mW Power Supply Rejection Ratio7 —AVDD −0.4 +0.4 % of FSR/V Power Supply Rejection Ratio7—DVDD1, DVDD2 −0.025 +0.025 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, IOUTFS, is 32 times the IREF current. 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at fCLK = 25 MSPS and fOUT = 1.0 MHz. 5 Measured at fCLK = 100 MSPS and fOUT = 1 MHz. 6 Measured as unbuffered voltage output with IOUTFS = 20 mA and RLOAD = 50 Ω at IOUTA and IOUTB, fCLK = 100 MSPS, and fOUT = 40 MHz. 7 ±10% power supply variation.
Rev. B | Page 4 of 32 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V , DVDD1 = DVDD2 = 3.3 V or 5 V , IOUTFS = 20 mA, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLK) 125 MSPS Output Settling Time (tST) to 0.1%1 35 ns Output Propagation Delay (tPD) 1 ns Glitch Impulse 5 pV-s Output Rise Time (10% to 90%)1 2.5 ns Output Fall Time (90% to 10%)1 2.5 ns Output Noise (IOUTFS = 20 mA) 50 pA/√Hz Output Noise (IOUTFS = 2 mA) 30 pA/√Hz AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLK = 100 MSPS, fOUT = 1.00 MHz 0 dBFS Output 63 68 dBc –6 dBFS Output 62 dBc –12 dBFS Output 56 dBc –18 dBFS Output 50 dBc fCLK = 65 MSPS, fOUT = 1.00 MHz 68 dBc fCLK = 65 MSPS, fOUT = 2.51 MHz 68 dBc fCLK = 65 MSPS, fOUT = 5.02 MHz 66 dBc fCLK = 65 MSPS, fOUT = 14.02 MHz 60 dBc fCLK = 65 MSPS, fOUT = 25 MHz 50 dBc fCLK = 125 MSPS, fOUT = 25 MHz 63 dBc fCLK = 125 MSPS, fOUT = 40 MHz 55 dBc Signal to Noise and Distortion Ratio fCLK = 50 MHz, fOUT = 1 MHz 50 dB Total Harmonic Distortion fCLK = 100 MSPS, fOUT = 1.00 MHz −67 −63 dBc fCLK = 50 MSPS, fOUT = 2.00 MHz −63 dBc fCLK = 125 MSPS, fOUT = 4.00 MHz −63 dBc fCLK = 125 MSPS, fOUT = 10.00 MHz −63 dBc Multitone Power Ratio (Eight Tones at 110 kHz Spacing) fCLK = 65 MSPS, fOUT = 2.00 MHz to 2.99 MHz 0 dBFS Output 58 dBc –6 dBFS Output 51 dBc –12 dBFS Output 46 dBc –18 dBFS Output 41 dBc Channel Isolation fCLK = 125 MSPS, fOUT = 10 MHz 85 dBc fCLK = 125 MSPS, fOUT = 40 MHz 77 dBc 1 Measured single-ended into 50 Ω load.
TMIN to TMAX, AVDD = 3.3 V or 5 V , DVDD1 = DVDD2 = 3.3 V or 5 V IOUTFS = 20 mA, unless otherwise noted. See Table 3 and the DAC Timing section for more information about the timing specifications. Figure 2. Timing for Dual and Interleaved Modes
soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance
Figure 3. Pin Configuration Table 6. Pin Function Descriptions
17 WRT1/IQWRT Input Write Signal for Port 1 (IQWRT in Interleaving Mode)
18 CLK1/IQCLK Clock Input for DAC1 (IQCLK in Interleaving Mode)
19 CLK2/IQRESET Clock Input for DAC2 (IQRESET in Interleaving Mode)
20 WRT2/IQSEL Input Write Signal for Port 2 (IQSEL in Interleaving Mode)
37 SLEEP Power-Down Control Input
38 ACOM Analog Common
41 FSADJ2 Full-Scale Current Output Adjust for DAC2
42 GAINCTRL Master/Slave Resistor Control Mode.
43 REFIO Reference Input/Output
44 FSADJ1 Full-Scale Current Output Adjust for DAC1
47 AVDD Analog Supply Voltage
48 MODE Mode Select (1 = dual port, 0 = interleaved)
Rev. B | Page 11 of 32 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full-scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of zero. For I OUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error Gain error is the difference between the actual and ideal output spans. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Output Compliance Range The output compliance range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. Temp er atu re D r i ft Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T MIN or TMAX. For offset and gain drift, the drift is reported in part per million (ppm) of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius (pm/°C). Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in picovolts per second (pV-s). Spurious-Free Dynamic Range The difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB).
Rev. B | Page 14 of 32 DAC TRANSFER FUNCTION Both DACs in the AD9709 provide complementary current out- puts, IOUTA and IOUTB. IOUTA provides a near full-scale current output, IOUTFS, when all bits are high (that is, DAC CODE = 256) while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as IOUTA = (DAC CODE/256) × IOUTFS (1) IOUTB = (255 − DAC CODE)/256 × IOUTFS (2) where DAC CODE = 0 to 255 (that is, decimal representation). IOUTFS is a function of the reference current (IREF), which is nominally set by a reference voltage (VREFIO) and an external resistor (RSET). It can be expressed as IOUTFS = 32 × IREF (3) where IREF = VREFIO/RSET (4) The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be connected directly to matching resistive loads, RLOAD, that are tied to the analog common, ACOM. Note that RLOAD can represent the equivalent load resistance seen by IOUTA or IOUTB, as would be the case in a doubly terminated 50 Ω or 75 Ω cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is VOUTA = IOUTA × RLOAD (5) VOUTB = IOUTB × RLOAD (6) Note the full-scale value of VOUTA and VOUTB must not exceed the specified output compliance range to maintain the specified distortion and linearity performance. VDIFF = (IOUTA − IOUTB) × RLOAD (7) Equation 7 highlights some of the advantages of operating the AD9709 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTA and IOUTB, such as noise, distortion, and dc offsets. Second, the differential code-dependent current and subsequent voltage, V DIFF, is twice the value of the single-ended voltage output (that is, VOUTA or VOUTB), thus providing twice the signal power to the load. Note that the gain drift temperature performance for a single- ended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9709 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship. ANALOG OUTPUTS The complementary current outputs, IOUTA and IOUTB, in each DAC can be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in Equation 5 through Equation 7. The differential voltage, VDIFF, existing between VOUTA and VOUTB can be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9709 is optimum and specified using a differential transformer-coupled output in which the voltage swing at I OUTA and IOUTB is limited to ±0.5 V . If a single-ended unipolar output is desirable, IOUTA should be selected. The distortion and noise performance of the AD9709 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (that is, assuming no source termination). Because the output currents of I OUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer allows the AD9709 to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kΩ in parallel with 5 pF . It is also slightly dependent on the output voltage (that is, V OUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration results in the optimum dc linearity. Note that the INL/DNL specifications for the AD9709 are measured with I OUTA maintained at a virtual ground via an op amp. IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of −1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9709. The positive output compliance range is slightly dependent on the full-scale output current, I OUTFS. When IOUTFS is decreased from 20 mA to 2 mA, the positive output compliance range degrades slightly from its nominal 1.25 V to 1.00 V . The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at I OUTA and IOUTB does not exceed 0.5 V . Applications requiring the AD9709 output (that is, VOUTA and/or VOUTB) to extend its output compliance range should size RLOAD accordingly. Operation beyond this compliance range adversely affects the linearity performance of the AD9709 and subsequently degrade its distortion performance.
maintain “clean” digital inputs. jitter manifesting itself as phase noise on a reconstructed waveform. family suitable for the application. more noticeable at higher sampling rates and output frequencies. required data setup and hold times. shows the relationship of SNR to clock/data placement. Figure 32. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS
component at a 90° phase shift with respect to the I component. signal at the specified carrier frequency. Figure 43. Typical Analog QAM Architecture proper gain and phase matching between the I and Q channels. AD8346 via matching networks.
0 TO IOUTFS
- DAC FULL-SCALE OUTPUT CURRENT = IOUTFS.
- RA, RB, AND RL ARE THIN FILM RESISTOR NETWORKS
FROM OHMTEK ORNXXXXD SERIES OR EQUIVALENT. Figure 44. Baseband QAM Implementation Using an AD9709 and AD8346
resolution, high speed conversion is required. Figure 46. Power Decoupling and Clocks on AD9709 Evaluation Board (1)
8 DS90LV048B
Figure 47. Power Decoupling and Clocks on AD9709 Evaluation Board (2)
2 LOCAL OSC INPUT
Figure 48. Modulator on AD9709 Evaluation Board
152 RP5
134 RP5
116 RP5
98 RP5
152 RP6
134 RP6
161 RP5
143 RP5
125 RP5
107 RP5
Figure 49. Digital Input Signaling (1)
Figure 50. Digital Input Signaling (2)
Figure 51. Device Under Test/Analog Output Signal Conditioning
Figure 52. Assembly, Top Side
Figure 53. Assembly, Bottom Side
Figure 54. 48-Lead Low Profile Quad Flat Package [LQFP] registered trademarks are the prop erty of their respective owners.