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8-/10-/12-/14-Bit, 175 MSPS TxDAC Digital-to-Analog Converters Data Sheet AD9704/AD9705/AD9706/AD9707 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 © 2006–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

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175 MSPS update rate

Low power member of pin-compatible TxDAC product family Low power dissipation 12 mW at 80 MSPS, 1.8 V 50 mW at 175 MSPS, 3.3 V Wide supply voltage: 1.7 V to 3.6 V SFDR to Nyquist AD9707: 84 dBc at 5 MHz output AD9707: 83 dBc at 10 MHz output AD9707: 75 dBc at 20 MHz output Adjustable full-scale current outputs: 1 mA to 5 mA On-chip 1.0 V reference CMOS-compatible digital interface Common-mode output: adjustable 0 V to 1.2 V Power-down mode <2 mW at 3.3 V (SPI controllable) Self-calibration Compact 32-lead LFCSP , RoHS compliant package GENERAL DESCRIPTION The AD9704/AD9705/AD9706/AD9707 are the fourth-generation family in the TxDAC series of high performance, CMOS digital-to- analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit resolution family is optimized for low power operation, while maintaining excellent dynamic performance. The AD9704/ AD9705/AD9706/AD9707 family is pin-compatible with the AD9748/AD9740/AD9742/AD9744 family of TxDAC converters and is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface, LFCSP package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9704/AD9705/AD9706/AD9707 offers exceptional ac and dc performance, while supporting update rates up to 175 MSPS. The flexible power supply operating range of 1.7 V to 3.6 V and low power dissipation of the AD9704/AD9705/AD9706/AD9707 parts make them well suited for portable and low power applications. Power dissipation of the AD9704/AD9705/AD9706/AD9707 can be reduced to 15 mW , with a small trade-off in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 2.2 mW . The AD9704/AD9705/AD9706/AD9707 has an optional serial peripheral interface (SPI®) that provides a higher level of program- mability to enhance performance of the DAC. An adjustable output, common-mode feature allows for easy interfacing to other components that require common modes from 0 V t o 1 . 2 V. Edge-triggered input latches and a 1.0 V temperature-compensated band gap reference have been integrated to provide a complete, monolithic DAC solution. The digital inputs support 1.8 V and 3.3 V CMOS logic families. PRODUCT HIGHLIGHTS 1. Pin Compatible. The AD9704/AD9705/AD9706/AD9707 line of TxDAC® converters is pin-compatible with the AD9748/AD9740/AD9742/AD9744 TxDAC line (LFCSP package). 2. Low Power. Complete CMOS DAC operates on a single supply of 3.6 V down to 1.7 V , consuming 50 mW (3.3 V) and 12 mW (1.8 V). The DAC full-scale current can be reduced for lower power operation. Sleep and power-down modes are provided for low power idle periods. 3. Self-Calibration. Self-calibration enables true 14-bit INL and DNL performance in the AD9707. 4. Twos Complement/Binary Data Coding Support. Data input supports twos complement or straight binary data coding. 5. Flexible Clock Input. A selectable high speed, single-ended, and differential CMOS clock input supports 175 MSPS conversion rate. 6. Device Configuration. Device can be configured through pin strapping, and SPI control offers a higher level of programmability. 7. Easy Interfacing to Other Components. Adjustable common-mode output allows for easy interfacing to other signal chain components that accept common-mode levels from 0 V to 1.2 V . 8. On-Chip Voltage Reference. The AD9704/AD9705/AD9706/ AD9707 include a 1.0 V temperature-compensated band gap voltage reference. 9. Industry-Standard 32-Lead LFCSP Package.

Data Sheet AD9704/AD9705/AD9706/AD9707 Rev. D | Page 3 of 42 Changes to Reference Operation Section and Reference Control Changes to Adjustable Output Common Mode Section and Changed Sleep and Power-Down Operation (Pin Mode) Section 4/2007— Rev. 0 to Rev. A Replaced Single-Ended Buffered Output Using an Op 7/2006— Revision 0: Initial Version

AD9704/AD9705/AD9706/AD9707 Data Sheet Rev. D | Page 4 of 42 FUNCTIONAL BLOCK DIAGRAM 0.1µF LSB SWITCHES SEGMENTED SWITCHES LATCHES CURRENT SOURCE ARRAY DIGITAL INPUTS (DB13 TO DB0) SLEEP/CSB CMODE/SCLK MODE/SDIOSPI IOUTB IOUTA OTCM REFIO FS ADJ CLKVDD CLKCOM CLK– CLK+ ACOMAVDD DVDD DCOM 1.0V REF R SET 1.7V TO 3.6V 1.7V TO 3.6V 1.7V TO 3.6V PIN/SPI/RESET AD9707 05926-001 Figure 1.

Data Sheet AD9704/AD9705/AD9706/AD9707 Rev. D | Page 5 of 42 SPECIFICATIONS DC SPECIFICATIONS (3.3 V) TMIN to TMAX, A VDD = 3.3 V , DVDD = 3.3 V , CLKVDD = 3.3 V , IOUTFS = 2 mA, unless otherwise noted. Table 1. AD9707 AD9706 AD9705 AD9704 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 14 12 10 8 Bits DC ACCURACY1 Integral Nonlinearity (INL) Precalibration Integral Nonlinearity (INL) Postcalibration Differential Nonlinearity (DNL) Precalibration Differential Nonlinearity (DNL) Postcalibration ANALOG OUTPUT Gain Error (With External Reference Gain Error (With Internal Reference) Full-Scale Output Current2 1 2 5 1 2 5 1 2 5 1 2 5 mA Output Compliance Range (From OTCM to IOUTA/IOUTB) Output Resistance 200 200 200 200 MΩ Output Capacitance 5 5 5 5 pF REFERENCE OUTPUT Reference Output Current3 100 100 100 100 nA REFERENCE INPUT Reference Input Resistance (Reference Powered Up) 10 10 10 10 kΩ Reference Input Resistance (Reference Powered Down) 1 1 1 1 MΩ TEMPERATURE COEFFICIENTS Offset Drift 0 0 0 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±29 ±29 ±29 ±29 ppm of FSR/°C Gain Drift (With Internal Reference) ±40 ±40 ±40 ±40 ppm of FSR/°C Reference Voltage Drift ±25 ±25 ±25 ±25 ppm/°C POWER SUPPLY Supply Voltage Power Dissipation4 50.2 57 48.5 57 46.9 57 45.5 57 mW Supply Current Sleep Mode (IAVDD)

AD9704/AD9705/AD9706/AD9707 Data Sheet Rev. D | Page 6 of 42 AD9707 AD9706 AD9705 AD9704 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Supply Current Power-Down Mode (IAVDD) Supply Current Clock Power- Down Mode (IDVDD)5 0.6 1 0.6 1 0.6 1 0.6 1 mA Supply Current Clock Power- Down Mode (ICLKVDD)5 42.5 64 42.5 64 42.5 64 42.5 64 µA Power Supply Rejection Ratio (AVDD)6 FSR/V OPERATING RANGE −40 +85 −40 +85 −40 +85 −40 +85 °C 1 Measured at IOUTA, driving a virtual ground. 2 Normal full scale current, IOUTFS is 32 × the IREF current. 3 Use an external buffer amplifier with an input bias current <100 nA to drive any external load. 4 Measured at fCLOCK = 175 MSPS and fOUT = 1.0 MHz, using a differential clock. 5 Measured at fCLOCK = 100 MSPS and fOUT = 1.0 MHz, using a differential clock. 6 ± 5% power supply variation. DYNAMIC SPECIFICATIONS (3.3 V) TMIN to TMAX, AVDD = 3.3 V , DVDD = 3.3 V , CLKVDD = 3.3 V , IOUTFS = 2 mA, differential transformer coupled output, 453 Ω differentially terminated unless otherwise noted. Table 2. AD9707 AD9706 AD9705 AD9704 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate, fCLOCK 175 175 175 175 MSPS Output Settling Time, tST (to 0.1%)1 11 11 11 11 ns Output Propagation Delay, tPD 4 4 4 4 ns Glitch Impulse 5 5 5 5 pV-s Output Rise Time (10% to 90%)1 2.5 2.5 2.5 2.5 ns Output Fall Time (10% to 90%)1 2.5 2.5 2.5 2.5 ns AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 10 MSPS, fOUT = 2.1 MHz 84 84 84 70 dBc fCLOCK = 25 MSPS, fOUT = 2.1 MHz 84 83 84 68 dBc fCLOCK = 65 MSPS, fOUT = 5.1 MHz 84 84 84 70 dBc fCLOCK = 65 MSPS, fOUT = 10.1 MHz 83 83 83 71 dBc fCLOCK = 80 MSPS, fOUT = 1.0 MHz 74 83 72 82 72 82 66 70 dBc fCLOCK = 125 MSPS, fOUT = 15.1 MHz 78 78 78 68 dBc fCLOCK = 125 MSPS, fOUT = 25.1 MHz 77 77 76 69 dBc fCLOCK = 175 MSPS, fOUT = 20.1 MHz 75 75 75 69 dBc fCLOCK = 175 MSPS, fOUT = 40.1 MHz 72 71 71 67 dBc Noise Spectral Density fCLOCK = 175 MSPS, fOUT = 6.0 MHz, IOUTFS = 2 mA − 152 − 152 − 144 − 136 dBc/Hz fCLOCK = 175 MSPS, fOUT = 6.0 MHz, IOUTFS = 5 mA − 161 dBc/Hz fCLOCK = 175 MSPS, fOUT = 6.0 MHz, IOUTFS = 1 mA − 146 dBc/Hz 1 Measured single-ended into 500 Ω load.

Data Sheet AD9704/AD9705/AD9706/AD9707 Rev. D | Page 7 of 42 DIGITAL SPECIFICATIONS (3.3 V) TMIN to TMAX, A VDD = 3.3 V , DVDD = 3.3 V , CLKVDD = 3.3 V , IOUTFS = 2 mA, unless otherwise noted. Table 3. AD9707 AD9706 AD9705 AD9704 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit DIGITAL INPUTS1 Logic 1 Voltage 2.1 3 2.1 3 2.1 3 2.1 3 V Logic 0 Voltage 0 0.9 0 0.9 0 0.9 0 0.9 V Logic 1 Current −10 +10 −10 +10 −10 +10 −10 +10 µA Logic 0 Current 10 10 10 10 µA Input Capacitance 5 5 5 5 pF Input Setup Time, tS, +25°C 1.4 1.4 1.4 1.4 ns Input Hold Time, tH, +25°C 0.3 0.3 0.3 0.3 ns Input Setup Time, tS, −40°C to +85°C 1.6 1.6 1.6 1.6 ns Input Hold Time, tH, −40°C to +85°C 0.6 0.6 0.6 0.6 ns Latch Pulse Width, tLPW 2.8 2.8 2.8 2.8 ns CLK INPUTS2 Input Voltage Range 0 3 0 3 0 3 0 3 V 1 Includes CLK+ pin in single-ended clock input mode. 2 Applicable to CLK+ input and CLK− input when configured for differential clock input mode.

AD9704/AD9705/AD9706/AD9707 Data Sheet Rev. D | Page 8 of 42 DC SPECIFICATIONS (1.8 V) TMIN to TMAX, A VDD = 1.8 V , DVDD = 1.8 V , CLKVDD = 1.8 V , IOUTFS = 2 mA, unless otherwise noted. Table 4. AD9707 AD9706 AD9705 AD9704 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 14 12 10 8 Bits DC ACCURACY1 Integral Nonlinearity (INL) Precalibration Differential Nonlinearity (DNL) Precalibration ANALOG OUTPUT Gain Error (With Internal Reference) Full-Scale Output Current2 1 2 2.5 1 2 2.5 1 2 2.5 1 2 2.5 mA Output Compliance Range (With OTCM = AGND) Output Resistance 200 200 200 200 MΩ Output Capacitance 5 5 5 5 pF REFERENCE OUTPUT Reference Output Current3 100 100 100 100 nA REFERENCE INPUT Reference Input Resistance (Reference Powered Up) 10 10 10 10 kΩ Reference Input Resistance (External Reference) 1 1 1 1 MΩ TEMPERATURE COEFFICIENTS Offset Drift 0 0 0 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±30 ±30 ±30 ±30 ppm of FSR/°C Gain Drift (With Internal Reference) ±60 ±60 ±60 ±60 ppm of FSR/°C Reference Voltage Drift ±25 ±25 ±25 ±25 ppm/°C POWER SUPPLY Supply Voltage Analog Supply Current (IAVDD)4 Digital Supply Current (IDVDD)4, 5 Clock Supply Current (ICLKVDD)4, 5 Supply Current Sleep Mode (IAVDD) Supply Current Power-Down Mode (IAVDD) 5 6 5 6 5 6 5 6 µA Supply Current Clock Power- Down Mode (IDVDD)5 Supply Current Clock Power- Down Mode (ICLKVDD)5 9.5 16 9.5 16 9.5 16 9.5 16 µA

Data Sheet AD9704/AD9705/AD9706/AD9707 Rev. D | Page 9 of 42 AD9707 AD9706 AD9705 AD9704 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Power Supply Rejection Ratio (AVDD)6 FSR/V OPERATING RANGE −40 +85 −40 +85 −40 +85 −40 +85 °C 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, IOUTFS, is 32 × the IREF current. 3 Use an external buffer amplifier with an input bias current <100 nA to drive any external load. 4 Measured at IOUTFS = 1 mA. 5 Measured at fCLOCK = 80 MSPS and fOUT = 1 MHz, using a differential clock. 6 ±5% power supply variation. DYNAMIC SPECIFICATIONS (1.8 V) TMIN to TMAX, AVDD = 1.8 V , DVDD = 1.8 V , CLKVDD = 1.8 V , IOUTFS = 1 mA, differential transformer coupled output, 453 Ω differentially terminated unless otherwise noted. Table 5. AD9707 AD9706 AD9705 AD9704 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate, fCLOCK 125 125 125 125 MSPS Output Settling Time, tST, (to 0.1%)1 11 11 11 11 ns Output Propagation Delay (tPD) 5.6 5.6 5.6 5.6 ns Glitch Impulse 5 5 5 5 pV-s Output Rise Time (10% to 90%)1 2.5 2.5 2.5 2.5 ns Output Fall Time (10% to 90%)1 2.5 2.5 2.5 2.5 ns AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 10 MSPS; fOUT = 2.1 MHz 86 86 85 70 dBc fCLOCK = 25 MSPS; fOUT = 2.1 MHz 87 86 84 68 dBc fCLOCK = 25 MSPS; fOUT = 5.1 MHz 82 82 82 68 dBc fCLOCK = 65 MSPS; fOUT = 10.1 MHz 82 79 78 70 dBc fCLOCK = 65 MSPS; fOUT = 15.1 MHz 77 76 74 69 dBc fCLOCK = 80 MSPS; fOUT = 1.0 MHz 74 82 72 82 72 82 66 70 dBc fCLOCK = 80 MSPS; fOUT = 15.1 MHz 77 77 77 68 dBc fCLOCK = 80 MSPS; fOUT = 30.1 MHz 60 59 59 60 dBc Noise Spectral Density fCLOCK = 80 MSPS; fOUT = 10 MHz; IOUTFS = 1 mA − 145 − 144 − 140 − 128 dBc/Hz fCLOCK = 80 MSPS; fOUT = 10 MHz; IOUTFS = 2 mA − 151 dBc/Hz 1 Measured single-ended into 500 Ω load.

TMIN to TMAX, A VDD = 1.8 V , DVDD = 1.8 V , CLKVDD = 1.8 V , IOUTFS = 1 mA, unless otherwise noted. 1 Includes CLK+ pin in single-ended clock input mode. 2 Applicable to CLK+ input and CLK– input when configured for differential clock input mode. Figure 2. Timing Diagram

in still air, in accordance with EIA/JESD51-7. Table 8. Thermal Resistance

IT IS RECOMMENDED THAT THE EXPOSED PAD BE

Figure 3. AD9707 Pin Configuration Table 9. AD9707 Pin Function Descriptions DB12 to DB1 Data Bit 12 to Data Bit 1. 3 DVDD Digital Supply Voltage (1.7 V to 3.6 V). DVDD, AV DD, and CLKVDD must be at the same supply voltage. 9 DB0 (LSB) Least Significant Data Bit (LSB). 11 CLKVDD Clock Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage. 12 CLK+ Positive Differential Clock Input. 13 CLK− Negative Differential Clock Input. complement. In SPI mode, this pin acts as SPI data input/output. operation. Pulse high to reset SPI registers to default values. 18 AVDD Analog Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage. 19 OTCM Adjustable Output Common Mode. Refer to the Theory of Operation section for details. 20 IOUTB Complementary DAC Current Output. Full-scal e current is sourced when all data bits are 0s. 21 IOUTA DAC Current Output. Full-scale curren t is sourced when all data bits are 1s. 24 FS ADJ Full-Scale Current Output Adjust. 25 SLEEP/CSB In pin mode, active high powers down chip. In SP I mode, this pin is the serial port chip select (active low). 27 DB13 (MSB) Most Significant Data Bit (MSB). electrical and thermal performance.

NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
IT IS RECOMMENDED THAT THE EXPOSED PAD BE

Figure 4. AD9706 Pin Configuration Table 10. AD9706 Pin Function Descriptions DB10 to DB1 Data Bit 10 to Data Bit 1. 3 DVDD Digital Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage. 7 DB0 (LSB) Least Significant Data Bit (LSB). 11 CLKVDD Clock Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage. 12 CLK+ Positive Differential Clock Input. 13 CLK− Negative Differential Clock Input. complement. In SPI mode, this pin acts as SPI data input/output. operation. Pulse high to reset SPI registers to default values. 18 AVDD Analog Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage. 19 OTCM Adjustable Output Common Mode. Refer to the Theory of Operation section for details. 20 IOUTB Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. 21 IOUTA DAC Current Output. Full-scale current is sourced when all data bits are 1s. 24 FS ADJ Full-Scale Current Output Adjust. 25 SLEEP/CSB In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low). 27 DB11 (MSB) Most Significant Data Bit (MSB). electrical and thermal performance.

NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
IT IS RECOMMENDED THAT THE EXPOSED PAD BE

Figure 5. AD9705 Pin Configuration Table 11. AD9705 Pin Function Descriptions DB8 to DB1 Data Bit 8 to Data Bit 1. 3 DVDD Digital Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage. 5 DB0 (LSB) Least Significant Data Bit (LSB). 11 CLKVDD Clock Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage. 12 CLK+ Positive Differential Clock Input. 13 CLK− Negative Differential Clock Input. CLK+ and float CLK–). Connect to CLKVDD for differential receiver. In SPI mode, this pin is the serial data clock input. complement. In SPI mode, this pin acts as SPI data input/output. operation. Pulse high to reset SPI registers to default values. 18 AVDD Analog Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage. 19 OTCM Adjustable Output Common Mode. Refer to the Theory of Operation section for details. 20 IOUTB Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. 21 IOUTA DAC Current Output. Full-scale current is sourced when all data bits are 1s. output when internal reference is activated. Requires a 0.1 µF capacitor to ACOM when internal reference is activated. 24 FS ADJ Full-Scale Current Output Adjust. 25 SLEEP/CSB In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low). 27 DB9 (MSB) Most Significant Data Bit (MSB). electrical and thermal performance.

NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
IT IS RECOMMENDED THAT THE EXPOSED PAD BE

Figure 6. AD9704 Pin Configuration Table 12. AD9704 Pin Function Descriptions 28 to 32, 1 DB6 to DB1 Data Bit 6 to Data Bit 1. 2 DB0 (LSB) Least Significant Data Bit (LSB). 3 DVDD Digital Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage. 11 CLKVDD Clock Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage. 12 CLK+ Positive Differential Clock Input. 13 CLK− Negative Differential Clock Input. and float CLK−). Connect to CLKVDD for differential receiver. In SPI mode, this pin is the serial data clock input. complement. In SPI mode, this pin acts as SPI data input/output. operation. Pulse high to reset SPI registers to default values. 18 AVDD Analog Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage. 19 OTCM Adjustable Output Common Mode. Refer to the Theory of Operation section for details. 20 IOUTB Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. 21 IOUTA DAC Current Output. Full-scale current is sourced when all data bits are 1s. when internal reference is activated. Requires a 0.1 µF capacitor to ACOM when internal reference is activated. 24 FS ADJ Full-Scale Current Output Adjust. 25 SLEEP/CSB In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low). 27 DB7 (MSB) Most Significant Data Bit (MSB). electrical and thermal performance.

Figure 13. SFDR vs. fOUT and OTCM @ 175 MSPS Figure 14. SFDR vs. AOUT and fCLOCK at fOUT = fCLOCK/5 Figure 15. NSD vs. fOUT and fCLOCK @ 0 dBFS Figure 16. NSD vs. fOUT and IOUTFS @ 175 MSPS Figure 17. Dual-Tone IMD vs. Lower fOUT and fCLOCK @ 0 dBFS Figure 18. Dual-Tone IMD vs. Lower fOUT and Temperature at 0 dBFS,

175 MSPS

VDD = 3.3 V , IOUTFS = 2 mA, unless otherwise noted. Figure 44. AD9704/AD9705/AD9706/AD9707 NSD vs. fOUT at 0 dBFS, Figure 45. AD9704 Typical Uncalibrated INL Figure 46. AD9704 Typical Uncalibrated DNL Figure 47. AD9705 Typical Uncalibrated INL Figure 48. AD9705 Typical Uncalibrated DNL Figure 49. AD9706 Typical Uncalibrated INL

Figure 56. AD9706Dual-Tone SFDR

Figure 69. AD9706 Dual-Tone SFDR

drawn from zero to full scale. to full scale, associated with a 1 LSB change in digital input code. increases or remains constant as the digital input increases. 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1. the gain error does not include effects of the reference. breakdown, resulting in nonlinear performance. and maximum specified voltages. measured from the start of the output transition. specified as the net area of the glitch in picovolt-seconds (pV-s). over the specified bandwidth. components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Figure 70. Basic AC Characterization Test Setup

data transfer cycle, none of the present data is written. writing to the last bit of each transfer byte. indicates a read operation. Logic 0 indicates a write operation. number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 14. Table 14. Byte Transfer Count during the entire communication cycle. line to transmit and receive data. must be written from most significant bit to least significant bit. data byte of the multibyte communication cycle. must be written from least significant bit to most significant bit. if the LSB first mode is active. register can occur during the middle of the communication cycle. for the remaining bytes of the current communication cycle. values except Register 0x00, which remains unchanged. prevent unexpected device behavior.

Table 16. SPI CTL— Register 0x00 SDIODIR 7 I 1 0 = SDIO pin configured for input only during data transfer (4-wire interface). 1 = SDIO pin configured for input or output during data transfer (3-wire interface). DATADIR 6 I 0 0 = Serial data uses MSB first format. 1 = Serial data uses LSB first format. SWRST 5 I 0 1 = i nitiates a software reset; this bit is set to 0 upon reset completion. LNGINS 4 I 0 0 = u ses 1 byte preamble (5 address bits). 1 = u ses 2 byte preamble (13 address bits). PDN 3 I 0 1 = s huts down DAC output current internal band gap reference. Sleep 2 I 0 1 = DAC output current off. CLKOFF 1 I 0 1 = d isables internal master clock. EXREF 0 I 0 0 = i nternal band gap reference. Table 17. Data— Register 0x02 DESKEW 3 I 0 0 = DESKEW mode disabled. Table 18. Version— Register 0x0D Table 19. CALMEM— Register 0x0E

Data Sheet AD9704/AD9705/AD9706/AD9707 Rev. D | Page 35 of 42 DAC TRANSFER FUNCTION The AD9704/AD9705/AD9706/AD9707 provide complementary current outputs, IOUTA and IOUTB. IOUTA provides a near full-scale current output, IOUTFS, when all bits are high (that is, DAC CODE = 2N − 1, where N = 8, 10, 12, or 14 for the AD9704, AD9705, AD9706, and AD9707, respectively), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as IOUTA = (DAC CODE/2N) × IOUTFS (1) IOUTB = ((2N − 1) − DAC CODE)/2N × IOUTFS (2) where DAC CODE = 0 to 2N − 1 (that is, decimal representation). IOUTFS is a function of the reference current, IREF, which is nominally set by a reference voltage, VREFIO, and an external resistor, RSET. It can be expressed as IOUTFS = 32 × IREF (3) where IREF = VREFIO/RSET (4) The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be connected to matching resistive loads (RLOAD) that are tied to analog common (ACOM). The single-ended voltage output appearing at the IOUTA and IOUTB nodes is VIOUTA = IOUTA × RLOAD (5) VIOUTB = IOUTB × RLOAD (6) To achieve the maximum output compliance of 1 V at the nominal 2 mA output current, RLOAD must be set to 500 Ω. Also, the full-scale value of VIOUTA and VIOUTB must not exceed the specified output compliance range to maintain specified distortion and linearity performance. VDIFF = (IOUTA – IOUTB) × RLOAD (7) Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be expressed as VDIFF = {(2 × DAC CODE – (2N − 1))/2N} × (32 × VREFIO/RSET) × RLOAD (8) Equation 7 and Equation 8 highlight some of the advantages of operating the AD9704/AD9705/AD9706/AD9707 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTA and IOUTB, such as noise, distortion, and dc offsets. Second, the differential code dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (that is, VIOUTA or VIOUTB), thus providing twice the signal power to the load. The gain drift temperature performance for a single-ended output (VIOUTA and VIOUTB) or the differential output (VDIFF) of the AD9704/AD9705/AD9706/AD9707 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET, because of their ratiometric relationship, as shown in Equation 8. ANALOG OUTPUTS The complementary current outputs in each DAC, IOUTA, and IOUTB can be configured for single-ended or differential oper- ation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VIOUTA and VIOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equation 5 through Equation 8. The differential voltage, VDIFF, existing between VIOUTA and VIOUTB, can also be converted to a single-ended voltage via a transformer or a differential amplifier configuration. The ac performance of the AD9704/AD9705/ AD9706/AD9707 is optimum and is specified using a differential transformer-coupled output in which the voltage swing at IOUTA and IOUTB is limited to ±0.5 V . The distortion and noise performance of the AD9704/AD9705/ AD9706/AD9707 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common- mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Because the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. When the AD9704/AD9705/AD9706/AD9707 is being used at its nominal operating point of 2 mA output current and 0.5 V output swing is desired, RLOAD must be set to 250 Ω. A properly selected transformer allows the AD9704/AD9705/AD9706/AD9707 to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 200 MΩ in parallel with 5 pF . It is also slightly dependent on the output voltage (that is, VIOUTA and VIOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration results in the optimum dc linearity. Note that the INL/DNL specifications for the AD9704/AD9705/AD9706/AD9707 are measured with IOUTA maintained at a virtual ground via an op amp. IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The absolute maximum negative output compliance range of −1 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit can result in a breakdown of the output stage and affect the reliability of the AD9704/AD9705/AD9706/AD9707.

nominal 1.0 V for an IOUTFS = 2 mA to 0.8 V for an IOUTFS = 1 mA. signal at IOUTA and IOUTB does not exceed 0.5 V . parts, allowing them to run at higher dc output bias voltages.

3.3 V , the parts perform optimally when the OTCM pin is tied

14, 12, 10, and 8 bits, respectively, and each has a clock input. the two outputs as a function of the input code. Figure 79. Equivalent Digital Input edges may affect digital feedthrough and distortion performance. transitions on the falling edge of a 50% duty cycle clock. set to 0, disabling the deskew mode. impedance. Table 24 gives a summary of clock mode control. Table 24. Clock Mode Selection wave into a single-ended square wave internally.

Figure 85. ICLKVDD vs. fCLOCK (Differential Clock Mode) at CLKVDD = 1.8 V writing a Logic 1 to the corresponding bit in Register 0x00. Table 25. Power-Down Mode Selection Figure 86. AD9707 SFDR vs. fOUT at 175 MSPS and IOUTFS = 2 mA Figure 87. IMD vs. Lower fOUT at 175 MSPS and IOUTFS = 2 mA

Enable the calibration clock by setting the CALCLK bit
Enable self-calibration by writing 0x40 to Register 0x0F.
Wait approximately 4500 calibration clock cycles. Each

256 DAC clock cycles, depending on the value of

Check if the self-calibration has completed by reading the
When the self-calibration has completed, write 0x00 to
Disable the calibration clock by clearing the CALCLK bit

Data Sheet AD9704/AD9705/AD9706/AD9707 Rev. D | Page 39 of 42 The AD9704/AD9705/AD9706/AD9707 devices allow reading and writing of the calibration coefficients. There are 33 coefficients in total. The read/write feature of the coefficients can be useful for improving the results of the self-calibration routine by averaging the results of several calibration results and loading the averaged results back into the device. The reading and writing routines follow. To read the calibration coefficients to the device: 1. Enable the calibration clock by setting the CALCLK bit (Register 0x02, Bit 0). 2. Write the address of the first coefficient (0x00) to Register 0x10. 3. Set the SMEMRD bit (Register 0x0F , Bit 2) by writing 0x04 to Register 0x0F. 4. Wait at least 160 CLK+/CLK− clock cycles. 5. Read the value of the first coefficient by reading the contents of Register 0x11. 6. Clear the SMEMRD bit by writing 0x00 to Register 0x0F . 7. Repeat Step 2 through Step 6 for each of the remaining 32 coefficients by incrementing the address by one for each read. 8. Disable the calibration clock by clearing the CALCLK Bit (Register 0x02, Bit 0). To write the calibration coefficients to the device: 1. Enable the calibration clock by setting the CALCLK bit (Register 0x02, Bit 0). 2. Set the SMEMWR bit (Register 0x0F , Bit 3) by writing 0x08 to Register 0x0F. 3. Write the address of the first coefficient (0x00) to Register 0x10. 4. Write the value of the first coefficient to Register 0x11. 5. Wait at least 160 CLK+/CLK− clock cycles 6. Repeat Step 3 through Step 5 for each of the remaining 32 coefficients by incrementing the address by one for each write. 7. Clear the SMEMWR bit by writing 0x00 to Register 0x0F. 8. Disable the calibration clock by clearing the CALCLK bit (Register 0x02, Bit 0).

a differential version of the single-ended buffer shown in Figure 89. Figure 90. Single-Supply Differential Buffer

3.50 REF

0.20 REF

0.65 TYP

0.05 MAX

0.02 NOM

0.60 MAX

0.25 MIN

Figure 91. 32-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the prop erty of their respective owners.

Summary

Digital-to-Analog Converters 11/2017-Rev. C to Rev. D

Description