AD9627ABCPZ-125

AD9627_17 AD | Alldatasheet

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Technical content

12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS,

1.8 V Dual Analog-to-Digital Converter

Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.

FEATURES

SNR = 69.4 dBc (70.4 dBFS) to 70 MHz @ 125 MSPS SFDR = 85 dBc to 70 MHz @ 125 MSPS Low power: 750 mW @ 125 MSPS SNR = 69.2 dBc (70.2 dBFS) to 70 MHz @ 150 MSPS SFDR = 84 dBc to 70 MHz @ 150 MSPS Low power: 820 mW @ 150 MSPS

1.8 V analog supply operation

1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS output supply Integer 1-to-8 input clock divider IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes Integrated receive features Fast detect/threshold bits Composite signal monitor

APPLICATIONS

Multimode digital receivers (3G) GSM, EDGE, WCDMA, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications FUNCTIONAL BLOCK DIAGRAM 06571-001 VIN+A VIN–A VREF SENSE VIN–B VIN+B D11A D0A CLK+ CLK– DCOA DCOB D11B D0B AGND SYNC FD(0:3)B ADC ADC SIGNAL MONITOR DATA AVDD DVDD FD(0:3)A DRGND PROGRAMMING DATA DRVDD FD BITS/THRESHOLD DETECT REF SELECT DUTY CYCLE STABILIZER MULTICHIP SYNC FD BITS/THRESHOLD DETECT SIGNAL MONITOR INTERFACE DCO GENERATION DIVIDE

1 TO 8

1.PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES. Figure 1. PRODUCT HIGHLIGHTS 1. Integrated dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/ 150 MSPS ADC. 2. Fast overrange detect and signal monitor with serial output. 3. Signal monitor block with dedicated serial output mode. 4. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 450 MHz. 5. Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. 6. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. 7. Pin compatibility with the AD9640, AD9627-11, and AD9600 for a simple migration from 12 bits to 14 bits, 11 bits, or 10 bits.

AD9627* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS

• AD9627 Evaluation Board DOCUMENTATION Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-742: Frequency Domain Response of Switched- Capacitor ADCs
• AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit
• AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs
• AN-835: Understanding High Speed ADC Testing and Evaluation
• AN-851: A WiMax Double Downconversion IF Sampling Receiver Design
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

• AN-935: Designing an ADC Transformer-Coupled Front End Data Sheet
• AD9627: 12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS,

1.8 V Dual Analog-to-Digital Converter Data Sheet

• Visual Analog
• AD9627 IBIS Models
• AD9627/AD9640 S-Parameters REFERENCE MATERIALS Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC DESIGN RESOURCES
• AD9627 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints DISCUSSIONS View all AD9627 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. B | Page 2 of 76 TABLE OF CONTENTS

Rev. B | Page 3 of 76

REVISION HISTORY

5/10—Rev. A to Rev. B Changed AD9627BCPZ-80 to AD9267-80 and Changed AD9627BCPZ-125 to AD9267-125 and 6/09—Rev. 0 to Rev. A Change to Signal Monitor Period (Register 0x113 10/07—Revision 0: Initial Version

Rev. B | Page 4 of 76 GENERAL DESCRIPTION The AD9627 is a dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/ 150 MSPS analog-to-digital converter (ADC). The AD9627 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design consid- erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The AD9627 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency. In addition, the programmable threshold detector allows moni- toring of the incoming signal power, using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has very low latency, the user can quickly turn down the system gain to avoid an overrange condition. The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. The ADC output data can be routed directly to the two external 12-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD9627 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

Rev. B | Page 5 of 76 SPECIFICATIONS ADC DC SPECIFICATIONS—AD9627-80/AD9627-105 enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 1. Parameter Temperature AD9627-80 AD9627-105 Unit Min Typ Max Min Typ Max RESOLUTION Full 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.2 ±0.6 ±0.3 ±0.7 % FSR Differential Nonlinearity (DNL)1 Full ±0.4 ±0.4 LSB 25°C ±0.2 ±0.2 LSB Integral Nonlinearity (INL)1 Full ±0.9 ±0.9 LSB 25°C ±0.4 ±0.4 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.2 ±0.6 ±0.3 ±0.7 % FSR Gain Error Full ±0.2 ±0.75 ±0.2 ±0.75 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 mV Load Regulation @ 1.0 mA Full 7 7 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.3 0.3 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance2 Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES Supply Voltage Supply Current IAVDD1, 3 Full 233 278 310 365 mA IDVDD1, 3 Full 26 34 mA IDRVDD1 (3.3 V CMOS) Full 23 34 mA IDRVDD1 (1.8 V CMOS) Full 11 15 mA IDRVDD1 (1.8 V LVDS) Full 47 47 mA POWER CONSUMPTION DC Input Full 452 490 600 650 mW Sine Wave Input1 (DRVDD = 1.8 V) Full 495 657 mW Sine Wave Input1 (DRVDD = 3.3 V) Full 550 740 mW Standby Power4 Full 52 68 mW Power-Down Power Full 2.5 6 2.5 6 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

Rev. B | Page 6 of 76 ADC DC SPECIFICATIONS—AD9627-125/AD9627-150 enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 2. Parameter Temperature AD9627-125 AD9627-150 Unit Min Typ Max Min Typ Max RESOLUTION Full 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.6 ±0.2 ±0.6 % FSR Differential Nonlinearity (DNL)1 Full ±0.4 ±0.9 LSB 25°C ±0.2 ±0.2 LSB Integral Nonlinearity (INL)1 Full ±0.9 ±1.3 LSB 25°C ±0.4 ±0.5 LSB MATCHING CHARACTERISTIC Offset Error 25°C ±0.3 ±0.6 ±0.2 ±0.7 % FSR Gain Error 25°C ±0.1 ±0.75 ±0.2 ±0.8 % FSR TEMPERATURE DRIFT Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 mV Load Regulation @ 1.0 mA Full 7 7 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.3 0.3 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance2 Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES Supply Voltage Supply Current IAVDD1, 3 Full 385 455 419 495 mA IDVDD1, 3 Full 42 50 mA IDRVDD1 (3.3 V CMOS) Full 36 42 mA IDRVDD1 (1.8 V CMOS) Full 18 22 mA IDRVDD1 (1.8 V LVDS) Full 48 49 mA POWER CONSUMPTION DC Input Full 750 800 820 890 mW Sine Wave Input1 (DRVDD = 1.8 V) Full 814 895 mW Sine Wave Input1 (DRVDD = 3.3 V) Full 900 995 mW Standby Power4 Full 77 77 mW Power-Down Power Full 2.5 6 2.5 6 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

Rev. B | Page 7 of 76 ADC AC SPECIFICATIONS—AD9627-80/AD9627-105 enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 3. Parameter1 Temperature AD9627-80 AD9627-105 Unit Min Typ Max Min Typ Max SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.3 MHz 25°C 69.7 69.6 dB fIN = 70 MHz 25°C 69.5 69.4 dB Full 68.1 68.6 dB fIN = 140 MHz 25°C 69.2 69.1 dB fIN = 220 MHz 25°C 68.5 68.4 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.3 MHz 25°C 69.6 69.5 dB fIN = 70 MHz 25°C 69.4 69.3 dB Full 67.4 68.0 dB fIN = 140 MHz 25°C 69.0 69.0 dB fIN = 220 MHz 25°C 68.3 68.1 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.3 MHz 25°C 11.5 11.4 Bits fIN = 70 MHz 25°C 11.4 11.4 Bits fIN = 140 MHz 25°C 11.4 11.4 Bits fIN = 220 MHz 25°C 11.3 11.2 Bits WORST SECOND OR THIRD HARMONIC fIN = 2.3 MHz 25°C −87 −87 dBc fIN = 70 MHz 25°C −85 −85 dBc Full −74 −74 dBc fIN = 140 MHz 25°C −84 −84 dBc fIN = 220 MHz 25°C −83 −83 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.3 MHz 25°C 87 87 dBc fIN = 70 MHz 25°C 85 85 dBc Full 74 74 dBc fIN = 140 MHz 25°C 84 84 dBc fIN = 220 MHz 25°C 83 83 dBc WORST OTHER HARMONIC OR SPUR fIN = 2.3 MHz 25°C −92 −92 dBc fIN = 70 MHz 25°C −89 −88 dBc Full −82 −82 dBc fIN = 140 MHz 25°C −89 −87 dBc fIN = 220 MHz 25°C −89 −86 dBc T W O - T O N E S F D R fIN = 29.1 MHz, 32.1 MHz (−7 dBFS ) 25°C 85 85 dBc fIN = 169.1 MHz, 172.1 MHz (−7 dBFS ) 25°C 82 82 dBc CROSSTALK2 Full −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 MHz 1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.

Rev. B | Page 8 of 76 ADC AC SPECIFICATIONS—AD9627-125/AD9627-150 enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 4. Parameter1 Temperature AD9627-125 AD9627-150 Unit Min Typ Max Min Typ Max SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.3 MHz 25°C 69.5 69.4 dB fIN = 70 MHz 25°C 69.4 69.2 dB Full 68.1 67.1 dB fIN = 140 MHz 25°C 69.1 68.8 dB fIN = 220 MHz 25°C 68.8 68.2 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.3 MHz 25°C 69.4 69.3 dB fIN = 70 MHz 25°C 69.3 69.1 dB Full 67.9 65.9 dB fIN = 140 MHz 25°C 69.0 68.7 dB fIN = 220 MHz 25°C 68.3 67.8 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.3 MHz 25°C 11.4 11.4 Bits fIN = 70 MHz 25°C 11.4 11.4 Bits fIN = 140 MHz 25°C 11.3 11.3 Bits fIN = 220 MHz 25°C 11.3 11.2 Bits WORST SECOND OR THIRD HARMONIC fIN = 2.3 MHz 25°C −86.5 −86.5 dBc fIN = 70 MHz 25°C −85 −84 dBc Full −74 −73 dBc fIN = 140 MHz 25°C −84 −83.5 dBc fIN = 220 MHz 25°C −83 −77 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.3 MHz 25°C 86.5 86.5 dBc fIN = 70 MHz 25°C 85 84 dBc Full 74 73 dBc fIN = 140 MHz 25°C 84 83.5 dBc fIN = 220 MHz 25°C 83 77 dBc WORST OTHER HARMONIC OR SPUR fIN = 2.3 MHz 25°C −92 −92 dBc fIN = 70 MHz 25°C −89 −88 dBc Full −81 −80 dBc fIN = 140 MHz 25°C −89 −88 dBc fIN = 220 MHz 25°C −89 −88 dBc TWO-TONE SFDR fIN = 29.1 MHz, 32.1 MHz (−7 dBFS ) 25°C 85 85 dBc fIN = 169.1 MHz, 172.1 MHz (−7 dBFS ) 25°C 82 82 dBc CROSSTALK2 Full −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 MHz 1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.

Rev. B | Page 9 of 76 DIGITAL SPECIFICATIONS enabled, unless otherwise noted. Table 5. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 1.2 V Input Voltage Range Full GND − 0.3 AVDD + 1.6 V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ LOGIC INPUT (CSB)1 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT (SCLK/DFS)2 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)1 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA

Rev. B | Page 10 of 76 Parameter Temperature Min Typ Max Unit Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage IOH = 50 μA Full 3.29 V IOH = 0.5 mA Full 3.25 V Low Level Output Voltage IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V CMOS Mode—DRVDD = 1.8 V High Level Output Voltage IOH = 50 μA Full 1.79 V IOH = 0.5 mA Full 1.75 V Low Level Output Voltage IOL = 1.6 mA Full 0.2 V IOL = 50 μA Full 0.05 V LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V 1 Pull up. 2 Pull down.

Rev. B | Page 11 of 76 SWITCHING SPECIFICATIONS—AD9627-80/AD9627-105 DCS enabled, unless otherwise noted. Table 6. Parameter Temperature AD9627-80 AD9627-105 Unit Min Typ Max Min Typ Max CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 MHz Conversion Rate DCS Enabled1 Full 20 80 20 105 MSPS DCS Disabled1 Full 10 80 10 105 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 12.5 9.5 ns CLK Pulse Width High Divide-by-2 Mode, DCS Enabled Full 1.6 1.6 ns Divide-by-3 Through Divide-by-8 Modes, DCS Enabled Full 0.8 0.8 ns DATA OUTPUT PARAMETERS (DATA, FD) CMOS Mode—DRVDD = 3.3 V Setup Time (tS) Full 6.25 5.25 ns Hold Time (tH) Full 5.75 4.25 ns CMOS Mode—DRVDD = 1.8 V Setup Time (tS) Full 6.65 5.15 ns Hold Time (tH) Full 5.85 4.35 ns LVDS Mode—DRVDD = 1.8 V CMOS Mode Pipeline Delay (Latency) Full 12 12 Cycles LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Full 12/12.5 12/12.5 Cycles Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 ps rms Wake-Up Time3 Full 350 350 μs OUT-OF-RANGE RECOVERY TIME Full 2 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors.

Rev. B | Page 12 of 76 SWITCHING SPECIFICATIONS—AD9627-125/AD9627-150 DCS enabled, unless otherwise noted. Table 7. Parameter Temperature AD9627-125 AD9627-150 Unit Min Typ Max Min Typ Max CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 MHz Conversion Rate DCS Enabled1 Full 20 125 20 150 MSPS DCS Disabled1 Full 10 125 10 150 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 8 6.66 ns CLK Pulse Width High Divide-by-2 Mode, DCS Enabled Full 1.6 1.6 ns Divide-by-3-Through-8 Mode, DCS Enabled Full 0.8 0.8 ns DATA OUTPUT PARAMETERS (DATA, FD) CMOS Mode—DRVDD = 3.3 V Setup Time (tS) Full 4.5 3.83 ns Hold Time (tH) Full 3.5 2.83 ns CMOS Mode—DRVDD = 1.8 V Setup Time (tS) Full 4.4 3.73 ns Hold Time (tH) Full 3.6 2.93 ns LVDS Mode—DRVDD = 1.8 V CMOS Mode Pipeline Delay (Latency) Full 12 12 Cycles LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Full 12/12.5 12/12.5 Cycles Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 ps rms Wake-Up Time3 Full 350 350 μs OUT-OF-RANGE RECOVERY TIME Full 3 3 Cycles 1 Conversion rate is the clock rate after the divider. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors.

Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)

the thermal capability of the package. Table 10. Thermal Resistance 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air).

1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.

Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View) Table 11. Pin Function Descriptions (Parallel CMOS Mode) 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the expo sed thermal pad on the bottom of the package. 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN−B Input Differential Analog Input Pin (−) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Table 14 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input—True. 50 CLK− Input ADC Clock Input—Complement. 29 FD0A Output Channel A Fast Detect Indicator. See Table 17 for details. 30 FD1A Output Channel A Fast Detect Indicator. See Table 17 for details. 31 FD2A Output Channel A Fast Detect Indicator. See Table 17 for details. 32 FD3A Output Channel A Fast Detect Indicator. See Table 17 for details. 53 FD0B Output Channel B Fast Detect Indicator. See Table 17 for details. 54 FD1B Output Channel B Fast Detect Indicator. See Table 17 for details. 55 FD2B Output Channel B Fast Detect Indicator. See Table 17 for details. 56 FD3B Output Channel B Fast Detect Indicator. See Table 17 for details.

Rev. B | Page 17 of 76 Pin No. Mnemonic Type Description Digital Input 52 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 14 D0A (LSB) Output Channel A CMOS Output Data. 15 D1A Output Channel A CMOS Output Data. 16 D2A Output Channel A CMOS Output Data. 17 D3A Output Channel A CMOS Output Data. 18 D4A Output Channel A CMOS Output Data. 19 D5A Output Channel A CMOS Output Data. 22 D6A Output Channel A CMOS Output Data. 23 D7A Output Channel A CMOS Output Data. 25 D8A Output Channel A CMOS Output Data. 26 D9A Output Channel A CMOS Output Data. 27 D10A Output Channel A CMOS Output Data. 28 D11A (MSB) Output Channel A CMOS Output Data. 60 D0B (LSB) Output Channel B CMOS Output Data. 61 D1B Output Channel B CMOS Output Data. 62 D2B Output Channel B CMOS Output Data. 63 D3B Output Channel B CMOS Output Data. 2 D4B Output Channel B CMOS Output Data. 3 D5B Output Channel B CMOS Output Data. 4 D6B Output Channel B CMOS Output Data. 5 D7B Output Channel B CMOS Output Data. 6 D8B Output Channel B CMOS Output Data. 7 D9B Output Channel B CMOS Output Data. 8 D10B Output Channel B CMOS Output Data. 9 D11B (MSB) Output Channel B CMOS Output Data. 11 DCOA Output Channel A Data Clock Output. 10 DCOB Output Channel B Data Clock Output. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Fo rmat Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Du ty Cycle Stabilizer Pin in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Signal Monitor Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Outp ut/Output Enable Input (Active Low) in External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock O utput/Power-Down Input in External Pin Mode.

1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.

Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View) Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode) 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the expo sed thermal pad on the bottom of the package. 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN−B Input Differential Analog Input Pin (−) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Table 14 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input—True. 50 CLK− Input ADC Clock Input—Complement. 54 FD0+ Output Channel A/Channel B LVDS Fast De tect Indicator 0—True. See Table 17 for details. 53 FD0− Output Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 17 for details. 56 FD1+ Output Channel A/Channel B LVDS Fast De tect Indicator 1—True. See Table 17 for details. 55 FD1− Output Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 17 for details. 59 FD2+ Output Channel A/Channel B LVDS Fast De tect Indicator 2—True. See Table 17 for details. 58 FD2− Output Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 17 for details. 61 FD3+ Output Channel A/Channel B LVDS Fast De tect Indicator 3—True. See Table 17 for details. 60 FD3− Output Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 17 for details. 52 SYNC Input Digital Synchronization Pin. Slave mode only.

Rev. B | Page 19 of 76 Pin No. Mnemonic Type Description Digital Outputs 5 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 4 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 7 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 6 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 9 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 8 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 13 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 12 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 15 D4+ Output Channel A/Channel B LVDS Output Data 4 —True. 14 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 17 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 16 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 19 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 18 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 23 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 22 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 26 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 25 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 28 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 27 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 30 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 29 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 32 D11+ (MSB) Output Channel A/Channel B LVDS Output Data 11—True. 31 D11− (MSB) Output Channel A/Channe l B LVDS Output Data 11—Complement. 11 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 10 DCO− Output Channel A/Channel B LV DS Data Clock Output—Complement. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Fo rmat Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Du ty Cycle Stabilizer Pin in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Signal Monitor Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock O utput/Power-Down Input in External Pin Mode.

0.3 LSB rms

Figure 40. AD9627 Grounded Input Histogram Figure 41. AD9627 INL with fIN = 10.3 MHz Figure 42. AD9627 DNL with fIN = 10.3 MHz Figure 43. AD9627-150 SNR/SFDR vs. Duty Cycle with fIN = 10.3 MHz Figure 44. AD9627-150 SNR/SFDR vs. Input Common Mode (VCM)

used for I input data, and the other is used for Q input data. timing between multiple channels or multiple devices. using a 3-bit SPI-compatible serial interface. combined into a final 12-bit result in the digital correction logic. preceding samples. Sampling occurs on the rising edge of the clock. can be ac- or dc-coupled in differential or single-ended modes. a separate supply, allowing adjustment of the output voltage swing. while processing a differential input signal. the sample capacitors and settling within 1/2 of a clock cycle. the precise values are dependent on the application. for more information on this subject (see www.analog.com). Figure 45. Switched-Capacitor SHA Input VIN+ and VIN− should be matched. core. The span of the ADC core is set by this buffer to 2 × VREF. The analog inputs of the AD9627 are not internally dc biased. is included in the design and is available from the CML pin. excellent performance and a flexible interface to the ADC.

sufficient output current to drive a wide variety of logic families. the supplies that may affect converter performance. or large fanouts may require external buffers or latches. in the external pin mode (see Table 15). binary, twos complement, or gray code when using the SPI control. Table 15. SCLK/DFS Mode Selection (External Pin Mode) high, the output data drivers are placed in a high impedance state. (DRVDD) and should not exceed that supply voltage. output enable bar bit in Register 0x14. delay (tPD) after the rising edge of the clock signal. should be minimized to reduce transients within the AD9627. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9627 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. for a graphical timing description. Table 16. Output Data Format

reliably determine when the converter is about to be clipped. mation on the state of the analog input that is of limited usefulness. significant slew rates, latency of this function is of major concern. resolution for this function. outside the desired range (magnitude). tion, allowing very flexible external gain control implementations. six configurations available for the fast detect pins. Table 17. Fast Detect Mode Select Bits Settings

000 ADC fast magnitude

001 ADC fast magnitude

010 ADC fast magnitude

011 ADC fast magnitude

100 OR C_UT F_UT F_LT

101 OR F_UT IG DG

1 The fast detect pins are FD0A/FD0B to FD9A/FD9B for the CMOS mode

2 See the ADC Overrange (OR) and Gain Switching sections for more

information about OR, C_UT, F_UT, F_LT, IG, and DG. datapath, there is significant uncertainty in the level indicated. ADC fast magnitude, are shown in Table 18. Table 18. ADC Fast Magnitude Nominal Levels with Fast Detect

modes, the fast detect output pins have a latency of six clock cycles. magnitude is presented on the FD[3:1] pins). Table 19. ADC Fast Magnitude Nominal Levels with Table 20. ADC Fast Magnitude Nominal Levels with input is indicated by this bit 12 clock cycles after it occurs. Table 21. Coarse Upper Threshold Levels threshold register located in Register 0x106 and Register 0x107. threshold register located at Register 0x108 and Register 0x109. compared with the signal magnitude at the output of the ADC. lower threshold indicators is shown in Figure 67.

before signaling external circuitry to increase the gain. gain output is shown in Figure 67. NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES. *C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY. Figure 67. Threshold Settings for C_UT, F_UT, IG, DG, and F_LT

bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS). register located at Register 0x10C, Bits[5:2]. 15 provides the same result as programming 13). CLK is the AD9627 ADC sample rate in hertz (Hz). value that can span the entire input range of the ADC. adds the currently calculated value to the data. drives all three SPORT output pins on the chip. into the signal path, if these prove to be a problem in the system. sync, followed by data from Datapath B. is sent MSB first on the next positive edge after the SMI SDFS. and threshold, as shown in Figure 71.

20 CYCLES 16 CYCLES16 CYCLES 20 CYCLES 16 CYCLES 16 CYCLES

Figure 71. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)

20 CYCLES 16 CYCLES 20 CYCLES 16 CYCLES

Figure 72. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)

Rev. B | Page 39 of 76 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9627 includes built-in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. A BIST (built-in self-test) feature is included that verifies the integrity of the digital datapath of the AD9627. Various output test options are also provided to place predictable values on the outputs of the AD9627. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9627 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath starting at the ADC block output. The BIST sequence runs for 512 cycles and stops. The BIST signature value for Channel A or Channel B is placed in Register 0x24 and Register 0x25. If one channel is chosen, its BIST signature is written to the two registers. If both channels are chosen, the results from Channel A are placed in the BIST signature registers. The outputs are not disconnected during this test, so the PN sequence can be observed as it runs. The PN sequence can be continued from its last value or reset from the beginning, based on the value programmed in Register 0x0E, Bit 2. The BIST signature result varies based on the channel configuration. OUTPUT TEST MODES The output test options are shown in Table 25. When an output test mode is enabled, the analog section of the ADC is discon- nected from the digital back end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The seed value for the PN sequence tests can be forced if the PN reset bits are used to hold the generator in reset mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see Application Note AN-877, Interfacing to High Speed ADCs via SPI.

Rev. B | Page 40 of 76 CHANNEL/CHIP SYNCHRONIZATION The AD9627 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful for guaranteeing synchro- nized sample clocks across multiple ADCs. The signal monitor block can also be synchronized using the SYNC input, allowing properties of the input signal to be measured during a specific time period. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The signal monitor block is synchronized on every SYNC input signal. The SYNC input is internally synchronized to the sample clock; however, to ensure there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 8. The SYNC input should be driven using a single- ended CMOS-type signal.

disables the read and write cycles. Table 22. Serial Port Interface Pins synchronize serial interface reads and writes. on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. (SDIO) pin to change direction from an input to an output. at the appropriate point in the serial frame. Based Serial Port Interface (SPI) Boot Circuit. tioning at the converter inputs during critical sampling periods. functions supported on the AD9627.

Table 23. Mode Selection following Table 25, the external memory map register table. Table 24. Features Accessible Using the SPI Figure 73. Serial Port Interface Timing Diagram

Rev. B | Page 43 of 76 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x25); and the digital feature control registers (Address 0x100 to Address 0x11B). The memory map register table (see Table 25) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x18, the VREF select register, has a hexadecimal default value of 0xC0. This means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This setting is the default reference selection setting. The default value uses a 2.0 V p-p reference. For more information on this function and others, see Application Note AN-877, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers, from Register 0x100 to Register 0x11B, are documented in the Memory Map Register Description section. Open Locations All address and bit locations that are not included in Table 25 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD9627 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 25. Logic Levels An explanation of logic level terminology follows:  “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit. ”  “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” Transfer Register Map Address 0x08 to Address 0x18 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simulta- neously when the transfer bit is set. The internal update takes place when the transfer bit is set, and the bit autoclears. Channel-Specific Registers Some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 25 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 25 affect the entire part or the channel features where independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits.

All address and bit locations that are not included in Table 25 are not currently supported for this device. Table 25. Memory Map Registers

0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles

Rev. B | Page 45 of 76 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0x0E BIST Enable (Local) Open Open Open Open Open Reset BIST sequence Open BIST enable 0x00 0x10 Offset Adjust (Local) Open Open Offset adjust in LSBs from +31 to −32 (twos complement format) 0x00 0x14 Output Mode Drive strength 0 V to 3.3 V CMOS or ANSI LVDS; 1 V to 1.8 V CMOS or reduced LVDS (global) Output type 0 = CMOS 1 = LVDS (global) Open Output enable bar (local) Open Output invert (local) 00 = offset binary 01 = twos complement 01 = gray code 11 = offset binary (local) 0x00 Configures the outputs and the format of the data 0x16 Clock Phase Control (Global) Invert DCO clock Open Open Open Open In put clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x00 Allows selection of clock delays into the input clock divider 0x17 DCO Output Delay (Global) Open Open Open DCO clock delay (delay = 2500 ps × register value/31) 00000 = 0 ps 00001 = 81 ps 00010 = 161 ps 11110 = 2419 ps 11111 = 2500 ps 0x00 0x18 VREF Select (Global) Reference voltage selection 00 = 1.25 V p-p 01 = 1.5 V p-p 10 = 1.75 V p-p 11 = 2.0 V p-p (default) Open Open Open Open Open Open 0xC0 0x24 BIST Signature LSB (Local) BIST Signature[7:0] 0x00 Read only 0x25 BIST Signature MSB (Local) BIST Signature[15:8] 0x00 Read only Digital Feature Control 0x100 Sync Control (Global) Signal monitor sync enable Open Open Open Open Clock divider next sync only Clock divider sync enable Master sync enable 0x00 0x104 Fast Detect Control (Local) Open Open Open Open Fast De tect Mode Select[2:0] Fast detect enable 0x00 0x105 Coarse Upper Threshold (Local) Open Open Open Open Open Coarse Upper Threshold[2:0] 0x00 0x106 Fine Upper Threshold Register 0 (Local) Fine Upper Threshold[7:0] 0x00 0x107 Fine Upper Threshold Register 1 (Local) Open Open Open Fine Upper Threshold[12:8] 0x00 0x108 Fine Lower Threshold Register 0 (Local) Fine Lower Threshold[7:0] 0x00

Rev. B | Page 46 of 76 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0x109 Fine Lower Threshold Register 1 (Local) Open Open Open Fine Lower Threshold[12:8] 0x00 0x10A Increase Gain Dwell Time Register 0 (Local) Increase Gain Dwell Time[7:0] 0x00 In ADC clock cycles 0x10B Increase Gain Dwell Time Register 1 (Local) Increase Gain Dwell Time[15:8] 0x00 In ADC clock cycles 0x10C Signal Monitor DC Correction Control (Global) Open DC correction freeze DC Correction Bandwidth[3:0] DC correction for signal path enable DC correction for signal monitor enable 0x00 0x10D Signal Monitor DC Value Channel A Register 0 (Global) DC Value Channel A[7:0] Read only 0x10E Signal Monitor DC Value Channel A Register 1 (Global) Open Open DC Value Channel A[13:8] Read only 0x10F Signal Monitor DC Value Channel B Register 0 (Global) DC Value Channel B[7:0] Read only 0x110 Signal Monitor DC Value Channel B Register 1 (Global) Open Open DC Value Channe l B[13:8] Read only 0x111 Signal Monitor SPORT Control (Global) Open RMS/MS magnitude output enable Peak detector output enable Threshold crossing output enable SPORT SMI SCLK divide 00 = undefined 01 = divide by 2 10 = divide by 4 11 = divide by 8 SPORT SMI SCLK sleep Signal monitor SPORT output enable 0x04 0x112 Signal Monitor Control (Global) Complex power calculation mode enable Open Open Open Signal monitor rms/ms select 0 = rms 1 = ms Signal monitor mode 00 = rms/ms magnitude 01 = peak detector 10 = threshold crossing 11 = threshold crossing Signal monitor enable 0x00 0x113 Signal Monitor Period Register 0 (Global) Signal Monitor Period[7:0] 0x80 In ADC clock cycles 0x114 Signal Monitor Period Register 1 (Global) Signal Monitor Period[15:8] 0x00 In ADC clock cycles 0x115 Signal Monitor Period Register 2 (Global) Signal Monitor Period[23:16] 0x00 In ADC clock cycles 0x116 Signal Monitor Result Channel A Register 0 (Global) Signal Monitor Result Channel A[7:0] Read only

Rev. B | Page 47 of 76 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0x117 Signal Monitor Result Channel A Register 1 (Global) Signal Monitor Result Channel A[15:8] Read only 0x118 Signal Monitor Result Channel A Register 2 (Global) Open Open Open Open Signal Monitor Value Channel A[19:16] Read only 0x119 Signal Monitor Result Channel B Register 0 (Global) Signal Monitor Result Channel B[7:0] Read only 0x11A Signal Monitor Result Channel B Register 1 (Global) Signal Monitor Result Channel B[15:8] Read only 0x11B Signal Monitor Result Channel B Register 2 (Global) Open Open Open Open Signal Monitor Result Channel B[19:16] Read only MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see Application Note AN-877, Interfacing to High Speed ADCs via SPI. Sync Control (Register 0x100) Bit 7—Signal Monitor Sync Enable Bit 7 enables the sync pulse from the external SYNC input to the signal monitor block. The sync signal is passed when Bit 7 and Bit 0 are high. This is continuous sync mode. Bits[6:3]—Reserved Bit 2—Clock Divider Next Sync Only If the master sync enable bit (Address 0x100, Bit0) and the clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit (Address 0x100, Bit 1) resets after it syncs. Bit 1—Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider. The sync signal is passed when Bit 1 is high and Bit 0 is high. This is continuous sync mode. Bit 0—Master Sync Enable Bit 0 must be high to enable any of the sync functions. Fast Detect Control (Register 0x104) Bits[7:4]—Reserved Bits[3:1]—Fast Detect Mode Select These bits set the mode of the fast detect output pins (see Table 17). Bit 0—Fast Detect Enable Bit 0 is used to enable the fast detect output pins. When the fast detect output pins are disabled, the outputs go into a high impedance state. In LVDS mode, when the outputs are interleaved, the outputs go high-Z only if both channels are turned off (power-down/standby/output disabled). If only one channel is turned off (power-down/standby/output disabled), the fast detect output pins repeat the data of the active channel. Coarse Upper Threshold (Register 0x105) Bits[7:3]—Reserved Bits[2:0]—Coarse Upper Threshold These bits set the level required to assert the coarse upper threshold indication (see Table 21). Fine Upper Threshold (Register 0x106 and Register 0x107) Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0] Register 0x107, Bits[7:5]—Reserved Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8] These registers provide the fine upper limit threshold. This 13-bit value is compared with the 13-bit magnitude from the ADC block. If the ADC magnitude exceeds this threshold value, the F_UT flag is set. Fine Lower Threshold (Register 0x108 and Register 0x109) Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0] Register 0x109, Bits[7:5]—Reserved Register 0x109, Bits[4:0]—Fine Lower Threshold[12:8] These registers provide the fine lower limit threshold. This 13-bit value is compared with the 13-bit magnitude from the ADC block. If the ADC magnitude is less than this threshold value, the F_LT flag is set.

Rev. B | Page 48 of 76 Increase Gain Dwell Time (Register 0x10A and Register 0x10B) Register 0x10A, Bits[7:0]—Increase Gain Dwell Time[7:0] Register 0x10B, Bits[7:0]—Increase Gain Dwell Time[15:8] These registers are programmed with the dwell time in ADC clock cycles for which the signal must be below the fine lower threshold value before the increase gain output is asserted. Signal Monitor DC Correction Control (Register 0x10C) Bit 7—Reserved Bit 6—DC Correction Freeze When Bit 6 is set high, the dc correction is no longer updated to the signal monitor block. It holds the last dc value it calculated. Bits[5:2]—DC Correction Bandwidth These bits set the averaging time of the power monitor dc correction function. This 4-bit word sets the bandwidth of the correction block according to the following equation: 22 _ _14 CLKk fBW Corr DC where: k is the 4 bit value programmed in Register 0x10C, Bits[5:2] (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). fCLK is the AD9627 ADC sample rate in hertz (Hz). Bit 1—DC Correction for Signal Path Enable Setting Bit 1 high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path. Bit 0—DC Correction for Signal Monitor Enable Bit 0 enables the dc correction function in the signal monitor block. The dc correction is an averaging function that can be used by the signal monitor to remove dc offset in the signal. Removing this dc offset from the measurement allows a more accurate reading. Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E) Register 0x10D, Bits[7:0]—DC Value Channel A[7:0] Register 0x10E, Bits[7:6]—Reserved Register 0x10E, Bits[5:0]—DC Value Channel A[13:8] These read-only registers hold the latest dc offset value computed by the signal monitor for Channel A. Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x10F , Bits[7:0]—DC Value Channel B[7:0] Register 0x110, Bits[7:6]—Reserved Register 0x110, Bits[5:0]—DC Value Channel B[13:8] These read-only registers hold the latest dc offset value computed by the signal monitor for Channel B. Signal Monitor SPORT Control (Register 0x111) Bit 7—Reserved Bit 6—RMS/MS Magnitude Output Enable These bits enable the 20-bit rms or ms magnitude measurement as output on the SPORT. Bit 5—Peak Detector Output Enable Bit 5 enables the 13-bit peak measurement as output on the SPORT. Bit 4—Threshold Crossing Output Enable Bit 4 enables the 13-bit threshold measurement as output on the SPORT . Bits[3:2]—SPORT SMI SCLK Divide The values of these bits set the SPORT SMI SCLK divide ratio from the input clock. A value of 0x01 sets divide by 2 (default), a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8. Bit 1— SPORT SMI SCLK Sleep Setting Bit 1 high causes the SMI SCLK to remain low when the signal monitor block has no data to transfer. Bit 0—Signal Monitor SPORT Output Enable When set, Bit 0 enables the SPORT output of the signal monitor to begin shifting out the result data from the signal monitor block. Signal Monitor Control (Register 0x112) Bit 7—Complex Power Calculation Mode Enable This mode assumes I data is present on one channel and Q data is present on the alternate channel. The result reported is the complex power, measured as 2 2Q I Bits[6:4]—Reserved Bit 3—Signal Monitor RMS/MS Select Setting Bit 3 low selects rms power measurement mode. Setting Bit 3 high selects ms power measurement mode. Bits[2:1]—Signal Monitor Mode Bit 2 and Bit 1 set the mode of the signal monitor for data output to Register 0x116 through Register 0x11B. Setting Bit 2 and Bit 1 to 0x00 selects rms/ms magnitude output; setting these bits to 0x01 selects peak detector output; and setting these bits to 0x10 or 0x11 selects threshold crossing output. Bit 0—Signal Monitor Enable Setting Bit 0 high enables the signal monitor block.

Rev. B | Page 49 of 76 Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits[7:0]—Signal Monitor Period[7:0] Register 0x114, Bits[7:0]—Signal Monitor Period[15:8] Register 0x115, Bits[7:0]—Signal Monitor Period[23:16] This 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. The minimum value for this register is 128 cycles; programmed values less than 128 revert to 128. Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits[7:0]—Signal Monitor Result Channel A[7:0] Register 0x117, Bits[7:0]—Signal Monitor Result Channel A[15:8] Register 0x118, Bits[7:4]—Reserved Register 0x118, Bits[3:0]—Signal Monitor Result Channel A[19:16] This 20-bit value contains the result calculated by the signal monitoring block for Channel A. The result is dependent on the settings in Register 0x112[2:1]. Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x119, Bits[7:0]— Signal Monitor Result Channel B[7:0] Register 0x11A, Bits[7:0]—Signal Monitor Result Channel B[15:8] Register 0x11B, Bits[7:4]—Reserved Register 0x11B, Bits[3:0]—Signal Monitor Result Channel B[19:16] This 20-bit value contains the result calculated by the signal monitoring block for Channel B. The result is dependent on the settings in Register 0x112[2:1].

Rev. B | Page 50 of 76 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9627 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9627, it is recommended that two separate 1.8 V supplies be used: one supply should be used for analog (AVDD) and digital (DVDD), and a separate supply should be used for the digital outputs (DRVDD). The AVDD and DVDD supplies, while derived from the same source, should be isolated with a ferrite bead or filter choke and separate decoupling capacitors. The designer can employ several different decoupling capacitors to cover both high and low frequencies. These capacitors should be located close to the point of entry at the PC board level and close to the pins of the part with minimal trace length. A single PCB ground plane should be sufficient when using the AD9627. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. LVDS Operation The AD9627 defaults to CMOS output mode on power-up. If LVDS operation is desired, this mode must be programmed using the SPI configuration registers after power-up. When the AD9627 powers up in CMOS mode with LVDS termination resistors (100 Ω) on the outputs, the DRVDD current can be higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage to the AD9627, but it should be taken into account when consid- ering the maximum DRVDD current for the part. To avoid this additional DRVDD current, the AD9627 outputs can be disabled at power-up by taking the OEB pin high. After the part is placed into LVDS mode via the SPI port, the OEB pin can be taken low to enable the outputs. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask), copper plane on the PCB should mate to the AD9627 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. See the evalua- tion board for a PCB layout example. For detailed information about packaging and PCB layout of chip scale packages, see Application Note AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). CML The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 47. RBIAS The AD9627 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. Reference Decoupling The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9627 to keep these signals from transitioning at the converter inputs during critical sampling periods.

Rev. B | Page 52 of 76 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9627 evaluation board. POWER Connect the switching power supply that is provided in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P500. VIN The evaluation board is set up for a double balun configuration analog input with optimum 50 Ω impedance matching from 70 MHz to 200 MHz. For more bandwidth response, the differ- ential capacitor across the analog inputs can be changed or removed (see Table 13). The common mode of the analog inputs is developed from the center tap of the transformer via the CML pin of the ADC (see the Analog Input Considerations section). VREF VREF is set to 1.0 V by tying the SENSE pin to ground by adding a jumper on Header J5 (Pin 1 to Pin 2). This causes the ADC to operate in 2.0 V p-p full-scale range. To place the ADC in 1.0 V p-p mode (VREF = 0.5 V), a jumper should be placed on Header J4. A separate external reference option is also included on the evalua- tion board. To use an external reference, connect J6 (Pin 1 to Pin 2) and provide an external reference at TP5. Proper use of the VREF options is detailed in the Voltage Reference section. RBIAS RBIAS requires a 10 kΩ resistor (R503) to ground and is used to set the ADC core bias current. CLOCK The default clock input circuitry is derived from a simple balun- coupled circuit using a high bandwidth 1:1 impedance ratio balun (T5) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single- ended sine wave inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. When the AD9627 input clock divider is utilized, clock frequencies up to 625 MHz can be input into the evaluation board through Connector S5. PDWN To enable the power-down feature, connect J7, shorting the PDWN pin to AVDD. CSB The CSB pin is internally pulled up, setting the chip into external pin mode, to ignore the SDIO and SCLK information. To connect the control of the CSB pin to the SPI circuitry on the evaluation board, connect J21, Pin 1 to J21, Pin 2. SCLK/DFS If the SPI port is in external pin mode, the SCLK/DFS pin sets the data format of the outputs. If the pin is left floating, the pin is inter- nally pulled down, setting the default data format condition to offset binary. Connecting J2, Pin 1 to J2, Pin 2 sets the format to twos complement. If the SPI port is in serial pin mode, connecting J2, Pin 2 to J2, Pin 3 connects the SCLK pin to the on-board SPI circuitry (see the Serial Port Interface (SPI) section). SDIO/DCS If the SPI port is in external pin mode, the SDIO/DCS pin sets the duty cycle stabilizer. If the pin is left floating, the pin is internally pulled up, setting the default condition to DCS enabled. To disable the DCS, connect J1, Pin 1 to J1, Pin 2. If the SPI port is in serial pin mode, connecting J1, Pin 2 to J1, Pin 3 connects the SDIO pin to the on-board SPI circuitry (see the Serial Port Interface (SPI) section). ALTERNATIVE CLOCK CONFIGURATIONS Two alternate clocking options are provided on the AD9627 evaluation board. The first option is to use an on-board crystal oscillator (Y1) to provide the clock input to the part. To enable this crystal, Resistor R8 (0 Ω) and Resistor R85 (10 kΩ) should be installed, and Resistor R82 and Resistor R30 should be removed. A second clock option is to use a differential LVPECL clock to drive the ADC input using the AD9516 (U2). When using this drive option, the AD9516 charge pump filter components need to be populated (see Figure 79). Consult the AD9516 data sheet for more information. To configure the clock input from S5 to drive the AD9516 reference input instead of directly driving the ADC, the following components need to be added, removed, and/or changed. Remove R32, R33, R99, and R101 in the default clock path. 2. Populate C78 and C79 with 0.001 μF capacitors and R78 and R79 with 0 Ω resistors in the clock path. In addition, unused AD9516 outputs (one LVDS and one LVPECL) are routed to optional Connector S8 through Connector S11 on the evaluation board.

Rev. B | Page 53 of 76 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this particular drive option, some additional components need to be populated. For more details on the AD8352 differential driver, including how it works and its optional pin settings, consult the AD8352 data sheet. To configure the analog input to drive the AD8352 instead of the default transformer option, the following components need to be added, removed, and/or changed for Channel A. For Channel B the corresponding components should be changed. Remove C1, C17, C18, and C117 in the default analog input path. 2. Populate C8 and C9 with 0.1 μF capacitors in the analog input path. To drive the AD8352 in the differential input mode, populate the T10 transformer; the R1, R37, R39, R126, and R127 resistors; and the C10, C11, and C125 capacitors. Populate the optional amplifier output path with the desired components including an optional low-pass filter. Install 0 Ω resistors, R44 and R48. R43 and R47 should be increased (typically to 100 Ω) to increase to 200 Ω the output impedance seen by the AD8352.

57.6 OH M

33 OHM

100 OH M

0 OH M

33 OH M

24.9 OH M

Figure 75. Evaluation Board Schematic, Channel A Analog Inputs

Figure 76. Evaluation Board Schematic, Channel B Analog Inputs

57.6 OHM

24.9 OHM

Figure 77. Evaluation Board Schematic, DUT Clock Input

49.9 OHM

100 OHM

Figure 78. Evaluation Board Schematic, Optional AD9516 Clock Circuit

Figure 79. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input

1 TP3

Figure 80. Evaluation Board Schematic, DUT

Figure 81. Evaluation Board Schematic, Digital Output Interface

Figure 82. Evaluation Board Schematic, SPI Circuitry

261 OHM

140 KOHM

78.7 KOHM

Figure 83. Evaluation Board Schematic, Power Supply

3 ADP333 9

78.7 KOH M

140 KOH M

Figure 84. Evaluation Board Schematic, Power Supply (Continued)

Figure 85. Evaluation Board Layout, Primary Side

Figure 86. Evaluation Board Layout, Ground Plane

Figure 87. Evaluation Board Layout, Power Plane

Figure 88. Evaluation Board Layout, Power Plane

Figure 89. Evaluation Board Layout, Ground Plane

Figure 90. Evaluation Board Layout, Secondary Side (Mirrored Image)

Figure 91. Evaluation Board Layout, Silkscreen, Primary Side

Figure 92. Evaluation Board Layout, Silkscreen, Secondary Side

Table 26. Evaluation Board Bill of Materials (BOM)1, 2

Rev. B | Page 73 of 76 Item Qty Reference Designator Description Package Manufacturer Mfg. Part Number 26 1 R16 261 Ω, 0603, 1/10 W, 1% resistor R0603 NIC Components NRC06F2610TRF 27 3 R17, R22, R23 100 kΩ, 0603, 1/10 W, 1% resistor R0603 NIC Components NRC06F 1003TRF 28 7 R18, R24, R63, R65, R82, R118, R140 10 kΩ, 0402, 1/16 W, 1% resistor R0402SM NIC Components NRC04F 1002TRF 29 3 R19, R20, R21 1 kΩ, 0603, 1/10 W, 1% resistor R0603 NIC Components NRC06F 1001TRF 30 9 R26, R27, R43, R46, R47, R70, R71, R73, R74 33 Ω, 0402, 1/16 W, 5% resistor R0402SM NIC Components NRC04J330TRF 31 5 R57, R59 to R62 22 Ω, 16-pin, 8-resistor, resistor array R_742 CTS Corporation 742C163220JPTR 32 1 R58 22 Ω, 8-pin, 4-resistor, resistor array RES_ARRY CTS Corporation 742C083220JPTR 33 1 R76 200 Ω, 0402, 1/16 W, 1% resistor R0402SM NIC Components NCR04F2000TRF 34 4 S2, S3, S5 ,S12 SMA, inline, male, coaxial connector SMA_EDGE Emerson Network Power 142-0701-201 35 1 SJ35 0 Ω, 1/8 W, 1% resistor SLDR_PAD2MUYLAR NIC Components NRC10ZOTRF 36 5 T1 to T5 Balun TRAN6B M/A-COM MABA-007159-000000 37 1 U1 IC, AD9627 LFCSP64-9X9-9E Analog Devices AD9627BCPZ 38 1 U2 Clock distribution, PLL IC LFCSP64-9X9 Analog Devices AD9516-4BCPZ 39 1 U3 Dual inverter IC SC70_6 Fairchild Semiconductor NC7WZ04P6X_NL 40 1 U7 Dual buffer IC, open-drain circuits SC70_6 Fairchild Semiconductor NC7WZ07P6X_NL 41 1 U8 UHS dual buffer IC SC70_6 Fairchild Semiconductor NC7WZ16P6X_NL 42 3 U15 to U17 16-bit CMOS buffer IC TSOP48_8_1MM Fairchild Semiconductor 74VCX16244MTDX_NL 43 2 VR1, VR2 Adjustable regulator LFC SP8-3X3 Analog Devices ADP3334ACPZ 44 1 VR3 1.8 V high accuracy regulator SO T223-HS Analog Devices ADP3339AKCZ-1.8 45 1 VR4 5.0 V high accuracy regulator SOT223-HS Analog Devices ADP3339AKCZ-5.0 46 2 VR5, VR6 3.3 V high accuracy regulato r SOT223-HS Analog Devices ADP3339AKCZ-3.3 47 1 Y1 Oscillator clock, VFAC3 OSC-CTS-CB3 Valpey Fisher VFAC3-BHL 48 2 Z1, Z2 High speed IC, op amp LFCSP16-3X3-PAD Analog Devices AD8352ACPZ 1 This bill of materials is RoHS compliant. 2 The bill of materials lists only those items that are normally installed in the default condition. Items that are not installed are not included in the BOM.

0.22 MINTOP VIEW

0.20 REF

0.65 TYP

0.05 MAX

0.02 NOM

0.60 MAX

Figure 93. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. B | Page 75 of 76 NOTES

Rev. B | Page 76 of 76 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06571-0-5/10(B)