AD9626

AD9626 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 36

Technical content

12-Bit, 170 MSPS/210 MSPS/250 MSPS,

1.8 V Analog-to-Digital Converter

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.

FEATURES

SNR = 64.8 dBFS @ fIN up to 70 MHz @ 250 MSPS ENOB of 10.5 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) SFDR = 80 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) Excellent linearity DNL = ±0.3 LSB typical INL = ±0.7 LSB typical CMOS outputs Single data port at up to 250 MHz Interleaved dual port @ ½ sample rate up to 125 MHz

700 MHz full power analog bandwidth

On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation 272 mW @ 170 MSPS 364 mW @ 250 MSPS Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal

1.8 V analog and digital supply operation

Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock

APPLICATIONS

Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization FUNCTIONAL BLOCK DIAGRAM AGNDPWDNRBIAS AVDD (1.8V) VIN+ VIN– CML TRACK-AND-HOLD REFERENCE ADC 12-BIT CORE OUTPUT STAGING LVDS CLK+ CLK– CLOCK MANAGEMENT SERIAL PORT RESET SCLK SDIO CSB DCO– DCO+ OVRB OVRA Dx11 TO Dx0 DRGND DRVDD 12 12 AD9626 07099-001 Figure 1. GENERAL DESCRIPTION The AD9626 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary func- tions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differen- tial clock for full performance operation. The digital outputs are CMOS compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9626 is available in a 56-lead LFCSP , specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS with a 70 MHz input. 2. Low Power—Consumes only 364 mW @ 250 MSPS. 3. Ease of Use—CMOS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. 4. Serial Port Control—Standard serial port interface supports various product functions, such as data formatting, clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. 5. Pin-Compatible Family—10-bit pin-compatible family offered as the AD9601.

Rev. 0 | Page 2 of 36 TABLE OF CONTENTS

REVISION HISTORY

11/07—Revision 0: Initial Version

Rev. 0 | Page 3 of 36 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V , DRVDD = 1.8 V , TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V , single port output mode, DCS enabled, unless otherwise noted. Table 1. AD9626-170 AD9626-210 AD9626-250 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 12 12 Bits A C C U R A C Y No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error 25°C 4.0 4.0 4.0 mV Full −12 +12 −12 +12 −12 +12 mV Gain Error 25°C 1.4 1.4 1.4 % FS Differential Nonlinearity (DNL) 25°C 0.3 0.3 0.3 LSB Integral Nonlinearity (INL) 25°C 0.7 0.6 0.7 LSB T E M P E R A T U R E D R I F T Offset Error Full ±8 ±8 ±8 μV/°C Gain Error Full 0.021 0.021 0.021 %/°C ANALOG INPUTS (VIN+, VIN−) Input Common-Mode Voltage Full 1.4 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 4.3 kΩ Input Capacitance 25°C 2 2 2 pF P O W E R S U P P L Y S u p p l y C u r r e n t s IAVDD3 Full 134 143 151 161 178 191 mA IDRVDD3/Single Port Mode4 Full 17 18.5 21 22 24 25.5 mA IDRVDD3/Interleaved Mode5 Full 15 18 20 mA Power Dissipation3 F u l l m W Single Port Mode4 Full 272 291 310 330 364 390 mW Interleaved Mode5 Full 268 304 357 mW Power-Down Mode Supply Currents IAVDD Full 40 40 40 μA IDRVDD Full 170 170 22 170 μA S t a n d b y M o d e S u p p l y C u r r e n t s IAVDD Full 19 19 19 mA IDRVDD Full 170 170 22 170 μA 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9626. 5 Interleaved mode; user-programmable feature. See the Memory Map section.

Rev. 0 | Page 4 of 36 AC SPECIFICATIONS AVDD = 1.8 V , DRVDD = 1.8 V , TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V , , Single Port Output mode, DCS enabled, unless otherwise noted.1 Table 2. AD9626-170 AD9626-210 AD9626-250 Parameter2 Temp Min Typ Max Min Typ Max Min Typ Max Unit S N R fIN = 10 MHz 25°C 64.5 64.4 64.0 dB Full 63.6 63.0 dB fIN = 70 MHz 25°C 64.4 64.2 63.8 dB Full 63.0 62.3 dB S I N A D fIN = 10 MHz 25°C 64.5 64.4 64.0 dB Full 63.5 62.8 dB fIN = 70 MHz 25°C 64.2 64.0 63.4 dB Full 62.6 62.0 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 10.6 10.6 10.5 Bits fIN = 70 MHz 25°C 10.5 10.5 10.5 Bits WORST HARMONIC (SECOND OR THIRD) fIN = 10 MHz 25°C 84 86 83 dBc Full 75 77 73 dBc fIN = 70 MHz 25°C 79 79 80 dBc Full 71 73 71 dBc WORST OTHER (SFDR EXCLUDING SECOND AND THIRD) fIN = 10 MHz 25°C 92 90 84 dBc Full 85 79 76 dBc fIN = 70 MHz 25°C 92 87 84 dBc Full 81 77 73 dBc T W O - T O N E I M D 140.2 MHz/141.3 MHz @ −7 dBFS 25°C 80 dBFS 170.2 MHz/171.3 MHz @ −7 dBFS 25°C 83 83 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

Rev. 0 | Page 5 of 36 DIGITAL SPECIFICATIONS Table 3. AD9626-170 AD9626-210 AD9626-250 Parameter1 T emp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUTS Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 1.2 1.2 V Differential Input Voltage Full 0.2 6 0.2 6 0.2 6 V p-p Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 AVDD − 0.3 AVDD + 1.6 AVDD − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD 1.1 AVDD 1.1 AVDD V Low Level Input Voltage (VIL) Full 0 0.8 0 0.8 0 0.8 V Input Resistance (Differential) Full 16 20 24 16 20 24 16 20 24 kΩ Input Capacitance Full 4 4 4 pF LOGIC INPUTS Logic 1 Voltage Full 0.8 × AVDD 0.8 × AVDD 0.8 × AVDD V Logic 0 Voltage Full 0.2 × AVDD 0.2 × AVDD 0.2 × AVDD V Logic 1 Input Current (SDIO) Full 0 0 0 μA Logic 0 Input Current (SDIO) Full −60 −60 −60 μA Logic 1 Input Current (SCLK, PDWN, CSB, RESET) Full 55 55 50 μA Logic 0 Input Current (SCLK, PDWN, CSB, RESET) Full 0 0 0 μA Input Capacitance 25°C 4 4 4 pF LOGIC OUTPUTS2 High Level Output Voltage Full DRVDD − 0.05 DRVDD − 0.05 DRVDD − 0.05 V Low Level Output Voltage Full GND + 0.05 GND + 0.05 GND + 0.05 V Output Coding Twos complement, Gray code, or offset binary (default) 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 LVDS RTERMINATION = 100 Ω.

Rev. 0 | Page 6 of 36 SWITCHING SPECIFICATIONS Table 4. AD9626-170 AD9626-210 AD9626-250 Parameter (Conditions) Temp Min Typ Max Min Typ Max Min Typ Max Unit Maximum Conversion Rate Full 170 210 250 MSPS Minimum Conversion Rate Full 40 40 40 MSPS Output, Single Data Port Mode1 Data Propagation Delay (tPD) 25°C 3.7 3.7 3.7 ns DCO Propagation Delay (tCPD) 25°C 3.4 3.4 3.4 ns Latency Full 6 6 6 Cycles Output, Interleaved Mode2 Data Propagation Delay (tPDA, tPDB) 25°C 3.5 3.5 3.5 ns DCO Propagation Delay (tCPDA, tCPDB) 25°C 3.0 3.0 3.0 ns Latency Full 6 6 6 Cycles Standby Recovery 25°C 250 250 250 ns Power-Down Recovery 50 50 50 μs Aperture Delay (tA) 25°C 0.1 0.1 0.1 ns Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 0.2 ps rms 1 See Figure 2. 2 See Figure 3.

Rev. 0 | Page 8 of 36 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating ELECTRICAL AVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +2.0 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −2.0 V to +2.0 V Dx0 Through Dx11 to DRGND −0.3 V to DRVDD + 0.3 V DCO+/DCO− to DRGND −0.3 V to DRVDD + 0.3 V OVRA/OVRB to DGND −0.3 V to DRVDD + 0.3 V CLK+ to AGND −0.3 V to +3.6 V CLK− to AGND −0.3 V to +3.6 V VIN+ to AGND −0.3 V to AVDD + 0.2 V VIN− to AGND −0.3 V to AVDD + 0.2 V SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V PDWN to AGND −0.3 V to +3.6 V CSB to AGND −0.3 V to +3.6 V SCLK/DFS to AGND −0.3 V to +3.6 V ENVIRONMENTAL Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 6. Package Type θJA θJC Unit 56-Lead LFCSP (CP-56-2) 30.4 2.9 °C/W Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA. In addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes reduces the θJA. ESD CAUTION

35 VIN+

36 VIN–

37 AVDD

38 AVDD

39 AVDD

40 CML

41 AVDD

42 AVDD

34 AVDD

33 AVDD

32 AVDD

31 RBIAS

30 AVDD

29 PWDN

Figure 4. Pin Configuration Table 7. Single Data Rate Mode Pin Function Descriptions 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 8, 23, 48 DRGND1 Digital Output Ground. 36 VIN− Analog Input—Complement. optimized internal bias voltage for VIN+/VIN−. 45 CLK− Clock Input—Complement. 31 RBIAS Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V. 28 RESET CMOS-Compatible Chip Reset (Active Low). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 DA0 (LSB) Output Port A Output Bit 0 (LSB). 52 DA1 Output Port A Output Bit 1. 53 DA2 Output Port A Output Bit 2. 54 DA3 Output Port A Output Bit 3. 55 DA4 Output Port A Output Bit 4. 56 DA5 Output Port A Output Bit 5. 1 DA6 Output Port A Output Bit 6. 2 DA7 Output Port A Output Bit 7.

Rev. 0 | Page 10 of 36 Pin No. Mnemonic Description 3 DA8 Output Port A Output Bit 8. 4 DA9 Output Port A Output Bit 9. 5 DA10 Output Port A Output Bit 10. 6 DA11 (MSB) Output Port A Output Bit 11 (MSB). 9 OVRA Output Port A Overrange Output Bit. 10 DB0 (LSB) Output Port B Output Bit 0 (LSB). 11 DB1 Output Port B Output Bit 1. 12 DB2 Output Port B Output Bit 2. 13 DB3 Output Port B Output Bit 3. 14 DB4 Output Port B Output Bit 4. 15 DB5 Output Port B Output Bit 5. 16 DB6 Output Port B Output Bit 6. 17 DB7 Output Port B Output Bit 7. 18 DB8 Output Port B Output Bit 8. 19 DB9 Output Port B Output Bit 9. 20 DB10 Output Port B Output Bit 10. 21 DB11 (MSB) Output Port B Output Bit 11 (MSB). 22 OVRB Output Port B Overrange Output Bit. 1 AGND and DRGND should be tied to a common quiet ground plane.

Figure 41. Offset vs. Temperature

where aperture jitter may affect the dynamic range of the AD9626. be retimed by the original clock at the last step. performance as it relates to ADCs (visit www.analog.com).

16 BITS

14 BITS

12 BITS

10 BITS

8 BITS

Figure 50. Ideal SNR vs. Input Frequency and Jitter for 0 dBFS input Signal DRVDD supply and bias current of the LVDS output drivers. low returns the AD9626 into its normal operational mode. operation after allowing for the pipeline latency. to reduce switching transient effects on performance. example of the output coding format can be found in Table 11. ment, see the AD9626 Configuration Using the SPI section. Figure 3 for more information. Figure 51. OVRA/OVRB remains high until range low conditions can be detected. Figure 51. OVRA/OVRB Relation to Input Voltage and Output Data

Rev. 0 | Page 21 of 36 TIMING—SINGLE PORT MODE In single port mode, the CMOS output data is available from Data Port A (DA0 to DA11). The outputs for Port B (DB0 to DB11) are unused, and are high impedance in this mode. The Port A outputs and the differential output data clock (DCO+/DCO−) switch nearly simultaneously during the rising edge of DCO+. In this mode, it is recommended to use the rising edge of DCO− to capture the data from Port A. The setup and hold time depends on the input sample clock period, and is approximately 1/f CLK ± tSKEW. TIMING—INTERLEAVED MODE In interleaved mode, the output data of the AD9626 is demultiplexed onto two data port buses, Port A (DA0 to DA11) and Port B (DB0− to DB11). The output data and differential data capture clock switch at one-half the rate of the sample clock input (CLK+/CLK−), increasing the setup and hold time for the external data capture circuit relative to single port mode (see Figure 3, interleaved mode timing diagram). The two ports switch on alternating sample clock cycles, with the data for Port A being valid during the rising edge of DCO+, and the data for Port B being valid during the rising edge of DCO−. The pipeline latency for both ports is six sample clock cycles. Due to the random nature of the ÷2 circuit that generates the timing for the output stage in interleaved mode, the first data sample during power up can be assigned to either Data Port A or Port B. The user cannot control the polarity of the output data clock relative to the input sample clock. In this mode, it is recom- mended to use the rising edge of DCO+ to capture the data from Port A, and the rising edge of DCO− to capture the data from Port B. In both cases, the setup and hold time depends on the input sample clock period, and both are approximately 2/f S ± tSKEW. fS/2 Spurious Because the AD9626 output data rate is at one-half the sampling frequency in interleaved output mode, there is significant fS/2 energy in the outputs of the part, and there will be significant energy in the ADC output spectrum at fS /2. Care must be taken to be certain that this fS/2 energy does not couple into either the clock circuit or the analog inputs of the AD9626. When fS/2 energy is coupled in this fashion, it appears as a spurious tone reflected around f S/4, 3fS/4, 5fS/4, and so on. For example, in a

125 MSPS sampling application with a 90 MHz single-tone

analog input, this energy generates a tone at 97.5 MHz. [(3 × 125 MSPS/4 − 90 MHz) + 3 × 125 MSPS/4] Depending on the relationship of the IF frequency to the center of the Nyquist zone, this spurious tone may or may not be in the user’s band of interest. Some residual fS/2 energy is present in the AD9601, and the level of this spur is typically below the level of the harmonics at clock rates. Figure 20 shows a plot of the fS/2 spur level vs. the analog input frequency for the AD9626-250. For the specifications provided in Table 2, the fS/2 spur effect is not a factor, as the device is specified in single port output mode.

resistor (suggested value of 10 kΩ). ground, which disables the serial port interface. Table 9. Mode Selection strappable functions supported on the AD9626. Figure 53. Serial Port Interface Timing Diagram

Table 10. Serial Timing Definitions Table 11. Output Data Format

Each row in the memory map table has eight address locations. (Address 0x08 to Address 0x2A). Address 0x09, clock, has a hexadecimal default value of 0x01. have a 0 written into their registers during power-up. Table 12. Memory Map Register

Rev. 0 | Page 26 of 36 Addr (Hex) Parameter Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 09 clock 0 0 0 0 0 0 0 Duty cycle stabilizer: 0 = disabled 1 = enabled (default) 0x01 OD test_io Reset PN23 gen: 1 = on 0 = off (default) Reset PN9 gen: 1 = on 0 = off (default) Output test mode: 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checker board output 0101 = PN 23 sequence 0110 = PN 9 0111 = one/zero word toggle 1000 = unused 1001 = unused 1010 = unused 1011 = unused 1100 = unused (Format determined by output_mode) 0x00 When set, the test data is placed on the output pins in place of normal data. OF ain_config 0 0 0 0 0 Analog input disable: 1 = on 0 = off (default) CML enable: 1 = on 0 = off (default) 0 0x00 14 output_mode 0 0 Interleave output mode: 1 = enabled 0 = disabled (default) Output enable: 0 = enable (default) 1 = disable

0 Output

invert: 1 = on 0 = off (default) Data format select: 00 = offset binary (default) 01 = twos complement 10 = Gray code 0x00 16 output_phase Output clock polarity 1 = inverted 0 = normal (default) 0 0 0 0x03 17 flex_output_delay Output delay enable: 0 = enable 1 = disable Output clock delay: 00000 = 0.1 ns 00001 = 0.2 ns 00010 = 0.3 ns 11101 = 3.0 ns 11110 = 3.1 ns 11111 = 3.2 ns 0x00 18 flex_vref Input voltage range setting: 10000 = 0.98 V 10001 =1.00 V 10010 = 1.02 V 10011 =1.04 V 11111 = 1.23 V 00000 = 1.25 V 00001 = 1.27 V 01110 = 1.48 V 01111 = 1.50 V 0x00

0 L90

0 DNP

Figure 54. AD9601 Evaluation Board Schematic Page 1

Figure 55. AD9601 Evaluation Board Schematic Page 2

Figure 56. AD9601 Evaluation Board Schematic Page 3

Figure 57. AD9601 Evaluation Board Schematic Page 4 Table 13. Bill of Materials

7 C1, C3, C4, C5,

6 C8, C9, C11,

7 C27, C32, C33,

6 C28, C29, C30,

402 Capacitor, 120 pF , ceramic, C0G, 25 V, 5% Murata GRM1555C1H121JA01J

10 C21, C22, C23,

1 CR4 603 LED green, SMT, 0603, SS-TYPE Panasonic LNJ314G8TRA

1 CR2 Mini 3P Diode, 30 V, 20 mA Agilent HSMS2812

15 E1, E2, E3, E4,

2 J2, J3 SMA end

10 L2, L3, L4, L5,

1206 Ferrite bead, BLM, 3 A, 50 Ω @ 100 MHz Murata BLM31PG500SN1L

1 R1 201 Resistor, 100 Ω, 0201, 1/20 W, 1% NIC Components NRC02F1000TRF

1 R2 603 Resistor, 499 Ω, 0603, 1/10 W, 1% NIC Components NRC06F4990TRF

Rev. 0 | Page 31 of 36 Qty Reference Designator Package Description Vendor Part Number

2 R5, R6 402 Resistor, 36 Ω, 0402, 1/16 W, 1% Panasonic ERJ-2GEJ360X

2 R7, R16 402 Resistor, 15 Ω, 0402, 1/16 W, 5% Panasonic ERJ-2RKF15R0X

6 R10, R11, R13,

R24, R25, R27

402 Resistor, 1 kΩ, 0402, 1/16 W, 1% NIC Components NRC04F1001TRF

4 R12, R18, R19,

R26,

402 Resistor, 10 kΩ, 0402, 1/16 W, 5% NIC Components NRC04J103TRF

7 R15, C16, C18,

C19, C20, R89, R90

402 Resistor, 0 Ω, 0402, 1/16 W, 5% NIC Components NRC04ZOTRF

4 RN1, RN2, RN3,

0402x8 Resistor array, SMT 0402; 0 Ω, ¼ W, 5%, RESNEXB-2HV Panasonic EXB2HV050JV

3 L1, L8, L9 603 Resistor, 0 Ω, 0603, 1/10 W, 5% NIC Components NRC06ZOTRF

1 P9, P10 805 Resistor, 0 Ω, 0805, 1/8 W, 1% NIC Components NRC10ZOTRF

1 SW3 EVQ-

Switch, light touch SMD Panasonic P12937SCT-ND

1 T1 2020 Ferrite bead, 5 A, 50 V, 190 Ω @ 100 MHz Murata DLW5BSN191SQ2L

2 T2,T3 CD542 Transformer, 0.5 W, 30 mA Mini-Circuits ADT1-1WT+

1 U3 6-SC70 IC, buffer, inverter, UHS dual SC70-6 Fairchild NC7WZ16P6X

1 U5 6-SC70 IC, buffer, inverter, UHS dual OD out SC70-6 Fairchild NC7WZ07P6X

1 U7 DO-214AA Diode, 50 V, 2 A Micro Commercial S2A-TPMSTR-ND

1 U8 DO-214AB Diode, 30 V, 3 A (SMC) Micro Commercial SK33-TPMSCT-ND

1 U11 SOT-223 Voltage regulator, 3.3 V, 1.5 A Analog Devices ADP3339AKCZ-3.3 2 U9, U12 SOT-223 Voltage regulator, 1.8 V, 1.5 A Analog Devices ADP3339AKCZ-1.8

1 U4 LFCSP56 AD9230 12-bit, 170 MSPS/210 MSPS/250 MSPS,

1.8 V ADC, LFCSP-56

Analog Devices AD9230BCPZ-xxx

2 P7, P11 HM-Zd PCB Connector, 2-Pr, 10-column, high speed, HM-Zd,

Do not install the following:

0 C2, C54 TAJD Capacitor, tantalum, SMT 6032, 10 μF , 16 V, 10% Kemet T491C106K016AS

0 C15, C37, C38,

C40, C41, C61, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53, C39, C56, C57, C58, C59, C74, C75, C60, C66, C67, C68, C69, C72 402 Capacitor, 0.1 μF, ceramic, 10% Murata GRM155R71C104KA88D

0 CR1 Led_ss LED green, USS type 0603 Panasonic LNJ314G8TRA

0 CR3 Diode Schottky diode Agilent HSMS2812

0 805 Tyco/Raychem NANOSMDC110F-2

0 E6, E15, E16,

E17, E18, E19, E20 Connector, header, 0.1" Samtec TSW-150-08-G-S

0 J1 10-pin

TSW-110-08-G-D Samtec TSW-110-08-G-D

0 J4 SMA Connector, PCB coax SMA end launch,

0 L6 1206 Inductor, 10 nH Murata BLM31P500S

0 P12, P13, P14,

SMA Amphenol RF ARFX1231-ND

Rev. 0 | Page 32 of 36 Qty Reference Designator Package Description Vendor Part Number

0 R3, R14, R33,

R34, R35, R48, R49 402 Resistor, 49.9 Ω Susumu RR0510R-49R9-D

0 R42, R43, R54,

R85, R86

402 Resistor, 10 kΩ NIC Components NRC04J103TRF

0 R28, R29, R30,

R31, R32

402 Resistor, 5 kΩ NIC Components NRC04F4991TRF

0 R37, R38 402 Resistor, 25 Ω NIC Components NRC04F24R9TRF

0 R39, R45 402 Resistor, 5 Ω NIC Components NRC04J5R1TRF

0 R58, R59 402 Resistor, 100 Ω NIC Components NRC04F1000TRF

0 R60, R61 402 Resistor, 240 Ω NIC Components NRC04J241TRF

0 R8, R9, R17,

R36, R40, R41, R44, R46, R47, R87, R50, R51, R52, R53, R55, R56, R57, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84

402 Resistor, 0 Ω NIC Components NRC04ZOTRF

0 P1, P2, P16, P17 805 Resistor, 0 Ω NIC Components NRC10ZOTRF

0 SW1 EVQ-

Switch, light touch SMD Panasonic P12937SCT-ND 0 T4 Transformer, RF, 0.4 MHz to 800 MHz, SMD case style CD542 Mini-Circuits ADT1-1WT+

0 T5, T6 sm-22 Balun M/A-Com MABA007159-0000

0 U2 SOIC-8 PIC12F629 Microchip Tech PIC12F629-I/SN

0 U6 Crystal Cvhd_956 crystal CVHD_956

0 U10 SOT-223 Regulator ADP3339AKCZ-5.0

0 Z1 16CSP4X4 AD8352

0 U1 16CSP8X8 AD9515

0 P6 8-pin power connector post Wieland Z5.530.0825.0 0 P6 8-pin power connector top Wieland 25.602.2853.0

0.50 BSC

0.20 REF

0.65 TYP

0.60 MAX

0.05 MAX

0.02 NOM

0.30 MIN

Figure 58. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 34 of 36 NOTES

Rev. 0 | Page 35 of 36 NOTES

Rev. 0 | Page 36 of 36 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07099-0-11/07(0)