AD9618AQ

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Go ANALOG Low Distortion, Precision, DEVICES Wide Bandwidth Op Amp AD9618* FEATURES PIN CONFIGURATION Usable Closed-Loop Gain Range: +5/—1 to +100 Low Distortion: —63 dBc (2nd) at 20 MHz Small Signal Bandwidth: 160 MHz (Ay = +10) NC het —a . Large Signal Bandwidth: 150 MHz at 5 V p-p [| Settling Time: 10 ns to 0.1%; 14 ns to 0.02% ~INPUT [2] | 7 | +Vs5, Overdrive and Output Short Circuit Protected | >| Fast Overdrive Recovery +INPUT Gc OUTPUT DC Nonlinearity 5 ppm 114 ws eet |i "

APPLICATIONS

Driving Flash Converters ‘OPTIONAL +V, **OPTIONAL -Vs D/A Current to Voltage Converters Baseband and Video Communications CONNECTIONS. PERFORMANCE INDICATED IN Photodiode, CCD Preamps Seer eA TIONS I BASED ON SUPPLY CON- GENERAL DESCRIPTION ; ; The AD9618J operates over the range of 0 to +70°C and is The AD9618 is a current feedback amplifier which utilizes a available in either an 8-pin plastic mini-DIP or an 8 lead plastic proprietary architecture to produce superior distortion and de small outline package (SOIC). The AD9618A and B versions are precision. It achieves this along with fast settling, very fast slew rated over the industrial temperature range of — 40°C to +85°C. tate, wide bandwidth (both small signal and large signal), and The AD9618S and T versions are rated over the military tem- exceptional signal fidelity. The device achieves —63 dBc 2nd perature range of —55°C to +125°C; and are available processed harmonic distortion at 20 MHz while maintaining 160 MHz to MIL-STD-883B. small signal and 150 MHz large signal bandwidths. These attributes position the AD9618 as an ideal choice for driv- ing flash ADCs and buffering the latest generation of DACs. Optimized for applications requiring gain between +5/—1 to +40, the AD9618 is unity gain stable without external compensation. Additional benefits of the AD9618B and T grades include input offset voltage of 500 .V and temperature coefficient (TC) of 3 wV/°C. These accuracy performance levels make the AD9618 an excellent choice for driving emerging high resolution (12-16 bits), high speed analog to digital converters and flash converters. ‘The AD9618 offers outstanding performance in high fidelity, wide bandwidth applications in instrumentation ranging from network and spectrum analyzers to oscilloscopes, and in military systems such as radar, SIGINT, and ESM systems. The supe- rior slew rate, low overshoot, and fast settling of the AD9618 allow the device to be used in pulse applications such as com- munications receivers and high speed ATE. Most monolithic op amps suffer in these precision pulse applications due to slew rate limiting. *Patent pending. REV.A Information furnished by Analog Devices is believed to be accurate and One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Use, nor for any infringements of patents or other rights of third parties Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 which may result from its use. No license is granted by implication or West Coast Central Atlantic otherwise under any patent or patent rights of Analog Devices. 714/641-9391 214/231-5094 215/643-7790

ABSOLUTE MAXIMUM RATINGS’ Storage Temperature Supply Voltages (+Vg) 0-000 e eevee eee eee ATV AD9I8JNIJR oo eee ee eee 65°C to + 125°C Continuous Output Curren? 2.2... 0 eee eee 70mA AD96I8JNIJR oe cee eee ee es 150°C Operating Temperature Ranges AD9618AQBQISQITQ - oe eee es ITSC {unless otherwise noted, Ay = +10; +V; = +5 V; R- = 1000 0; DC ELECTRICAL CHARACTERISTICS Pic = 1902) Test | AD918JNJR | AD918AQ/SQ | AD9618BQTQ | Parameter | Conditions Temp | Level | Min Typ Max | Min Typ Max | Min Typ Max | Units Input Offset Voltage * 425°C [T =11 405 42.2 | 11 +05 42.2 [0.0 +05 +11 [mV Input Offset Voltage TC® Full [Iv |-4 +3 +25 |-4 +3 +25 | -4 +43 +25 | pvrc Input Bias Current? Inverting +25°C | I 450 +45 450 +45 | -20 0 +20 pA Noninverting +25°C | I | -25 +5 +35 -25 +5 +35 13, +5) +18 pA Input Bias Current TC* Noninverting Full Jv | so +30 +125 | -so +30 +125 | 30 +30 +125 | nave Inverting Full [IV | so +40 +130 -S0 +40 +130 | -50 +40 +130 | nA"C Input Resistance Noninverting +25°C |v 78 75 75 Ka Input Capacitance | Noninverting +259°C | V 1S LS 1S pF Common Mode Input Range® T = Trax - ity +10 +12 +10 +12 +1.0 +12 v T = Twin to +25°C | — 0 +14 415 +14 +15 +14 +15 v Common Mode Rejection Ratio” — | T = Tinax < ii 448 44 48 4 4B 4B T= +25 - sig 48 52 48 52 48 (52 dB T= Trin < Hi 50 54 50. 54 50 54 4B Power Supply Rejection Ratio AV, = =5% Full | I 50 60 50 60 50 60 4B Open Loop Gain To At de +25°C | V 3 3 3 MO Nonlinearity At de +25°C | V 5 5 5 | ppm Output Impedance Atde +25°C | V 0.08 0.08 0.08 in) Output Current (50 2 Load) | T= 425°C 0 Tine | — 1 60 60 60 mA T= Tain - iit 50 50 50 mA (unless otherwise noted, Ay = +10; +Vs = +5 V; Rp = 1kQ; AC ELECTRICAL CHARACTERISTICS Roo = 100 2) Test | AD9618JN/JR | AD9618AQ/SQ | AD9%18BQTQ Parameter Conditions Temp | Level | Min Typ Max | Min Typ Max | Min Typ Max | Units FREQUENCY DOMAIN Bandwidth (—3 dB) Small Signal Vour=2Vpp |Full | I 130 160 130 160 130 160 | MHz Large Signal Vour=5 Vp-p | Full | IV 150 120 150 120 150 MHz Bandwidth Variation vs. Ay Ay = -lto +40 +25°C | V 35 35 35 MHz Amplitude of Peaking (<50 MHz) | T = Tyg to +25°C | — 0 0 0 04 0 04 | dB T = Tix < 1 | 0 0 07 0 07 | dB Amplitude of Peaking (>50 MHz) | T = Tyyin to +25°C | it 0 0 06 0 0.6 | dB T= Tix <- 0 0 | 0 12 0 12° | 4B Amplitude of Roll-Off (<75 MHz) Full | I 0.5 0S 12 05 12 |B Phase Nonlinearity de to 75 MHz +25°C | V 0.5 0.5 0.5 Degree 2nd Harmonic Distortion 2Vp-ps4.3MHz | Full | IV -83. -75 -83 -75 =83 -75 | dBc 2Vp-p;20MHz | Full | IV ~63 —55 -63 -55 -63 -55 | dBc 2Vp-p;60MHz | Full | I —51 —43 -51 -43 -51 -43 | dBc 3rd Harmonic Distortion 2V p-p;4.3 MHz | Full | IV -85 -77 -85 -77 -85 -77 | dBe

2 V p-p; 20 MHz Full Iv —70 —62 -70 ~62 70-62 dBe

2 V p-p; 60 MHz Full IL 62-54 62 -S4 62 -S4 dBe

Input Noise Voltage | 10 MHz +25°C | V 12 1.2 12 aV/\\(Hz) Inverting Input Noise Current 10 MHz +25°C | V 24 24 24 pA/\\ (Hz) -2- REV.A

Test AD9618JN/JR AD9618AQ/SQ AD9618BQ/TQ Parameter Conditions Temp | Level | Min Typ Max | Min Typ Max Min Typ Max | Units Average Equivalent Integrated Input Noise Voltage 0.1 to 200 MHz +25C | V 38 38 38 pV, rms TIME DOMAIN Slew Rate Vour = 4 V Step Full Iv 1800 1400 1800 1400 1800 Vins Rise/Fall Time Vour = 2 V Step Full Iv 2.2 2.2 26 2.2 26 ns Vour = 5 V Step T = +25°C to < IV 23 23° 2.8 23°28 | ns T = Tonia - 1V 23 23031 23 3.1 | ns Overshoot Vour =2V Step | Full | IV 2 2 10 2 10 % Settling Time To 0.1% Vour=2VStep |Full [IV | 9 9 15 9 18 ns To 0.02% Vour = 2 V Step Full Vv 4 14 23 14 23 ns To 0.1% Vour=4V Step | Full | IV 10 10 16 10 16 | ns To 0.02% Vour = 4 V Step Full Iv 16 16 24 16 24 ns 2*Overdrive Recovery to | | +2 mV of Final Value Vin = 0.6 V Step. +25C | V 50 50 50 ns Propagation Delay +25°C | V 2 2 2 ns Differential Gain* Full v 0.01 0.01 0.01 % Differential Phase* Full Vv 0.02 0.02 0.02 Degree POWER SUPPLY REQUIREMENTS Quiescent Current +Iy Full I 31 43 31 43 31 4B mA aly Full | 0 3143 | 3 8 | 31 430 | mA NOTES ‘Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. *Output is short circuit protected to ground, but not to supplies. Continuous short circuit to ground may affect device reliability. *Typical thermal impedances (part soldered onto board): Mini-DIP: 8,, = 140°C/W; 6) = 30°C/W. Side Brazed/Cerdip: 6;, = 110°C/W; 4. = 20°C/W. *Measured with respect to the inverting input. Typical is defined as the mean of the distribution. Measured in voltage follower configuration. ?Measured with Vij = 0.25 V. *Frequency = 4.3 MHz; Ry = 150; Ay = +10. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS ORDERING GUIDE Test Level I — 100% production tested. Temperature Package IL ~ 100% production tested at +25°C and sample tested at Model Range Description | Option specified temperatures. AC testing of J grade devices done AD9618JN 0 to +70°C Plastic DIP N-8 on sample basis. AD9618JR_| 0 to +70°C SOIC R8 III — Sample tested only. aDoeisee aie to er Gerdip Q8 . . oo D9618Bi —40°C to +85 Cerdip Q8 IV ruameter is guaranteed by design and characterization AD9613SQ 55°C to +125°C Cerdip Qs — . AD9618TQ | —55°C to +125°C_| Cerdip Q8 V_ - Parameter is a typical value only. 3. ——— VI ~ All devices are 100% production tested at +25°C. 100% DIE CONNECTIONS production tested at temperature extremes for extended ey. temperature devices; sample tested at temperature ° extremes for commercial/industrial devices. oOo oO <ipur |[-] Oj roe view orto Sete) neor [] oureur oO 0 0 vo Ms OIE Size = 53 « 67 x 15 mis REV. A -3-

THEORY OF OPERATION resistance (buffered) input and a low inverting (buffer output) The AD9618 has been designed to combine the key attributes of __input resistance. The feedback mechanics can be easily devel- traditional “low frequency” precision amplifiers with exceptional _oped using current feedback and transresistance open loop gain high frequency characteristics that are independent of closed- ‘T(s) to describe the I/O relationship. (See typical specification loop gain. Previous “high frequency” closed-loop amplifiers have chart.) low open loop gain relative to precision amplifiers. This results DC closed-loop gain for the AD9618 can be calculated using the in relatively poor de nonlinearity and precision, as well as exces fojfowing equations: sive high frequency distortion due to open loop gain roll-off. V RoR ~ Rei . . a Operational amplifiers use two basic types of feedback correc- G= v, “] LG inverting a tion, each with advantages and disadvantages. Voltage feedback 1 topologies exhibit an essentially constant gain bandwidth prod- uct. This forces the closed-loop bandwidth to vary inversely g - vo . 1+ RR noninverting 2) with closed-loop gain. Moreover, this type design typically slew Vy 1+ LG rate limits in a way that causes the large signal bandwidth to be much lower than its small signal characteristics. where: 2. ~ RstRe + RsiRr) 8) A newer approach is to use current feedback to realize better LG TSKRSIR) 7 dynamic performance. This architecture provides two key Because the noninverting input buffer is not ideal, input resis- attributes over voltage feedback configurations: (1) avoids slew tance Rg (at de) is gain dependent and is typically higher for rate limiting and therefore large signal bandwidth can approach -—-‘0ninverting operation than for inverting operation. Ry will ap- small signal performance; and (2) low bandwidth variation ver- proach the same value (~9 2) for both at input frequencies sus gain settings, due to the inherently low open loop inverting _-—-tbove 50 MHz. Below the open loop corner frequency, the non- input resistance (R.). inverting Rg can be approximated as: The AD9618 uses a new current feedback topology that over- Rg noninverting ~9 + TL = 9 4 Te @) comes these limitations and combines the positive attributes of Ao Ao| both current feedback and voltage feedback designs. These de devices achieve excellent high frequency dynamics (slew, BW where: Ag=Open Loop Voltage Gain ~ Gx350 and distortion) along with excellent low frequency linearity and Jyverting Rg below the open loop comer frequency can be ap- good de precision. proximated 2s: DC GAIN CHARACTERISTICS Tis) To A simplified equivalent schematic is shown below. When operat- Rs inverting) ~ 9 + = 9 + 5° ©) ing the device in the inverting mode, the input signal error cur- ° Ol a rent (I) is amplified by the open loop transimpedance gain here: Ap = 140,000 (To). The output signal generated is equal to Ty x Ip. Nega- where: Ao = 140,00 tive feedback is applied through Ry. such that the device oper- ates at a gain (G) equal to —R,/R,. [| TT ti] Noninverting operation is similar, with the input signal applied [| | to the high impedance buffer (noninverting) input. As before, : on Bl | INE I al | LN “uO 58 gs 5 Cs ltt ov. VA Le] S * Litt ty | yt | vO 6 2 = ° Fs) 72 Equivalent Circuit DC Nonlinearity vs. Vour an output (buffer) error current (I;) is generated at the low im- The AD9618 approaches this condition. With To = 3 x 10°. 0 pedance inverting input. The signal generated at the output is and Rs = 32 91 (dc), a gain error of 0.04% typically results for fed back to the inverting input such that the external gain is G = —1 and 0.11% for G = —100. Moreover, the architecture (1+ Rp/R,). The feedback mechanics are identical to the voltage _linearizes the open loop gain over its operating voltage range and feedback topology when exact equations are used. temperature resulting in >16 bits of linearity. ‘The major difference lies in the front end architecture. A voltage feedback amplifier has symmetrical high resistance (buffered) inputs. A current feedback amplifier has a high noninverting 4. REV.A

AC GAIN CHARACTERISTICS Re = 1100 + 8G (8) Closed-loop bandwidth at high frequencies is determined prima- (+ for inverting and ~ for noninverting) rily by the roll-off of T(s). But circuit layout is critical to mini- . mize external parasitics which can degrade performance by R, ~ UO 1G (noninverting) (9) causing premature peaking and/or reduced bandwidth. G-1 The inverting and noninverting dynamic characteristics are simi- R, ~ 100+ 1G inverting) (10) lar. When driving the noninverting input, the inverting input G capacitance (C,) will cause the noninverting closed-loop band- G = Closed-Loop Gain. width to be higher than the inverting bandwidth for gains less . . than five (5). In the remaining cases, inverting and noninverting Bandwidth Reduction ae responses are nearly identical. ‘The closed-loop bandwidth can be reduced by increasing Ry. Equations 6 and 7 can be used to determine the closed-loop For best overall dynamic performance, the value of the feedback handwidth for any value Rp. Do not connect a feedback capaci- resistor (Rr) should be 1000 @. Although bandwidth reduces a8 tor across Ry, as this will degrade dynamic performance and closed-loop gain increases, the change is relatively small due to possibly induce oscillation. low equivalent series input impedance, Z. (See typical perfor- _ . mance charts.) The simplified equations governing the device’s. DC Precision and Noise ae dynamic performance are shown below. Output offset voltage results from both input bias currents and _ . . input offset voltage. These input errors are multiplied by the Closed-Loop Gain vs. Frequency: noise gain term (1 + Ry/R;) and algebraically summed at the (noninverting operation) output as shown below. 14 Re Vo Rr Vo=Viox (1+8*) «1m Ry» (1428) 1x Rp ap yo Re 6) Rr Ry ‘ 14)e1 7 ( zi) Since the inputs are asymmetrical, IBi and IBn do not correlate. Canceling their output effects by making Ry = Rpl|R, will not where: 7=RpXCo=1.0 ns (Re=1 RO) reduce output offset errors, as it would for voltage feedback am- sn Rap ~ Ve oRoKCe R Slew Rate ~ Re ¥ € 7) here: Ka 28 R, where: = *R Increasing Bandwidth at Low Gains Va Pail Vour By reducing R,-, wider bandwidth and faster pulse response can be attained beyond the specified values, although increased over- V shoot, settling time, and possible ac peaking may result. As a Output Offset Voltage rule of thumb, overshoot and bandwidth will increase by 1% and 8%, respectively, for a 5% reduction in Ry: at gains of +10. +10 +10 the second order (open loop) frequency response term which is “ ——— sd sos the primary contributor to overshoot, peaking, and nonlinear | <7 bandwidth expansion. (See Open Loop Bode Plots.) The user 4 ana should exercise caution when selecting Rj values much lower eo 4 ° a than 1000 2, Note that a feedback resistor must be used in all g | 3 situations. ~ Increasing Bandwidth at High Gains “5 -05 Closed-loop bandwidth can be extended at high closed-loop gain by reducing R,-. Bandwidth reduction is a result of the feedback current being split between Rg and R,. As the gain increases =10 10 (for a given R,-), more feedback current is shunted through R,, ~ 55°C 425°C +1250 which reduces closed-loop bandwidth (see Equation 6). To DC Accuracy maintain specified BW, the following equations can be used to approximate R,. and R, for any gain from = +5/~1 to +40. plifiers. Typically, IBn is 5 pA and Vio is +0.5 mV (1 sigma = 0.3 mV), which means that the de output error can be reduced by making Ry ~ 100 ©. Note that the offset drift will not change significantly because the IBn TC is relatively small. (See specification table.) -5-

The effective noise at the output of the amplifier can be deter- Typical circuits for inverting and noninverting applications are mined by taking the root sum of the squares of Equation 11 and shown in Figures | and 2. applying the spectral noise values found in the typical graph sec- —__Cosed-loop gain for noninverting configurations is determined tion. This applies to noise from the op amp only. Note that by the value of R, according to the equation: both the noise figure and equivalent input offset voltage improve R as the closed-loop gain is increased (by keeping Re, fixed and G-14 a2) reducing R, with Ry = 09). Rr y ve 1k ) 33pF 9 3.3nF one oF Omar our 'n cu Recnies f oar ork i : t R Va Oe) Ola) 5000, ct Ps 09618 YE)—p—0 Vous anset8 YS)—y—ov ages Vv _ dim, Xow : Vn i 8 ese Capacitive Load Figure ~ “+4 r- ® + Al F- erie L i L 4 Capacitive Load Considerations Ou On Due to the low inverting input resistance (Rg) and output buffer jo 22uF design, the AD9618 can directly handle input and/or output Ne Ve load capacitances of up to 10 pF. See the chart below. “See pINOUTS “see PINOUTS 26 9 7 Figure 1. Noninverting Figure 2. Inverting ' | | 7 ] Operation Operation 55 f} Vour = 4V STEP 3 aoe fuser | , he amplifier’ fll bandwidth th ; o 45 ‘o preserve the amplifier’s andwidth, the noninverting e,f IAT) LET fT input should be driven from a low impedance source. Be | Aoreavsrer FL) AY A recommended circuit for an inverting amplification is shown g ( GL = OpF Wy in Figure 2. 2 4 | | gue ae ws apF/DIV—_25pOpF 4pF/DIV 20pF Closed-loop gain for inverting configurations is determined by ° INPUT CAPACITANCE (CLI) CAPACITIVE LOAD (cL) the value of R, per the following equation: Recmes = 08 . Rr ; - G=-— (13) Input/Output Capacitance Comparisons R; A small series resistor can be used at the output of the amplifier and outside of the feedback loop to facilitate driving larger Kayour CONSIDERATIONS liffers, printed circuit | capacitive loads or for obtaining faster settling time. For capaci- § with al) high performance amplifiers, printed circuit layout 1s ; critical in obtaining optimum results with the AD9618. The tive loads above 10 pF, Rsxres should be considered. : : SERIES ground plane in the area of the amplifier should cover as much bad ea of the component side of the board as possible. Each power 0 | supply trace should be decoupled close to the package with at ° lA least a 3.3 4.F tantalum and a low inductance, 0.1 4F ceramic 5 18 A capacitor. , 1 Vi Alll lead lengths for input, output, and the feedback resistor #10 should be kept as short as possible. All gain setting resistors é Taaae should be chosen for low values of parasitic capacitance and in- 5 ductance, i.e., microwave resistors and/or carbon resistors. Vi | | i | Stripline techniques should be used for lead lengths in excess of re ae ee one inch. Sockets should be avoided if possible because of their CL - pF stray inductance and capacitance. If sockets are necessary, indi- Recommended Rsepies VS. CL vidual pin sockets such as AMP p/n 6-330808-3 should be used. These contribute far less stray reactance than molded socket as- APPLYING THE AD9618 semblies. The superior frequency and time domain specifications of the . oo . AD9618 make it an obvious choice for driving flash converters An evaluation board is available from Analog Devices for a and buffering the outputs of high speed DACs. Its outstanding nominal charge. distortion and noise performance make it well suited as a driver for analog-to-digital converters (ADCs) with resolutions as high as 16 bits.

Typical Performance 1s, = +10; +v, = +5v; R, = 1 0, unless otherwise noted) CORSO PRS SX PESSANo HESS ON i-3 R, 90 1 rm “t * * { + 160 5 i] iy i Open Loop Transimpedance Gain Noninverting Frequency Response Inverting Frequency Response [Ts) Relative to 10] . PLEA A Pip i : K oe 2 oe | a “OA os ee ee CMRR and PSRR Settling Time Long Term Settling Time . Vour = 2¥ ee a +10 * . 41 a ~ a . ||, ] go SRZAN .« 2 * 7 ‘ FREQUENCY — MHz FREQUENCY - Mitr * weavtner Me Harmonic Distortion Frequency Response vs. R,oap Equivalent Input Noise ° | “OO AEE ALT) Cl. We. ._lJ ite) SASS CAE | Test ry | +08 rtN Bh Oy i. j g | i aii 7 ce 7 test oncur NS UGE CUAL Intermodulation Distortion (IMD) Large Signal Pulse Response Small Signal Pulse Response REV.A -7-

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