AD9613BCPZ-210

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Technical content

12-Bit, 170 MSPS/210 MSPS/250 MSPS,

1.8 V Dual Analog-to-Digital Converter (ADC)

Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS SFDR = 86 dBc at 185 MHz fIN and 250 MSPS −149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and

250 MSPS

Total power consumption: 770 mW at 250 MSPS

1.8 V supply voltages

LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Sample rates of up to 250 MSPS IF sampling frequencies of up to 400 MHz Internal ADC voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control Energy-saving power-down modes

APPLICATIONS

Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, L TE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION The AD9613 is a dual 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9613 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user- selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The ADC output data is routed directly to the two external 12-bit LVDS output ports and formatted as either interleaved or channel multiplexed. Flexible power-down options allow significant power savings, when desired. FUNCTIONAL BLOCK DIAGRAM REFERENCE SERIAL PORT SCLK SDIO CSB CLK+ CLK– SYNC

1 TO 8

VIN+A D0± D11± DCO± OR± PDWN OEB VIN–A VIN+B VCM VIN–B NOTES 1. THE D0± TO D11± PINS REPRESENT BOTH THE CHANNEL A AND CHANNEL B LVDS OUTPUT DATA. AVDD AGND DRVDD 09637-001 PARALLEL DDR LVDS AND DRIVERS PIPELINE 12-BIT ADC PIPELINE 12-BIT ADC Figure 1. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9613 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs. 2. Fast overrange and threshold detect. 3. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. 4. SYNC input allows synchronization of multiple devices. 5. 3-pin, 1.8 V SPI port for register programming and register readback. 6. Pin compatibility with the AD9643, allowing a simple migration up to 14 bits, and with the AD6649 and the AD6643.

Rev. C | Page 2 of 36 TABLE OF CONTENTS

REVISION HISTORY

1/13—Rev. B to Rev. C 9/11—Rev. A to Rev. B Changes Output Offset Voltage (VOS), ANSI Mode Typ Parameter and Output Offset Voltage (VOS), Reduced Swing Changes to Output Enable Bar and Power-Down Pin Type Changes to Pin 42 and Pin 43, Output Enable Bar and Power- Changes to Typical Performance Characteristics Conditions .. 16 Changes to Reading the Memory Map Register Table 5/11—Rev. 0 to Rev. A Changes to Table 2, AD9613-170: Worst Second or Third Harmonic and Worst Other (Harmonic or Spur) Max Values 4/11—Revision 0: Initial Version

Rev. C | Page 3 of 36 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V , DRVDD = 1.8 V , maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range, DCS enabled, unless otherwise noted. Table 1. AD9613-170 AD9613-210 AD9613-250 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±10 ±10 ±10 mV Gain Error Full +2/−6 +3/−5 ±4 %FSR Differential Nonlinearity (DNL) Full ±0.5 ±0.5 ±0.5 LSB Integral Nonlinearity (INL)1 Full ±0.5 ±0.6 ±0.8 LSB MATCHING CHARACTERISTIC Offset Error Full ±13 ±13 ±13 mV Gain Error Full ±2.5 +3.5/−2 +3.5/−2.5 %FSR TEMPERATURE DRIFT Offset Error Full ±5 ±5 ±5 ppm/°C Gain Error Full ±70 ±80 ±100 ppm/°C INPUT-REFERRED NOISE VREF = 1.75 V 25°C 0.39 0.39 0.39 LSB rms ANALOG INPUT Input Span Full 1.75 1.75 1.75 V p-p Input Capacitance2 Full 2.5 2.5 2.5 pF Input Resistance3 Full 20 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 0.9 V POWER SUPPLIES Supply Voltage Supply Current IAVDD1 Full 230 250 241 265 252 275 mA IDRVDD1 Full 142 160 159 185 176 210 mA POWER CONSUMPTION Sine Wave Input1 (DRVDD = 1.8 V) Full 670 738 720 810 770 873 mW Standby Power4 Full 90 90 90 mW Power-Down Power Full 10 10 10 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a dc input and the CLK± pin inactive (that is, set to AVDD or AGND).

Rev. C | Page 4 of 36 ADC AC SPECIFICATIONS AVDD = 1.8 V , DRVDD = 1.8 V , maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range, unless otherwise noted. Table 2. AD9613-170 AD9613-210 AD9613-250 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) fIN = 30 MHz 25°C 70.1 70.1 70.0 dBFS fIN = 90 MHz 25°C 70.0 70.0 69.8 dBFS Full 69.3 69.2 dBFS fIN = 140 MHz 25°C 69.8 69.8 69.6 dBFS fIN = 185 MHz 25°C 69.5 69.5 69.2 dBFS Full 67.8 dBFS fIN = 220 MHz 25°C 69.4 69.3 69.0 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 30 MHz 25°C 69.1 69.1 69.0 dBFS fIN = 90 MHz 25°C 69.0 69.0 68.8 dBFS Full 68.2 68 dBFS fIN = 140 MHz 25°C 68.8 68.8 68.6 dBFS fIN = 185 MHz 25°C 68.5 68.5 68.2 dBFS Full 66.5 dBFS fIN = 220 MHz 25°C 68.4 68.3 68.0 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz 25°C 11.2 11.2 11.2 Bits fIN = 90 MHz 25°C 11.2 11.2 11.1 Bits fIN = 140 MHz 25°C 11.1 11.1 11.1 Bits fIN = 185 MHz 25°C 11.1 11.1 11.0 Bits fIN = 220 MHz 25°C 11.1 11.0 11.0 Bits WORST SECOND OR THIRD HARMONIC fIN = 30 MHz 25°C −94 −94 −90 dBc fIN = 90 MHz 25°C −92 −94 −89 dBc Full −78 −80 dBc fIN = 140 MHz 25°C −87 −88 −86 dBc fIN = 185 MHz 25°C −89 −83 −86 dBc Full −80 dBc fIN = 220 MHz 25°C −80 −83 −85 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz 25°C 94 90 92 dBc fIN = 90 MHz 25°C 92 90 89 dBc Full 78 80 dBc fIN = 140 MHz 25°C 87 88 86 dBc fIN = 185 MHz 25°C 89 83 86 dBc Full 80 dBc fIN = 220 MHz 25°C 83 83 85 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 30 MHz 25°C −97 −95 −93 dBc fIN = 90 MHz 25°C −96 −95 −92 dBc Full −78 −80 dBc fIN = 140 MHz 25°C −97 −97 −91 dBc fIN = 185 MHz 25°C −91 −96 −91 dBc Full −80 dBc fIN = 220 MHz 25°C −93 −94 −89 dBc

Rev. C | Page 5 of 36 AD9613-170 AD9613-210 AD9613-250 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit TWO-TONE SFDR fIN = 184.12 MHz (−7 dBFS),

187.12 MHz (−7 dBFS)

25°C 88 88 88 dBc CROSSTALK2 Full 95 95 95 dB FULL POWER BANDWIDTH3 25°C 1000 1000 1000 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. 3 Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved.

Rev. C | Page 6 of 36 DIGITAL SPECIFICATIONS AVDD = 1.8 V , DRVDD = 1.8 V , maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 3. Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full 10 22 µA Low Level Input Current Full −22 −10 µA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −5 +5 µA Low Level Input Current Full −5 +5 µA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ LOGIC INPUT (CSB)1 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −5 +5 µA Low Level Input Current Full −80 +45 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT (SCLK)2 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 µA Low Level Input Current Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (SDIO)2 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 µA Low Level Input Current Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

Rev. C | Page 7 of 36 Parameter Temp Min Typ Max Unit LOGIC INPUTS (OEB, PDWN)2 High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 µA Low Level Input Current Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS LVDS Data and OR Outputs Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.22 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.22 1.35 V 1 Pull up. 2 Pull down.

Rev. C | Page 8 of 36 SWITCHING SPECIFICATIONS Table 4. AD9613-170 AD9613-210 AD9613-250 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz Conversion Rate1 Full 40 170 40 210 40 250 MSPS CLK Period, Divide-by-1 Mode (tCLK) Full 5.8 4.8 4 ns CLK Pulse Width High (tCH) Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 0.8 0.8 ns Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms DATA OUTPUT PARAMETERS LVDS Mode Data Propagation Delay (tPD) Full 6.0 6.0 6.0 ns DCO Propagation Delay (tDCO) Full 6.7 6.7 6.7 ns Pipeline Delay (Latency) Full 10 10 10 Cycles Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms Wake-Up Time (from Standby) Full 10 10 10 µs Wake-Up Time (from Power Down) Full 250 250 250 µs Out-of-Range Recovery Time Full 3 3 3 Cycles 1 Conversion rate is the clock rate after the divider.

Rev. C | Page 9 of 36 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SYNC TIMING REQUIREMENTS See Figure 3 for timing details tSSYNC SYNC to the rising edge of CLK setup time 0.3 ns tHSYNC SYNC to the rising edge of CLK hold time 0.4 ns SPI TIMING REQUIREMENTS See Figure 58 for SPI timing diagram tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK should be in a logic high state 10 ns tLOW Minimum period that SCLK should be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 58) 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 58) 10 ns

solder joints, maximizing the thermal capability of the package. power planes reduces the θJA. Table 7. Thermal Resistance 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air).

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE

MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 4. Pin Configuration (Top View) for the LFCSP Interleaved Parallel LVDS Mode Table 8. Pin Function Descriptions for the LFCSP Interleaved Parallel LVDS Mode

0 AGND,

must be connected to ground for proper operation. 4 to 9, 11, 12, 55, 56, 58 DNC Do not connect. Do not connect to these pins. 10, 19, 28, 37 DRVDD Supply Digital O utput Driver Supply (1.8 V Nominal). 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. be decoupled to ground using a 0.1 μF capacitor. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 3 SYNC Input Digital Synchronization Pin. Slave mode only.

Rev. C | Page 13 of 36 Pin No. Mnemonic Type Description Digital Outputs 14 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 13 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 16 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 15 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 18 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 17 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 21 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 20 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 23 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 22 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 27 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 26 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 30 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 29 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 32 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 31 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 34 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 33 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 36 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 35 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 39 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 38 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 41 D11+ (MSB) Output Channel A/Channel B LVDS Output Data 11—True. 40 D11− (MSB) Output Channel A/Channel B LVDS Output Data 11—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange—True. 42 OR− Output Channel A/Channel B LVDS Overrange—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK Input SPI Serial Clock. 44 SDIO Input/Output SPI Serial Data I/O. 46 CSB Input SPI Chip Select (Active Low). Output Enable Bar and Power-Down 47 OEB Input/Output Output Enable Bar Input (Active Low). 48 PDWN Input/Output Power-Down Input (Active High). Operation depends upon SPI mode; this input can be configured as power-down or standby. For further description, refer to Table 14.

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE

GROUND FOR PROPER OPERATION. Figure 5. Pin Configuration (Top View) for the LFCSP Channel Multiplexed (Even/Odd) LVDS Mode Table 9. Pin Function Descriptions for the LFCSP Channel Multiplexed (Even/Odd) LVDS Mode 10, 19, 28, 37 DRVDD Supply Digital O utput Driver Supply (1.8 V Nominal). 4 to 9, 26, 27, 55, 56, 58 DNC Do Not Connect. Do not connect to these pins.

0 AGND, Exposed

to ground for proper operation. 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. 3 SYNC Input Digital Synchronization Pin. Slave mode only. valid on the rising edge of the DCO. indication is valid on the rising edge of the DCO.

Rev. C | Page 15 of 36 Pin No. Mnemonic Type Description 11 B D0−/D1− (LSB) Output Channel B LVDS Output Data 1/Data 0—Complement. 12 B D0+/D1+ (LSB) Output Channel B LVDS Output Data 1/Data 0—True. 13 B D2−/D3− Output Channel B LVDS Output Data 3/Data 2—Complement. 14 B D2+/D3+ Output Channel B LVDS Output Data 3/Data 2—True. 15 B D4−/D5− Output Channel B LVDS Output Data 5/Data 4—Complement. 16 B D4+/D5+ Output Channel B LVDS Output Data 5/Data 4—True. 17 B D6−/D7− Output Channel B LVDS Output Data 7/Data 6—Complement. 18 B D6+/D7+ Output Channel B LVDS Output Data 7/Data 6—True. 20 B D8−/D9− Output Channel B LVDS Output Data 9/Data 8—Complement. 21 B D8+/D9+ Output Channel B LVDS Output Data 9/Data 8—True. 22 B D10−/D11− Output Channel B LVDS Output Data 11/Data 10—Complement. 23 B D10+/D11+ Output Channel B LVDS Output Data 11/Data 10—True. 29 A D0−/D1− (LSB) Output Channel A LVDS Output Data 1/Data 0—Complement. 30 A D0+/D1+ (LSB) Output Channel A LVDS Output Data 1/Data 0—True. 31 A D2−/D3− Output Channel A LVDS Output Data 3/Data 2—Complement. 32 A D2+/D3+ Output Channel A LVDS Output Data 3/Data 2—True. 33 A D4−/D5− Output Channel A LVDS Output Data 5/Data 4—Complement. 34 A D4+/D5+ Output Channel A LVDS Output Data 5/Data 4—True. 35 A D6−/D7− Output Channel A LVDS Output Data 7/Data 6—Complement. 36 A D6+/D7+ Output Channel A LVDS Output Data 7/Data 6—True. 38 A D8−/D9− Output Channel A LVDS Output Data 9/Data 8—Complement. 39 A D8+/D9+ Output Channel A LVDS Output Data 9/Data 8—True. 40 A D10−/D11− Output Channel A LVDS Output Data 11/Data 10—Complement. 41 A D10+/D11+ Output Channel A LVDS Output Data 11/Data 10—True. 43 ORA+ Output Channel A LVDS Overrange Output—True. The overrange indication is valid on the rising edge of the DCO. 42 ORA− Output Channel A LVDS Overrange Output—Complement. The overrange indication is valid on the rising edge of the DCO. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK Input SPI Serial Clock. 44 SDIO Input/Output SPI Serial Data I/O. 46 CSB Input SPI Chip Select (Active Low). Output Enable Bar and Power-Down 47 OEB Input Output Enable Bar Input (Active Low). 48 PDWN Input Power-Down Input (Active High). Operation depends upon SPI mode; this input can be configured as power-down or standby. For further description, refer to Table 14.

output port(s) as a filtered, and optionally, decimated digital signal. filtering at the ADC inputs with little loss in ADC performance. the expense of increased ADC noise and distortion. timing between multiple devices. using a 3-pin, SPI-compatible serial interface. samples. Sampling occurs on the rising edge of the clock. buffers go into a high impedance state. processing a differential input signal. mode and hold mode (see the configuration shown in Figure 46). the precise values are dependent on the application. for more information on this subject. Figure 46. Switched-Capacitor Input The analog inputs of the AD9613 are not internally dc biased. inductance between the part and this capacitor.

Performance Characteristics section. Figure 57. AD9613-250 Power and Current vs. Sample Rate the PDWN pin high), the AD9613 is placed in power-down mode. down, the output drivers are placed in a high impedance state. cycles result in proportionally shorter wake-up times. Interfacing to High Speed ADCs via SPI, for additional details. LVDS or reduced drive LVDS using a 1.8 V DRVDD supply. should not exceed that supply voltage. delay (tPD) after the rising edge of the clock signal. transients can degrade converter dynamic performance. clock rates below 40 MSPS, dynamic performance can degrade. diagram of the AD9613 output modes. indicated by this bit 10 clock cycles after it. Table 11. Output Data Format

Rev. C | Page 28 of 36 CHANNEL/CHIP SYNCHRONIZATION The AD9613 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The sync feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider can be synchronized using the SYNC input. The divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence by setting the appropriate bits in Register 0x3A. The SYNC input is internally synchronized to the sample clock. However, to ensure that there is no timing uncertainty between multiple parts, the SYNC input signal should be synchronized to the input clock signal. The SYNC input should be driven using a single-ended CMOS type signal.

flexibility and customization, depending on the application. active-low control that enables or disables the read and write cycles. Table 12. Serial Port Interface Pins synchronize serial interface reads and writes. turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. change direction from an input to an output. at the appropriate point in the serial frame. Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. at the converter inputs during critical sampling periods.

Memory Map Register Description section. Table 13. Features Accessible Using the SPI Figure 58. Serial Port Interface Timing Diagram

Rev. C | Page 31 of 36 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF); and the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x3A). The memory map register table (see Table 14) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x14, the output mode register, has a hexadecimal default value of 0x05. This means that Bit 0 = 1 and Bit 2 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0x20. The remaining register, Register 0x3A, is documented in the Memory Map Register Description section. Open and Reserved Locations All address and bit locations that are not included in Table 14 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD9613 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 14). Logic Levels An explanation of logic level terminology follows:

• “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.”
• “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Transfer Register Map Address 0x08 to Address 0x20 and Address 0x3A are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF , setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set and the bit autoclears. Channel Specific Registers Some channel setup functions, such as the signal monitor thresholds, can be programmed to a different value for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 14 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 14 affect the entire part and the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits.

All address and bit locations that are not included in Table 14 are not currently supported for this device. Table 14. Memory Map Registers

0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles

Rev. C | Page 33 of 36 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0x0D Test mode (local) User test mode control 0 = continuou s/repeat pattern 1 = single pattern, then 0s Open Reset PN long gen Reset PN short gen Output test mode 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN long sequence 0110 = PN short sequence 0111 = one/zero word toggle 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output 0x00 When this register is set, the test data is placed on the output pins in place of normal data 0x10 Offset adjust (local) Open Open Offset adjust in LSBs from +31 to −32 (twos complement format) 0x00 0x14 Output mode Open Open Open Output enable bar (local) Open Output invert (local) 1 = normal (default) 0 = inverted Output format 00 = offset binary 01 = twos complement (default) 10 = gray code 11 = reserved (local) 0x05 Configures the outputs and the format of the data 0x15 Output Adjust (Global) Open Open Open Open LVDS output drive current adjust 0000 = 3.72 mA output drive current 0001 = 3.5 mA output drive current (default) 0010 = 3.30 mA output drive current 0011 = 2.96 mA output drive current 0100 = 2.82 mA output drive current 0101 = 2.57 mA output drive current 0110 = 2.27 mA output drive current 0111 = 2.0 mA output drive current (reduced range) 1000 – 1111 = reserved 0x01 0x16 Clock phase control (global) Invert DCO clock Open Odd/Even Mode Output Enable 0 = disabled 1 = enabled Open Open Open Open Open 0x00 0x17 DCO output delay (global) Enable DCO clock delay Open Open DCO clock delay [delay = (3100 ps × register value/31 +100)] 00000 = 100 ps 00001 = 200 ps 00010 = 300 ps 11110 = 3100 ps 11111 = 3200 ps 0x00 0x18 Input span select (global) Open Open Open Full-scale input voltage selection 01111 = 2.087 V p-p 00001 = 1.772 V p-p 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p 10000 = 1.383 V p-p 0x00 Full-scale input adjustment in 0.022 V steps 0x19 User Test Pattern 1 LSB (global) User Test Pattern 1[7:0] 0x00 0x1A User Test Pattern 1 MSB (global) User Test Pattern 1[15:8] 0x00 0x1B User Test Pattern 2 LSB (global) User Test Pattern 2[7:0] 0x00 0x1C User Test Pattern 2 MSB (global) User Test Pattern 2[15:8] 0x00 0x1D User Test Pattern 3 LSB (global) User Test Pattern 3[7:0] 0x00

Rev. C | Page 34 of 36 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0x1E User Test Pattern 3 MSB (global) User Test Pattern 3[15:8] 0x00 0x1F User Test Pattern 4 LSB (global) User Test Pattern 4[7:0] 0x00 0x3A Sync control (global) Open Open Open Open Open Clock divider next sync only Clock divider sync enable Master sync buffer enable 0x00 1 The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00. MEMORY MAP REGISTER DESCRIPTION For more information on functions controlled in Register 0x00 to Register 0x20, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only If the master sync buffer enable bit (Address 0x3A, Bit 0) and the clock divider sync enable bit (Address 0x3A, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse that it receives and to ignore the rest. The clock divider sync enable bit (Address 0x3A, Bit 1) resets after it syncs. Bit 1—Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high and Bit 0 is high. This is continuous sync mode. Bit 0—Master Sync Buffer Enable Bit 0 must be set high to enable any of the sync functions. If the sync capability is not used, this bit should remain low to conserve power.

Rev. C | Page 35 of 36 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting system-level design and layout of the AD9613, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9613, it is recommended that two separate 1.8 V supplies be used: one supply should be used for analog (AVDD), and a separate supply should be used for the digital outputs (DRVDD). The designer can employ several different decoupling capacitors to cover both high and low frequencies. These capacitors should be located close to the point of entry at the PC board level and close to the pins of the part with minimal trace length. A single PCB ground plane should be sufficient when using the AD9613. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD9613 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. See the evaluation board for a PCB layout example. For detailed information about the packaging and PCB layout of chip-scale packages, refer to the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). VCM The VCM pin should be decoupled to ground with a 0.1 µF capacitor, as shown in Figure 48. For optimal channel-to-channel isolation, a 33 Ω resistor should be included between the AD9613 VCM pin and the Channel A analog input network connection, as well as between the AD9613 VCM pin and the Channel B analog input network connection. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9613 to keep these signals from transitioning at the converter input pins during critical sampling periods.

0.25 MIN

0.20 REF

7.50 REF

0.05 MAX

0.02 NOM

0.60 MAX

Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the property of their respective owners.