AD9608BCPZ-125

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10-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet AD9608 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

1.8 V analog supply operation

1.8 V CMOS or 1.8 V LVDS output SNR = 61.7 dBFS at 70 MHz SFDR = 85 dBc at 70 MHz Low power: 95 mW/channel at 125 MSPS Differential analog input with 650 MHz bandwidth IF sampling frequencies to 200 MHz On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = ±0.13 LSB Serial port control options Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment

APPLICATIONS

Broadband data applications Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound FUNCTIONAL BLOCK DIAGRAM VIN+A VIN–A VREF SENSE VCM RBIAS VIN–B VIN+B ORA D0A D9A DCOA DRVDD ORB D9B D0B DCOB SDIOAGNDAVDD SCLK SPI PROGRAMMING DATAMUX OPTION PDWN DFSCLK+ CLK– MODE CONTROLS DCS DUTY CYCLE STABILIZER SYNC DIVIDE

1 TO 8

1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES. 09977-001 Figure 1. PRODUCT HIGHLIGHTS 1. Operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or 1.8 V LVDS logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. 3. Includes a standard serial port interface that supports various product features and functions, such as data output format- ting, internal clock divider, power-down, DCO/data timing, and offset adjustments. 4. Packaged in a 64-lead, RoHS-compliant LFCSP that is pin compatible with the AD9650, AD9269, and AD9268 16-bit ADCs, the AD9258 and AD9648 14-bit ADCs, the AD9628 and AD9231 12-bit ADCs, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.

AD9608* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS

• AD9608 Evaluation Board DOCUMENTATION Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• AN-737: How ADIsimADC Models an ADC
• AN-742: Frequency Domain Response of Switched- Capacitor ADCs
• AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter
• AN-803: Pin Compatible High Speed ADCs Simplify Design Tasks
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs
• AN-835: Understanding High Speed ADC Testing and Evaluation
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

• AN-935: Designing an ADC Transformer-Coupled Front End Data Sheet
• AD9608: 10-Bit, 125/105 MSPS, 1.8 V Dual Analog-to- Digital Converter (ADC) Data Sheet User Guides
• UG-003: Evaluating the AD9650/AD9268/AD9258/ AD9251/AD9231/AD9204 Analog-to-Digital Converters TOOLS AND SIMULATIONS
• Visual Analog
• AD9608 IBIS Model
• AD9648/AD9628/AD9608 S-Parameters REFERENCE MATERIALS Product Selection Guide
• RF Source Booklet Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC DESIGN RESOURCES
• AD9608 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints DISCUSSIONS View all AD9608 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. C | Page 2 of 40 TABLE OF CONTENTS

REVISION HISTORY

11/15—Rev. B to Rev. C Changed AD9516 to AD9516-0/AD9516-1/AD9516-2/ AD9516-3/AD9516-4/AD9516-5, and AD9517 to AD9517-0/ 8/15—Rev. A to Rev. B Changes to Features Section and Product Highlights Section ... 1 Changes to Aperture Uncertainly (Jitter, tJ) Parameter, Changes to RBIAS Pin Description and OEB Pin Description, Changes to RBIAS Pin Description and OEB Pin Description, Changes to RBIAS Pin Description and OEB Pin Description, Changed Built-In Self-Test (BIST) and Output Test Mode 11/14—Rev. 0 to Rev. A 7/11—Revision 0: Initial Version

Rev. C | Page 3 of 40 GENERAL DESCRIPTION The AD9608 is a monolithic, dual-channel, 1.8 V supply, 10-bit,

105 MSPS/125 MSPS analog-to-digital converter (ADC) that

features a high performance sample-and-hold circuit and an on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at

125 MSPS data rates and to guarantee no missing codes over the

full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Logic levels of 1.8 V CMOS and 1.8 V LVDS are supported. Output data can also be multiplexed onto a single output bus. The AD9608 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).

Rev. C | Page 4 of 40 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V , DRVDD = 1.8 V , maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1. AD9608-105 AD9608-125 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION Full 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Differential Nonlinearity (DNL)1 Full ±0.35 ±0.35 LSB 25°C ±0.12 ±0.13 LSB Integral Nonlinearity (INL)1 Full ±0.40 ±0.40 LSB 25°C ±0.14 ±0.14 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.1 ±1.0 ±0.1 ±1.0 % FSR Gain Error Full ±0.5 ±6.5 ±0.5 ±6.5 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±50 ±50 ppm/°C INTERNAL VOLTAGE REFERENCE Load Regulation Error at 1.0 mA Full 2 2 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.08 0.08 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance2 Full 5 5 pF Input Resistance (Differential) Full 7.5 7.5 kΩ Input Common-Mode Voltage Full 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 V POWER SUPPLIES Supply Voltage Supply Current IAVDD1 Full 76.8 82.0 87.7 93.0 mA IDRVDD1 (1.8 V CMOS) Full 14.7 17.4 mA IDRVDD1 (1.8 V LVDS) Full 48.5 49.7 mA POWER CONSUMPTION DC Input Full 125 141 mW Sine Wave Input1 (DRVDD = 1.8 V CMOS Output Mode) Full 165 174 189 199 mW Sine Wave Input1 (DRVDD = 1.8 V LVDS Output Mode) Full 226 247 mW Standby Power3 Full 108 120 mW Power-Down Power Full 2.0 2.0 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode).

Rev. C | Page 5 of 40 AC SPECIFICATIONS AVDD = 1.8 V , DRVDD = 1.8 V , maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2. AD9608-105 AD9608-125 Parameter1 Temp Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) fIN = 9.7 MHz 25°C 61.7 61.7 dBFS fIN = 30.5 MHz 25°C 61.7 61.7 dBFS fIN = 70 MHz 25°C 61.7 61.7 dBFS Full 61.3 61.3 dBFS fIN = 100 MHz 25°C 61.6 61.6 dBFS fIN = 200 MHz 25°C 61.4 61.4 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 9.7 MHz 25°C 61.6 61.6 dBFS fIN = 30.5 MHz 25°C 61.6 61.6 dBFS fIN = 70 MHz 25°C 61.6 61.6 dBFS Full 61.1 61.1 dBFS fIN = 100 MHz 25°C 61.5 61.5 dBFS fIN = 200 MHz 25°C 61.3 61.3 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 9.9 9.9 Bits fIN = 30.5 MHz 25°C 9.9 9.9 Bits fIN = 70 MHz 25°C 9.9 9.9 Bits fIN = 100 MHz 25°C 9.9 9.9 Bits fIN = 200 MHz 25°C 9.9 9.9 Bits WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −90 −90 dBc fIN = 30.5 MHz 25°C −89 −89 dBc fIN = 70 MHz 25°C −89 −89 dBc Full −75 −75 dBc fIN = 100 MHz 25°C −89 −89 dBc fIN = 200 MHz 25°C −84 −84 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 85 85 dBc fIN = 30.5 MHz 25°C 85 85 dBc fIN = 70 MHz 25°C 85 85 dBc Full 75 75 dBc fIN = 100 MHz 25°C 85 85 dBc fIN = 200 MHz 25°C 84 84 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz 25°C −85 −85 dBc fIN = 30.5 MHz 25°C −85 −85 dBc fIN = 70 MHz 25°C −85 −85 dBc Full −75 −75 dBc fIN = 100 MHz 25°C −85 −85 dBc fIN = 200 MHz 25°C −85 −85 dBc TWO-TONE SFDR fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 25°C 82 82 dBc CROSSTALK2 Full −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

Rev. C | Page 6 of 40 DIGITAL SPECIFICATIONS AVDD = 1.8 V , DRVDD = 1.8 V , maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3. Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND − 0.3 AVDD + 0.2 V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −10 +10 µA Low Level Input Current Full −10 +10 µA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ LOGIC INPUT (CSB)1 High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 40 132 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT (SCLK/DFS/SYNC)2 High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −92 −135 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT/OUTPUT (SDIO/DCS)1 High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 38 128 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF LOGIC INPUTS (OEB, PDWN)2 High Level Input Voltage Full 1.22 DRVDD + 0.2 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 1.8 V) Full −90 −134 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS CMOS Mode—DRVDD = 1.8 V High Level Output Voltage IOH = 50 µA Full 1.79 V IOH = 0.5 mA Full 1.75 V Low Level Output Voltage IOL = 1.6 mA Full 0.2 V IOL = 50 µA Full 0.05 V

Rev. C | Page 7 of 40 Parameter Temp Min Typ Max Unit LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Full 290 345 400 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 160 200 230 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V 1 Pull up. 2 Pull down. SWITCHING SPECIFICATIONS AVDD = 1.8 V , DRVDD = 1.8 V , maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4. AD9608-105 AD9608-125 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 1000 1000 MHz Conversion Rate1 DCS Enabled Full 20 105 20 125 MSPS DCS Disabled Full 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 9.52 8 ns CLK Pulse Width High (tCH) Full 4.76 4 ns Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.137 0.137 ps rms DATA OUTPUT PARAMETERS CMOS Mode CMOS Mode (DRVDD = 1.8 V) LVDS Mode (DRVDD = 1.8 V) Data Propagation Delay (tPD) Full 2.4 2.4 ns DCO Propagation Delay (tDCO)2 Full 4.4 4.4 ns CMOS Mode Pipeline Delay (Latency) Full 16 16 Cycles LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Full 16/16.5 16/16.5 Cycles Wake-Up Time (Power-Down)3 Full 350 350 µs Wake-Up Time (Standby) Full 250 250 ns Out-of-Range Recovery Time Full 2 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see Table 18). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode.

maximizes the thermal capability of the package. Table 7. Thermal Resistance 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air).

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES

CONNECTED TO GROUND FOR PROPER OPERATION. Figure 6. Parallel CMOS Pin Configuration (Top View) Table 8. Pin Function Descriptions (Parallel CMOS Mode) 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). AVDD Supply Analog Power Supply (1.8 V Nominal). NC No Connect. Do not connect to this pin.

0 AGND,

for the part. This exposed pad must be connected to ground for proper operation. 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. Connect to 10 kΩ (1% tolerance) resistor to ground. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement.

Rev. C | Page 12 of 40 Pin No. Mnemonic Type Description Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 32 D0A (LSB) Output Channel A CMOS Output Data. 33 D1A Output Channel A CMOS Output Data. 34 D2A Output Channel A CMOS Output Data. 35 D3A Output Channel A CMOS Output Data. 36 D4A Output Channel A CMOS Output Data. 38 D5A Output Channel A CMOS Output Data. 39 D6A Output Channel A CMOS Output Data. 40 D7A Output Channel A CMOS Output Data. 41 D8A Output Channel A CMOS Output Data. 42 D9A (MSB) Output Channel A CMOS Output Data. 43 ORA Output Channel A Overrange Output. 11 D0B (LSB) Output Channel B CMOS Output Data. 12 D1B Output Channel B CMOS Output Data. 13 D2B Output Channel B CMOS Output Data. 14 D3B Output Channel B CMOS Output Data. 15 D4B Output Channel B CMOS Output Data. 16 D5B Output Channel B CMOS Output Data. 17 D6B Output Channel B CMOS Output Data. 18 D7B Output Channel B CMOS Output Data. 20 D8B Output Channel B CMOS Output Data. 21 D9B (MSB) Output Channel B CMOS Output Data.

22 ORB Output Channel B Overrange Output

24 DCOA Output Channel A Data Clock Output. 23 DCOB Output Channel B Data Clock Output. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES

CONNECTED TO GROUND FOR PROPER OPERATION. Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode) 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). AVDD Supply Analog Power Supply (1.8 V Nominal). NC No Connect. Do not connect to this pin. the part. This exposed pad must be connected to ground for proper operation. 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 58 RBIAS Input/Output External Reference Bias Resistor. Connect to 10 kΩ (1% tolerance) resistor to ground. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. 3 SYNC Input Digital Synchronization Pin. Slave mode only.

Rev. C | Page 14 of 40 Pin No. Mnemonic Type Description Digital Outputs 18 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 17 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 21 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 20 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 23 D2+ Output Channel A/Channel B LVDS Output Data 2 —True. 22 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 27 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 26 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 30 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 29 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 32 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 31 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 34 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 33 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 36 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 35 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 39 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 38 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 41 D9+ (MSB) Output Channel A/Channel B LVDS Output Data 9—True. 40 D9− (MSB) Output Channel A/Channel B LVDS Output Data 9—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange Output—True. 42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES

CONNECTED TO GROUND FOR PROPER OPERATION. Figure 8. Channel Multiplexed LVDS Pin Configuration (Top View) Table 10. Pin Function Descriptions (Channel Multiplexed Parallel LVDS Mode) 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). AVDD Supply Analog Power Supply (1.8 V Nominal). NC No Connect. Do not connect to this pin.

0 AGND, Exposed Pad Ground The exposed thermal pad on the bottom of the package provides the

51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 55 VREF Input/Output Voltage Reference Input/Output. 56 SENSE Input Reference Mode Selection. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. 3 SYNC Input Digital Synchronization Pin. Slave mode only.

Rev. C | Page 16 of 40 Pin No. Mnemonic Type Description Digital Outputs 14 B D1+/D0+ (LSB) Output Channel B LVDS Output Data 1/ Data 0—True. 13 B D1−/D0− (LSB) Output Channel B LVDS Output Data 1/ Data 0—Complement. 16 B D3+/D2+ Output Channel B LVDS Output Data 3/ Data 2—True. 15 B D3−/D2− Output Channel B LVDS Output Data 3/ Data 2—Complement. 18 B D5+/D4+ Output Channel B LVDS Output Data 5/ Data 4—True. 17 B D5−/D4− Output Channel B LVDS Output Data 5/ Data 4—Complement. 21 B D7+/D6+ Output Channel B LVDS Output Data 7/ Data 6—True. 20 B D7−/D6− Output Channel B LVDS Output Data 7/ Data 6—Complement. 23 B D9+/D8+ (MSB) Output Channel B LVDS Output Data 9/ Data 8—True. 22 B D9−/D8− (MSB) Output Channel B LVDS Output Data 9/ Data 8—Complement. 32 A D1+/D0+ (LSB) Output Channel A LVDS Output Data 1/ Data 0—True. 31 A D1−/D0− (LSB) Output Channel A LVDS Output Data 1/ Data 0—Complement. 34 A D3+/D2+ Output Channel A LVDS Output Data 3/ Data 2—True. 33 A D3−/D2− Output Channel A LVDS Output Data 3/ Data 2—Complement. 36 A D5+/D4+ Output Channel A LVDS Output Data 5/ Data 4—True. 35 A D5−/D4− Output Channel A LVDS Output Data 5/ Data 4—Complement. 39 A D7+/D6+ Output Channel A LVDS Output Data 7/ Data 6—True. 38 A D7−/D6− Output Channel A LVDS Output Data 7/ Data 6—Complement. 41 A D9+/D8+ (MSB) Output Channel A LVDS Output Data 9/ Data 8—True. 40 A D9−/D8− (MSB) Output Channel A LVDS Output Data 9/ Data 8—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange Output—True. 42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 46 CSB Input SPI Chip Select (Active Low). ADC Configuration 47 OEB Input Output Enable Input (Active Low). 48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.

for I input data and the other is used for Q input data. timing between multiple channels or multiple devices. a 3-bit SPI-compatible serial interface. The AD9608 architecture consists of a multistage, pipelined ADC. combined into a final 10-bit result in the digital correction logic. of flash errors. The last stage consists of a flash ADC. power-down, the output buffers go into a high impedance state. signal-dependent errors and achieve optimum performance. Figure 42. Switched-Capacitor Input Circuit A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application.

supply (DRVDD) and should not exceed that supply voltage. proportionally shorter wake-up times. busses as shown in Figure 2. glitches on the supplies and may affect converter performance. or large fanouts may require external buffers or latches. interleaved CMOS output mode is shown in Figure 3. specific) output port disable bit (Bit 4) in Register 0x14. in the external pin mode (see Table 13). binary, twos complement, or Gray code when using the SPI control. Table 13. SCLK/DFS Mode Selection (External Pin Mode) the OEB pin is low, the output data drivers and DCOs are enabled. should not exceed that supply voltage. output port disable bit (Bit 4) in Register 0x14. delay (tPD) after the rising edge of the clock signal. transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9608 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. output using SPI Register 0x17 to increase the data setup time. a graphical timing description of the output modes. Table 14. Output Data Format

Rev. C | Page 30 of 40 OUTPUT TEST The AD9608 includes various output test options to place predictable values on the outputs of theAD9608. OUTPUT TEST MODES The output test options are described in Table 18 at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

disables the read and write cycles. Table 15. Serial Port Interface Pins synchronize serial interface reads and writes. on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. to an output at the appropriate point in the serial frame. Figure 61. Serial Port Interface Timing Diagram

controller-Based Serial Port Interface (SPI) Boot Circuit. tioning at the converter inputs during critical sampling periods. PDWN pin serve as standalone CMOS-compatible control pins. which disables the serial port interface. Table 16. Mode Selection Memory Map Register Descriptions section). Table 17. Features Accessible Using the SPI

Rev. C | Page 33 of 40 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF) and the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x102). The memory map register table (see Table 18) lists the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x05, the device index register, has a hexadecimal default value of 0x03. This means that in Address 0x05, Bits[7:2] = 0, and Bits[1:0] = 1. This setting is the default channel index setting. The default value results in both ADC channels receiving the next write command. For more information about this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers are documented in the Memory Map Register Descriptions section. Open Locations All address and bit locations that are not included in Table 18 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x05). If the entire address location is open (for example, Address 0x13), this address location should not be written to. Default Values After the AD9608 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 18. Logic Levels An explanation of logic level terminology follows:

• “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit. ”
• “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” Channel-Specific Registers Some channel setup functions can be programmed for each channel individually. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 18 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 18 affect the entire part or the channel features for which independent settings are not allowed between channels.

All address and bit locations that are not included in Table 18 are not currently supported for this device. Table 18. Memory Map Registers

Rev. C | Page 35 of 40 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Comments 0x0B Clock divide (global) Open Open Open Open Open Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 The divide ratio is value plus 1 0x0C Enhance- ment control (global) Open Open Open Open Open Chop mode 0 = disabled 1 = enabled Open Open 0x00 Chop mode enabled if Bit 2 = 1 0x0D Test mode (local) User test mode control 00 = single pattern mode 01 = alternate continuous/repeat pattern mode 10 = single once pattern mode 11 = alternate once pattern mode Reset PN long gen Reset PN short gen Output test mode 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN long sequence 0110 = PN short sequence 0111 = one/zero word toggle 1000 = user test mode 1111 = ramp output 0x00 When this register is set, the test data is placed on the output pins in place of normal data 0x10 Customer offset adjust (local) Offset adjust in LSBs from +127 to −128 (twos complement format) 0x00 0x14 Output mode Output port logic type (global) 00 = CMOS, 1.8 V 10 = LVDS, ANSI 11 = LVDS, reduced range Output interleave enable (global) Output port disable (local) Open (global) Output invert (local) Output format 00 = offset binary 01 = twos complement 10 = Gray code 0x00 Configures the outputs and the format of the data 0x15 Output adjust Open Open CMOS 1.8 V DCO drive strength 00 = 1× 01 = 2× 10 = 3× 11 = 4× Open Open CMOS 1.8 V data drive strength 00 = 1× 01 = 2× 10 = 3× 11 = 4× 0x00 Determines CMOS output drive strength properties 0x16 Clock phase control (global) Invert DCO clock 0 = not inverted 1 = inverted Open Open Open Open Input clock divider phase adjust relative to the encode clock 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x00 Allows selection of clock delays into the input clock divider 0x17 Output delay (global) DCO clock delay 0 = disabled 1 = enabled Open Data delay 0 = disabled 1 = enabled Open Open Delay selection 000 = 0.56 ns 001 = 1.12 ns 010 = 1.68 ns 011 = 2.24 ns 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x00 This sets the fine output delay of the output clock but does not change internal timing 0x18 VREF select (global) Open Open Open Open Open Internal V REF digital adjustment 000 = 1.0 V p-p 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.6 V p-p 100 = 2.0 V p-p 0x04 Select and/or adjust V REF

Rev. C | Page 36 of 40 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Comments 0x19 User Pattern 1, LSB (global) B7 B6 B5 B4 B3 B2 B1 B0 0x00 User- Defined Pattern 1, LSB 0x1A User Pattern 1, MSB (global) B15 B14 B13 B12 B11 B10 B9 B8 0x00 User- Defined Pattern 1, MSB 0x1B User Pattern 2, LSB (global) B7 B6 B5 B4 B3 B2 B1 B0 0x00 User- Defined Pattern 2, LSB 0x1C User Pattern 2, MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User- Defined Pattern 2, MSBs 0x2A Overrange control (global) Open Open Open Open Open Open Open Overrange output 0 = disabled 1 = enabled 0x01 Overrange control settings 0x2E Output assign (local) Open Open Open Open Open Open Open 0 = ADC A 1 = ADC B (local) 0x00 = ADC A 0x01 = ADC B Assign an ADC to an output channel 0x3A Sync control (global) Open Open Open Open Open Clock divider next sync only Clock divider sync enable Open 0x00 Sets the global sync options 0x100 Sample rate override Open Sample rate override enable Open Open Open Sample rate 011 = 80 MSPS 100 = 105 MSPS 101 = 125 MSPS 0x00 0x101 User I/O Control Register 2 Output enable bar (OEB) pin enable Open Open Open Open Open Open Disable SDIO pull-down 0x80 OEB and SDIO pin controls 0x102 User I/O Control Register 3 Open Open Open Open VCM power-down Open 0x00

Rev. C | Page 37 of 40 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function If set, the external PDWN pin initiates power-down mode. If clear, the external PDWN pin initiates standby mode. Bits[4:2]—Open Bits[1:0]—Internal Power-Down Mode In normal operation (Bits[1:0] = 00), both ADC channels are active. In power-down mode (Bits[1:0] = 01), the digital data path clocks are disabled while the digital data path is reset. Outputs are disabled. In standby mode (Bits[1:0] = 10), the digital data path clocks and the outputs are disabled. During a digital reset (Bits[1:0] = 11), the digital data path clocks are disabled while the digital data path is held in reset. The outputs are enabled in this state. For optimum performance, it is recom- mended that both ADC channels be reset simultaneously. This is accomplished by ensuring that both channels are selected via Register 0x05 prior to issuing the digital reset instruction. Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode For applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct-conversion receivers, chopping in the first stage of the AD9628 is a feature that can be enabled by setting Bit 2. In the frequency domain, chopping translates offsets and other low frequency noise to fCLK/2 where it can be filtered. Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type 00 = CMOS, 1.8 V 10 = LVDS, ANSI 11 = LVDS, reduced range Bit 5—Output Interleave Enable For LVDS outputs, setting Bit 5 enables interleaving. Channel A is sent coincident with a high DCO clock, and Channel B is coincident with a low DCO clock. Clearing Bit 5 disables the interleaving feature. Channel A is sent on least significant bits (LSBs), and Channel B is sent on most significant bits (MSBs). The even bits are sent coincident with a high DCO clock, and the odd bits are sent coincident with a low DCO clock. For CMOS outputs, setting Bit 5 enables interleaving in CMOS DDR mode. On ADC Output Port A, Channel A is sent coincident with a low DCO clock, and Channel B is coincident with a high DCO clock. On ADC Output Port B, Channel B is sent coincident with a low DCO clock, and Channel A is coincident with a high DCO clock. Clearing Bit 5 disables the interleaving feature, and data is output in CMOS SDR mode. Channel A is sent to Port A, and Channel B is sent to Port B. Bit 4—Output Port Disable Setting Bit 4 high disables the output port for the channels selected in Bits[1:0] of the device index register (Register 0x05). Bit 3—Open Bit 2—Output Invert Setting Bit 2 high inverts the output port data for the channels selected in Bits[1:0] of the device index register (Register 0x05). Bits[1:0]—Output Format 00 = offset binary 01 = twos complement 10 = Gray code Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only If the clock divider sync enable bit (Address 0x3A, Bit 1) is high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit resets after it syncs. Bit 1—Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high. This is continuous sync mode. Bit 0—Open Transfer (Register 0xFF) All registers except Register 0x100 are updated the moment they are written. Setting Bit 0 of this transfer register high initializes the settings in the ADC sample rate override register (Address 0x100). Sample Rate Override (Register 0x100) This register is designed to allow the user to downgrade the device. Any attempt to upgrade the default speed grade results in a chip power-down. Settings in this register are not initialized until Bit 0 of the transfer register (Register 0xFF) is written high.

Rev. C | Page 38 of 40 User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable If the OEB pin enable bit (Bit 7) is set (default), the OEB pin is enabled. If Bit 7 is clear, the OEB pin is disabled. Bits[6:1]—Open Bit 0—SDIO Pull-Down Bit 0 can be set to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bit 3 can be set high to power down the internal VCM generator. This feature is used when applying an external reference. Bits[2:0]—Open

Rev. C | Page 39 of 40 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9608 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins. Power and Ground Recommendations When connecting power to the AD9608, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD, several different decoupling capa- citors should be used to cover both high and low frequencies. Place these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. A single PCB ground plane should be sufficient when using the AD9608. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. LVDS Operation The AD9608 defaults to CMOS output mode on power-up. If LVDS operation is desired, this mode must be programmed, using the SPI configuration registers after power-up. When the AD9608 powers up in CMOS mode with LVDS termination resistors (100 Ω) on the outputs, the DRVDD current can be higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage to the AD9608, but it should be taken into account when consid- ering the maximum DRVDD current for the part. To avoid this additional DRVDD current, the AD9608 outputs can be disabled at power-up by taking the PDWN pin high. After the part is placed into LVDS mode via the SPI port, the PDWN pin can be taken low to enable the outputs. Clock Stability Considerations When powered on, the AD9608 enters an initialization phase during which an internal state machine sets up the biases and the registers for proper operation. During the initialization process, the AD9608 needs a stable clock. If the ADC clock source is not present or not stable during ADC power-up, it disrupts the state machine and causes the ADC to start up in an unknown state. To correct this, an initialization sequence must be reinvoked after the ADC clock is stable by issuing a digital reset via Register 0x08. In the default configuration (internal V REF, ac-coupled input) where VREF and VCM are supplied by the ADC itself, a stable clock during power-up is sufficient. In the case where VREF and/or VCM are supplied by an external source, these, too, must be stable at power-up; otherwise, a subsequent digital reset via Register 0x08 is needed. Interruption of the sample clock during operation and changes in sample rate also necessitate a digital reset. The pseudo code sequence for a digital reset is as follows: SPI_Write (0x08, 0x03); # Digital Reset SPI_Write (0x08, 0x00); # Can be asserted as soon as the next SPI cycle, normal operation resumes after 2.9e6 sample clock cycles, ADC outputs 0s until the reset is complete. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD9608 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged to prevent solder wicking through the vias, which can compromise the connection. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). VCM The VCM pin should be decoupled to ground with a 0.1 μF capacitor. Reference Decoupling The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9608 to keep these signals from transitioning at the converter inputs during critical sampling periods.

0.25 MIN

0.20 REF

7.50 REF

0.05 MAX

0.02 NOM

Figure 62. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the property of their respective owners.