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10-Bit, 105 MSPS/125 MSPS/150 MSPS,

1.8 V Dual Analog-to-Digital Converter

Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.

FEATURES

SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS SFDR = 81 dBc to 70 MHz at 150 MSPS Low power: 825 mW at 150 MSPS

1.8 V analog supply operation

1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply Integer 1 to 8 input clock divider Intermediate frequency (IF) sampling frequencies up to 450 MHz Internal analog-to-digital converter (ADC) voltage reference Integrated ADC sample-and-hold inputs Flexible analog input: 1 V p-p to 2 V p-p range Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable built-in self-test (BIST) capability Energy-saving power-down modes Integrated receive features Fast detect/threshold bits Composite signal monitor

APPLICATIONS

Point-to-point radio receivers (GPSK, QAM) Diversity radio systems I/Q demodulation systems Smart antenna systems Digital predistortion General-purpose software radios Broadband data applications Data acquisition Nondestructive testing PRODUCT HIGHLIGHTS 1. Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC. 2. Fast overrange detect and signal monitor with serial output. 3. Signal monitor block with dedicated serial output mode. 4. Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz. 5. The AD9600 operates from a single 1.8 V supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. 6. A standard serial port interface supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down mode, and voltage reference mode. 7. The AD9600 is pin compatible with the AD9627-11, AD9627, and AD9640 , allowing a simple migration from 10 bits to 11 b its, 12 bits, or 14 bits. FUNCTIONAL BLOCK DIAGRAM 06909-001 SIGNAL MONITOR SHA ADC CMOS/LVDS OUTPUT BUFFER D9A D0AVIN + A VIN – A DRVDDDVDDAVDD CSB SCLK/ DFS SPI PROGRAMMING DATA SDIO/ DCSFD[0:3]A FD BITS/THRESHOLD DETECT SHA ADC CMOS/LVDS OUTPUT BUFFER D0B D9BVIN + B VIN – B DCOA DCOB CLK+ CLK– DCO GENERATION DUTY CYCLE STABLIZER DIVIDE 1 TO 8 DRGNDSYNCAGND SMI SDO/ OEB SMI SCLK/ PDWN SERIAL MONITOR DATA SMI SDFS SERIAL MONITOR INTERFACE FD[0:3]B FD BITS/THRESHOLD DETECT MULTICHIP SYNC VREF SENSE CML REFERENCE SELECT AD9600 NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES. Figure 1.

AD9600* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS

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  • AD9600: 10-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet TOOLS AND SIMULATIONS
  • Visual Analog
  • AD9600 IBIS Models REFERENCE MATERIALS Technical Articles
  • MS-2210: Designing Power Supplies for High Speed ADC DESIGN RESOURCES
  • AD9600 Material Declaration
  • PCN-PDN Information
  • Quality And Reliability
  • Symbols and Footprints DISCUSSIONS View all AD9600 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. B | Page 2 of 72 TABLE OF CONTENTS

Rev. B | Page 3 of 72

REVISION HISTORY

12/09—Rev. A to Rev. B 6/09—Rev. 0 to Rev. A Changes to Signal Monitor Period (Register 0x113 to 11/07—Revision 0: Initial Version

Rev. B | Page 4 of 72 GENERAL DESCRIPTION The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS ADC. It is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compen- sate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The AD9600 has several functions that simplify the automated gain control (AGC) function in a communications receiver. For example, the fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency. In addition, the programmable threshold detector allows moni- toring the amplitude of the incoming signal with short latency, using the four fast detect bits of the ADC. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly adjust the system gain to avoid an overrange condition. Another AGC-related function of the AD9600 is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. The ADC output data can be routed directly to the two external 10-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS. In addition, flexible power-down options allow significant power savings.

Rev. B | Page 5 of 72 SPECIFICATIONS DC SPECIFICATIONS DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted. Table 1. Parameter Temp AD9600ABCPZ-105/ AD9600BCPZ-105 AD9600ABCPZ-125/ AD9600BCPZ-125 AD9600ABCPZ-150/ AD9600BCPZ-150 Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 10 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Differential Nonlinearity (DNL)1 Full ±0.2 ±0.2 ±0.2 LSB Integral Nonlinearity (INL)1 Full ±0.3 ±0.3 ±0.4 LSB MATCHING CHARACTERISTICS TEMPERATURE DRIFT Offset Error Full ±15 ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ±95 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 ±5 ±16 mV Load Regulation @ 1.0 mA Full 7 7 7 mV INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.1 0.1 0.1 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance2 Full 8 8 8 pF VREF INPUT RESISTANCE Full 6 6 6 kΩ POWER SUPPLIES Supply Voltage Supply Current IAVDD1 Full 310 385 419 mA IDVDD1 Full 34 42 50 mA IAVDD and IDVDD1, 3 365 455 495 IDRVDD (3.3 V CMOS) Full 35 36 42 mA IDRVDD (1.8 V CMOS) Full 15 18 22 mA IDRVDD (1.8 V LVDS) 42 44 46 mA POWER CONSUMPTION DC Input Full 600 650 750 800 825 890 mW Sine Wave Input1 DRVDD = 1.8 V Full 645 813 892 mW DRVDD = 3.3 V Full 740 900 990 mW Standby Power3 Full 68 77 77 mW Power-Down Power Full 2.5 6 2.5 6 2.5 6 mW 1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 8 for the equivalent analog input structure. 3 Standby power is measured with a dc input and the CLK+ and CLK− pins inactive )set to AVDD or AGND.

Rev. B | Page 6 of 72 AC SPECIFICATIONS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted. Table 2. Parameter1 Temp AD9600ABCPZ-105/ AD9600BCPZ-105 AD9600ABCPZ-125/ AD9600BCPZ-125 AD9600ABCPZ-150/ AD9600BCPZ-150 Unit Min Typ Max Min Typ Max Min Typ Max SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.3 MHz 25°C 60.7 60.6 60.6 dB fIN = 70 MHz 25°C 60.6 60.6 60.6 dB Full 60.3 60.3 60.3 dB fIN = 140 MHz 25°C 60.6 60.6 60.5 dB fIN = 220 MHz 25°C 60.5 60.5 60.4 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.3 MHz 25°C 60.6 60.5 60.5 dB fIN = 70 MHz 25°C 60.5 60.5 60.5 dB Full 60.2 60.2 60.1 dB fIN = 140 MHz 25°C 60.5 60.5 60.4 dB fIN = 220 MHz 25°C 60.4 60.4 60.3 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.3 MHz 25°C 9.9 9.9 9.9 Bits fIN = 70 MHz 25°C 9.9 9.9 9.9 Bits fIN = 140 MHz 25°C 9.9 9.9 9.9 Bits fIN = 220 MHz 25°C 9.9 9.9 9.9 Bits WORST SECOND OR THIRD HARMONIC fIN = 2.3 MHz 25°C −87.0 −86.5 −88.5 dBc fIN = 70 MHz 25°C −85.0 −85.0 −84.0 dBc Full −72.0 −72.0 −72.0 dBc fIN = 140 MHz 25°C −84.0 −84.0 −83.5 dBc fIN = 220 MHz 25°C −83.0 −83.0 −77 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.3 MHz 25°C 85.5 85.5 85.5 dBc fIN = 70 MHz 25°C 85.0 85.0 84.0 dBc Full 72.0 72.0 72.0 dBc fIN = 140 MHz 25°C 83.0 84.0 83.5 dBc fIN = 220 MHz 25°C 81.0 81.0 77 dBc WORST OTHER HARMONIC OR SPUR fIN = 2.3 MHz 25°C −92 −92 −92 dBc fIN = 70 MHz 25°C −88 -88 −88 dBc Full −81 −81 −80 dBc fIN = 140 MHz 25°C −86 −86 −86 dBc fIN = 220 MHz 25°C −86 −86 −86 dBc TWO-TONE SFDR fIN = 29.1 MHz, 32.1 MHz (−7 dBFS ) 25°C 84 84 84 dBc fIN = 169.1 MHz, 172.1 MHz (−7 dBFS ) 25°C 82 82 82 dBc CROSSTALK2 Full 95 95 95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.

Rev. B | Page 7 of 72 DIGITAL SPECIFICATIONS enabled, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 1.2 V Input Voltage Range Full GND − 0.3 AVDD + 1.6 V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ LOGIC INPUT (CSB)1 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUT (SCLK/DFS)2 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)1 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

Rev. B | Page 8 of 72 Parameter Temperature Min Typ Max Unit LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2 High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage (IOH = 50 μA) Full 3.29 V High Level Output Voltage (IOH = 0.5 mA) Full 3.25 V Low Level Output Voltage (IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (IOL = 50 μA) Full 0.05 V CMOS Mode—DRVDD = 1.8 V High Level Output Voltage (IOH = 50 μA) Full 1.79 V High Level Output Voltage (IOH = 0.5 mA) Full 1.75 V Low Level Output Voltage (IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (IOL = 50 μA) Full 0.05 V LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V 1 Pull up. 2 Pull down.

Rev. B | Page 9 of 72 SWITCHING SPECIFICATIONS enabled, unless otherwise noted. Table 4. Parameter Temp AD9600ABCPZ-105/ AD9600BCPZ-105 AD9600ABCPZ-125/ AD9600BCPZ-125 AD9600ABCPZ-150/ AD9600BCPZ-150 Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz Conversion Rate DCS Enabled Full 20 105 20 125 20 150 MSPS DCS Disabled Full 10 105 10 125 10 150 MSPS CLK Period (tCLK) Full 9.5 8 6.66 ns C L K P u l s e W i d t h H i g h Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode, DCS Enabled Full 1.6 1.6 1.6 ns Divide-by-3 Through Divide- by-8 Modes, DCS Enabled Full 0.8 0.8 0.8 ns DATA OUTPUT PARAMETERS CMOS Mode—DRVDD = 3.3 V Setup Time (tS) Full 5.25 4.5 3.83 ns Hold Time (tH) Full 4.25 3.5 2.83 ns CMOS Mode—DRVDD = 1.8 V Setup Time (tS) Full 5.25 4.5 3.83 ns Hold Time (tH) Full 4.25 3.5 2.83 ns LVDS Mode—DRVDD = 1.8 V CMOS Mode Pipeline Delay (Latency) Full 12 12 12 Cycles LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Full 12/12.5 12/12.5 12/12.5 Cycles Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms Wake-Up Time2 Full 350 350 350 μs OUT-OF-RANGE RECOVERY TIME Full 2 3 3 Cycles 1 Output propagation delay is measured from the CLK+ and CLK− pins 50% transition to the output data pins 50% transition, with 5 pF load. 2 Wake-up time is dependent on the value of the decoupling capacitors.

Figure 2. CMOS Output Mode Data and Fast Detect Output Timing

1 The output data pins are D0A/D0B to D9A/D9B for the CMOS configuration

and D0+/D0− to D9+/D9− for the LVDS configuration.

2 The fast detect output pins are FD0A/FD0B to FD3A/FD3B for the CMOS

configuration and FD0+/FD0− to FD3+/FD3−.

3 The data clock output pins are DCOA and DCOB for the CMOS configuration

and DCO+ and DCO− for the LVDS configuration. maximizing the thermal capability of the package. Table 7. Thermal Resistance 1 Per JEDEC 51-7 standard and JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Typical θJA and θJC are specified for a 4-layer board in still air.

  1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE

GROUND FOR PROPER OPERATION. Figure 6. Parallel CMOS Mode Pin Configuration (Top View) Table 8. Parallel CMOS Mode Pin Function Descriptions 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. 37 VIN + A Input Differential Analog Input Pin (+) for Channel A. 38 VIN − A Input Differential Analog Input Pin (−) for Channel A. 44 VIN + B Input Differential Analog Input Pin (+) for Channel B. 43 VIN − B Input Differential Analog Input Pin (−) for Channel B. 39 VREF I/O Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select (see Table 11 for details). 42 RBIAS Input External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. CMOS (see Figure 60 and Figure 61 for the recommended connection). ended CMOS (see Figure 60 and Figure 61 for the recommended connection).

Rev. B | Page 14 of 72 Pin No. Mnemonic Type Description ADC Fast Detect Outputs 29 FD0A Output Channel A Fast Detect Indicator (see Table 14 for details). 30 FD1A Output Channel A Fast Detect Indicator (see Table 14 for details). 31 FD2A Output Channel A Fast Detect Indicator (see Table 14 for details). 32 FD3A Output Channel A Fast Detect Indicator (see Table 14 for details). 53 FD0B Output Channel B Fast Detect Indicator (see Table 14 for details). 54 FD1B Output Channel B Fast Detect Indicator (see Table 14 for details). 55 FD2B Output Channel B Fast Detect Indicator (see Table 14 for details). 56 FD3B Output Channel B Fast Detect Indicator (see Table 14 for details). Digital Inputs 52 SYNC Input Digital Synchronization Pin (Slave Mode Only). Digital Outputs 16 to 19, 22, 23, 25 to 28 D0A to D9A Output Channel A CMOS Output Data. 62, 63, 2 to 9 D0B to D9B Output Channel B CMOS Output Data. 11 DCOA Output Channel A Data Clock Output. 10 DCOB Output Channel B Data Clock Output. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Fo rmat Select Pin in External Pin Mode. 47 SDIO/DCS I/O SPI Serial Data Input and Output/Duty Cycle Stabilizer in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Signal Monitor Port

33 SMI SDO/OEB I/O Signal Monitor Serial Data Output/Output Enable Input (Active Low) in

External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN I/O Signal Monitor Serial Clock Output/Po wer-Down Input in External Pin Mode. Do Not Connect 12 to 15, 58 to 61 DNC N/A Do Not Connect.

  1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE

GROUND FOR PROPER OPERATION. Figure 7. Interleaved Parallel LVDS Mode Pin Configuration (Top View) Table 9. Interleaved Parallel LVDS Mode Pin Function Descriptions 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the expo sed thermal pad on the bottom of the package. 37 VIN + A Input Differential Analog Input Pin (+) for Channel A. 38 VIN − A Input Differential Analog Input Pin (−) for Channel A. 44 VIN + B Input Differential Analog Input Pin (+) for Channel B. 43 VIN − B Input Differential Analog Input Pin (−) for Channel B. 39 VREF I/O Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select (see Table 11 for details). 42 RBIAS Input External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. (see Figure 60 and Figure 61 for the recommended connection). CMOS (see Figure 60 and Figure 61 for the recommended connection).

Rev. B | Page 16 of 72 Pin No. Mnemonic Type Description ADC Fast Detect Outputs 54 FD0+ Output Channel A/Channel B LVDS Fast Detect Indicator 0 True (see Table 14 for full details).

53 FD0− Output Channel A/Channel B LVDS Fast Detect Indicator 0 Complement (see Table 14

r details). 56 FD1+ Output Channel A/Channel B LVDS Fast Detect Indicator 1 True (see Table 14 for details).

55 FD1− Output Channel A/Channel B LVDS Fast Detect Indicator 1 Complement (see Table 14

details). 59 FD2+ Output Channel A/Channel B LVDS Fast Detect Indicator 2 True (see Table 14 for details).

58 FD2− Output Channel A/Channel B LVDS Fast Detect Indicator 2 Complement (see Table 14

details). 61 FD3+ Output Channel A/Channel B LVDS Fast Detect Indicator 3 True (see Table 14 for details).

60 FD3− Output Channel A/Channel B LVDS Fast Detect Indicator 3 Complement (see Table 14

r details). Digital Inputs 52 SYNC Input Digital Synchronization Pin (Slave Mode Only). Digital Outputs 9 D0+ Output Channel A/Channel B LVDS Output Data 0 True. 8 D0− Output Channel A/Channel B LVDS Output Data 0 Complement. 13 D1+ Output Channel A/Channel B LVDS Output Data 1 True. 12 D1− Output Channel A/Channel B LVDS Output Data 1 Complement. 15 D2+ Output Channel A/Channel B LVDS Output Data 2 True. 14 D2− Output Channel A/Channel B LVDS Output Data 2 Complement. 17 D3+ Output Channel A/Channel B LVDS Output Data 3 True. 16 D3− Output Channel A/Channel B LVDS Output Data 3 Complement. 19 D4+ Output Channel A/Channel B LVDS Output Data 4 True. 18 D4− Output Channel A/Channel B LVDS Output Data 4 Complement. 23 D5+ Output Channel A/Channel B LVDS Output Data 5 True. 22 D5− Output Channel A/Channel B LVDS Output Data 5 Complement. 26 D6+ Output Channel A/Channel B LVDS Output Data 6 True. 25 D6− Output Channel A/Channel B LVDS Output Data 6 Complement. 28 D7+ Output Channel A/Channel B LVDS Output Data 7 True. 27 D7− Output Channel A/Channel B LVDS Output Data 7 Complement. 30 D8+ Output Channel A/Channel B LVDS Output Data 8 True. 29 D8− Output Channel A/Channel B LVDS Output Data 8 Complement. 32 D9+ Output Channel A/Channel B LVDS Output Data 9 True. 31 D9− Output Channel A/Channel B LVDS Output Data 9 Complement. 11 DCO+ Output Channel A/Channel B LVDS Data Clock Output True. 10 DCO− Output Channel A/Channel B LVDS Data Clock Output Complement. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Fo rmat Select Pin in External Pin Mode. 47 SDIO/DCS I/O SPI Serial Data Input and Output/Duty Cycle Stabilizer in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Signal Monitor Port External Pin Mode. 35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN I/O Signal Monitor Serial Clock Output/Po wer-Down Input in External Pin Mode. Do Not Connect 2 to 7, 62, 63 DNC N/A Do Not Connect.

0.10 LSB rms

Figure 40. AD9600 Grounded Input Histogram Figure 41. AD9600 INL with fIN1 = 10.3 MHz Figure 42. AD9600 DNL with fIN1 = 10.3 MHz Figure 43. AD9600-150 SNR/SFDR vs. Duty Cycle with fIN1 = 10.3 MHz Figure 44. AD9600-150 SNR/SFDR vs. Input Common-Mode Voltage (VCM) with

Table 12. SCLK/DFS Mode Selection (External Pin Mode) driver supply (DRVDD) and should not exceed that supply voltage. using the output enable bar bit in Register 0x14. delay (tPD) after the rising edge of the clock signal. should be minimized to reduce transients within the AD9600. in Figure 2 and Figure 3 for more information. Table 13. Output Data Format

reliably determine when the converter is about to be clipped. mation on the state of the analog input that is of limited usefulness. significant slew rates, latency of this function is of major concern. resolution for this function. signals outside the desired magnitude range. tion, allowing very flexible external gain control implementations. Table 14. Fast Detect Mode Select Bits Settings

000 ADC fast magnitude (see Table 15)

001 ADC fast magnitude

010 ADC fast magnitude

011 ADC fast magnitude

100 OR C_UT F_UT F_LT

101 OR F_UT IG DG

1 The fast detect pins are FD0A/FD0B to FD9A/FD9B for the CMOS mode

2 See the ADC Overrange (OR) and Gain Switching sections for more

rmation about OR, C_UT, F_UT, F_LT, IG, and DG. datapath, there is a significant uncertainty in the level indicated. ADC fast magnitude, are shown in Table 15. Table 15. ADC Fast Magnitude Nominal Levels with

modes, the fast detect output pins have a latency of six clock cycles. fast magnitude is presented on the FD [3:1] pins). Table 16. ADC Fast Magnitude Nominal Levels with Table 17. ADC Fast Magnitude Nominal Levels with would be indicated by this bit 12 clock cycles after it occurred. Table 18. Coarse Upper Threshold Levels

in Equation 1 (see the Fine Upper Threshold (F_UT) section). The operation of the IG and DG indicators is shown in Figure 66. NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF TWO ADC CLOCK CYCLES. *C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY. Figure 66. Threshold Settings for C_UT, F_UT, F_LT, IG, and DG

signal with significant dc content, such as GSM. bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS). bandwidth register located at Register 0x10C, Bits [5:2]. 15 provides the same result as programming 13). CLK is the AD9600 ADC sample rate in hertz. value that can span the entire input range of the ADC. dc correction and adds the currently calculated value to the data. enables the dc correction for use in the signal monitor calculations. be added to the output data signal path. all three SPORT output pins on the chip. not needed can reduce coupling errors in the return signal path. left enabled to ease frequency planning. sync, followed by data from Datapath B. value and the threshold crossing value, as shown in Figure 70.

20 CYCLES 16 CYCLES16 CYCLES 20 CYCLES 16 CYCLES 16 CYCLES

Figure 70. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)

20 CYCLES 16 CYCLES 20 CYCLES 16 CYCLES

Figure 71. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)

Rev. B | Page 36 of 72 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9600 includes built-in test features to enable verification of the integrity of each channel as well as to facilitate board level debugging. A BIST feature is included that verifies the integrity of the digital datapath of the AD9600. V arious output test options are also provided to place predictable values on the outputs of the AD9600. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9600 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath, starting at the ADC block output. The BIST sequence runs for 512 cycles and then stops. The BIST signature value for Channel A or Channel B is placed in Register 0x24 and Register 0x25. If one channel is chosen, its BIST signature is written to the two registers. If both channels are chosen, the results of the two channels are XOR’ ed and placed in the BIST signature registers. The outputs are not disconnected during this test; therefore, the PN sequence can be observed as it runs. The PN sequence can be continued from its last value or started from the beginning, based on the value programmed in Bit 2 of Register 0x0E. The BIST signature result varies depending on the channel configuration. OUTPUT TEST MODES The output test options are shown in Table 22. When an output te st mode is enabled, the analog section of the ADC is discon- nected from the digital back end blocks, and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The seed value for the PN sequence tests can be forced by setting Bit 4 or Bit 5 of the test mode register (Address 0x0D) to hold the generator in reset mode. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

Rev. B | Page 37 of 72 CHANNEL/CHIP SYNCHRONIZATION The AD9600 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful to guarantee synchronized sample clocks across multiple ADCs. The signal monitor block can also be synchronized using the SYNC input, allowing properties of the input signal to be measured during a specific period. The input clock divider can be enabled to synchronize on a single occurrence of the sync signal or on every occurrence. The signal monitor block is synchronized on every SYNC input signal. The SYNC input is internally synchronized to the sample clock; however, to ensure there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 5. The SYNC input should be driven us ing a single-ended CMOS-type signal.

low control that enables or disables the read and write cycles. Table 19. Serial Port Interface Pins synchronize serial interface reads and writes. on any secondary functions of the SPI pin. During an instruction phase, a 16-bit instruction is transmitted. represented by W1:W0 + 1 is the number of bytes to transfer. Interfacing to High Speed ADCs via SPI. Based Serial Port Interface (SPI) Boot Circuit. inputs during critical sampling periods. rappable functions supported on the AD9600.

Table 20. Mode Selection Table 21. Features Accessible Using the SPI Figure 72. Serial Port Interface Timing Diagram

Rev. B | Page 40 of 72 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map registers table (Table 22) has eight bi t locations. The memory map is divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02), the channel index and transfer registers (Address 0x05 and Address 0xFF), the ADC functions registers (Address 0x08 to Address 0x25), and the digital feature control registers (Address 0x100 to Address 0x11B). The leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. The (MSB) Bit 7 column is the start of the default hexadecimal value given. For example, Address 0x18, the VREF select register, has a default value of 0xC0, meaning that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This setting is the default reference selection setting. The default value uses a 2.0 V peak-to-peak reference. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers (from Register 0x100 to Register 0x11B) are documented in the Memory Map Register Description section. Open Locations All address and bit locations that are not included in Table 22 ar e currently not supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values When the AD9600 comes out of a reset, critical registers are loaded with default values. The default values for the registers are given in the memory map registers table (Table 22). Logic Levels An explanation of logic level terminology follows:

  • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit. ”
  • “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” Transfer Register Map Address 0x08 to Address 0x18 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simulta- neously when the transfer bit (Bit 0 of Register 0xFF) is set. The internal update takes place when the transfer bit is set, and the bit autoclears. Channel-Specific Registers Some channel setup functions, such as the signal monitor thresholds, can be individually programmed for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers are designated as local registers in Table 22 and can be accessed by setting the ap propriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. On the other hand, registers that are designated as global registers in Table 22 affect the entire part or the channel features for which indep endent settings are not allowed between the channels. The settings in Register 0x05 do not affect the global registers.

All address and bit locations that are not included in Table 22 are currently not supported for this device. Table 22. Memory Map Registers

0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles

Rev. B | Page 42 of 72 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0x0E BIST Enable (Local) Open Open Open Open Open Reset BIST sequence Open BIST enable 0x00 0x10 Offset Adjust (Local) Open Open Offset adjust in LSBs from +31 to −32 (twos complement format) 0x00 0x14 Output Mode Drive strength 0 V to 3.3 V CMOS or ANSI LVDS: 1 V to 1.8 V CMOS or reduced: LVDS (global) Output type 0 = CMOS 1 = LVDS (global) Open Output enable bar (local) Open Output invert (local) 00 = offset binary 01 = twos complement 01 = gray code 11 = offset binary (local) 0x00 Configures the outputs and the format of the data. 0x16 Clock Phase Control (Global) Invert DCO clock Open Open Open Open In put clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x00 Allows selection of clock delays into the input clock divider. 0x17 DCO Output Delay (Global) Open Open Open DCO clock delay (delay = 2500 ps × register value/31) 00000 = 0 ps 00001 = 81 ps 00010 = 161 ps 11110 = 2419 ps 11111 = 2500 ps 0x00 0x18 VREF Select (Global) Reference voltage selection 00 = 1.25 V p-p 01 = 1.5 V p-p 10 = 1.75 V p-p 11 = 2.0 V p-p (default) Open Open Open Open Open Open 0xC0 0x24 BIST Signature LSB (Local) BIST signature [7:0] 0x00 Read only. 0x25 BIST Signature MSB (Local) BIST signature [15:8] 0x00 Read only. Digital Feature Control Registers 0x100 Sync Control (Global) Signal monitor sync enable Open Open Open Open Clock divider next sync only Clock divider sync enable Master sync enable 0x00 0x104 Fast Detect Control (Local) Open Open Open Open Fast Dete ct Mode Select [2:0] Fast detect enable 0x00 0x105 Coarse Upper Threshold (Local) Open Open Open Open Open Coarse Upper Threshold [2:0] 0x00 0x106 Fine Upper Threshold Register 0 (Local) Fine Upper Threshold [7:0] 0x00 0x107 Fine Upper Threshold Register 1 (Local) Open Open Open Fine Upper Threshold [12:8] 0x00 0x108 Fine Lower Threshold Register 0 (Local) Fine Lower Threshold [7:0] 0x00 0x109 Fine Lower Threshold Register 1 (Local) Open Open Open Fine Lower Threshold [12:8] 0x00

Rev. B | Page 43 of 72 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0x10A Increase Gain Dwell Time Register 0 (Local) Increase Gain Dwell Time [7:0] 0x00 In ADC clock cycles. 0x10B Increase Gain Dwell Time Register 1 (Local) Increase Gain Dwell Time [15:8] 0x00 In ADC clock cycles. 0x10C Signal Monitor DC Correction Control (Global) Open DC correction freeze DC Correction Bandwidth [3:0] DC correction for signal path enable DC correction for signal monitor enable 0x00 0x10D Signal Monitor DC Value Channel A Register 0 (Global) DC Value Channel A [7:0] Read only. 0x10E Signal Monitor DC Value Channel A Register 1 (Global) Open Open DC Value Channel A [13:8] Read only. 0x10F Signal Monitor DC Value Channel B Register 0 (Global) DC Value Channel B [7:0] Read only. 0x110 Signal Monitor DC Value Channel B Register 1 (Global) Open Open DC Value Channel B [13:8] Read only 0x111 Signal Monitor SPORT Control (Global) Open RMS/MS magnitude output enable Peak detector output enable Threshold crossing output enable SPORT SMI SCLK divide 00 = undefined 01 = divide by 2 10 = divide by 4 11 = divide by 8 SPORT SMI SCLK sleep Signal monitor SPORT output enable 0x04 0x112 Signal Monitor Control (Global) Complex power calculation mode enable Open Open Open Signal monitor rms/ms select 0 = rms 1 = ms Signal monitor mode 00 = rms/ms magnitude 01 = peak power 10 = threshold crossing 11 = threshold crossing Signal monitor enable 0x00 0x113 Signal Monitor Period Register 0 (Global) Signal Monitor Period [7:0] 0x40 In ADC clock cycles. 0x114 Signal Monitor Period Register 1 (Global) Signal Monitor Period [15:8] 0x00 In ADC clock cycles. 0x115 Signal Monitor Period Register 2 (Global) Signal Monitor Period [23:16] 0x00 In ADC clock cycles. 0x116 Signal Monitor Result Channel A Register 0 (Global) Signal Monitor Result Channel A [7:0] Read only. 0x117 Signal Monitor Result Channel A Register 1 (Global) Signal Monitor Result Channel A [15:8] Read only.

Rev. B | Page 44 of 72 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0x118 Signal Monitor Result Channel A Register 2 (Global) Open Open Open Open Signal Monitor Value Channel A [19:16] Read only. 0x119 Signal Monitor Result Channel B Register 0 (Global) Signal Monitor Result Channel B [7:0] Read only. 0x11A Signal Monitor Result Channel B Register 1 (Global) Signal Monitor Result Channel B [15:8] Read only. 0x11B Signal Monitor Result Channel B Register 2 (Global) Open Open Open Open Signal Monitor Result Channel B [19:16] Read only. MEMORY MAP REGISTER DESCRIPTION For information about functions controlled in Register 0x00 to Register 0xFF, see Application Note AN-877, Interfacing to High Speed ADCs via SPI. Sync Control (Register 0x100) Bit 7—Signal Monitor Sync Enable Bit 7 enables the sync pulse from the external sync input to the signal monitor block. The sync signal is passed when both Bit 7 and Bit 0 are high. This is continuous sync mode. Bits [6:3]—Reserved Bit 2—Clock Divider Next Sync Only If the master sync enable bit (Address 0x100 [0]) is high and the clock divider sync enable bit (Address 0x100 [1]) is high, the clock divider next sync only bit (Address 0x100 [2]) allows the clock divider to sync to the first sync pulse it receives and ignore the rest. The clock divider sync enable bit (Address 0x100 [1]) resets after it syncs. Bit 1—Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider. The sync signal is passed when both Bit 1 and Bit 0 are high. This is continuous sync mode. Bit 0—Master Sync Enable Bit 0 must be high to enable the sync functions. Fast Detect Control (Register 0x104) Bits [7:4]—Reserved Bits [3:1]—Fast Detect Mode Select These bits set the mode of the fast detect output pins according to Table 14. Bit 0—Fast Detect Enable Bit 0 is used to enable the fast detect output pins. When the fast detect output pins are disabled, the outputs go into a high impedance state. In LVDS mode, when the fast detect output pins are interleaved, the outputs go high-Z only if both channels are turned off (power-down/standby/output disabled). If only one channel is turned off (power-down/standby/output disabled), the fast detect output pins repeat the data of the active channel. Coarse Upper Threshold (Register 0x105) Bits [7:3]—Reserved Bits [2:0]—Coarse Upper Threshold These bits set the level required to assert the coarse upper threshold indication (see Table 18). Fine Upper Threshold (Register 0x106 and Register 0x107) Register 0x106, Bits [7:0]—Fine Upper Threshold [7:0] Register 0x107, Bits [7:5]—Reserved Register 0x107, Bits [4:0]—Fine Upper Threshold [12:8] These registers provide the fine upper limit threshold. This 13-bit value is compared with the 10-bit magnitude from the ADC block. If the ADC magnitude exceeds this threshold value, the F_UT indicator is set. Fine Lower Threshold (Register 0x108 and Register 0x109) Register 0x108, Bits [7:0]—Fine Lower Threshold [7:0] Re gister 0x109, Bits [7:5]—Reserved Register 0x109, Bits [4:0]—Fine Lower Threshold [12:8] These registers provide a fine lower limit threshold. This 13-bit value is compared with the 10-bit magnitude from the ADC block. If the ADC magnitude is less than this threshold value, the F_LT indicator is set.

Rev. B | Page 45 of 72 Increase Gain Dwell Time (Register 0x10A and Register 0x10B) Register 0x10A, Bits [7:0]—Increase Gain Dwell Time [7:0] Re gister 0x10B, Bits [7:0]—Increase Gain Dwell Time [15:8] These registers are programmed with the dwell time in ADC clock cycles. The signal must be below the fine lower threshold value before the increase gain (IG) indicator is asserted. Signal Monitor DC Correction Control (Register 0x10C) Bit 7—Reserved Bi t 6—DC Correction Freeze When Bit 6 is set high, the dc correction is not updated to the signal monitor block; therefore, the block continues to hold the last dc value that it calculated. Bits [5:2]—DC Correction Bandwidth These bits set the averaging time of the power monitor dc correction function. This 4-bit word sets the bandwidth of the correction block according to the following equation: π ×× =− − 22 _ _14 CLKk fBW Corr DC where: k is the 4-bit value programmed in Register 0x10C, Bits [5:2] (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). f CLK is the AD9600 ADC sample rate in hertz. Bit 1—DC Correction for Signal Path Enable Setting Bit 1 high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path. Bit 0—DC Correction for Signal Monitor Enable Bit 0 enables the dc correction function in the signal monitor block. The dc correction is an averaging function that can be used by the signal monitor to remove dc offset in the signal. Removing this dc from the measurement allows a more accurate reading. Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E) Register 0x10D, Bits [7:0]—DC Value Channel A [7:0] Register 0x10E, Bits [7:6]—Reserved Register 0x10E, Bits [5:0]—DC Value Channel A [13:8] These read-only registers hold the latest dc offset value computed by the signal monitor for Channel A. Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x10F Bits [7:0]—DC Value Channel B [7:0] Register 0x110 Bits [7:6]—Reserved Register 0x110 Bits [5:0]—DC Value Channel B [13:8] These read-only registers hold the latest dc offset value computed by the signal monitor for Channel B. Signal Monitor SPORT Control (Register 0x111) Bit 7—Reserved Bit 6—RMS/MS Magnitude Output Enable These bits enable the 20-bit rms or ms magnitude measurement as output on the SPORT. Bit 5—Peak Detector Output Enable Bit 5 enables the 10-bit peak measurement as output on the SPORT. Bit 4—Threshold Crossing Output Enable Bit 4 enables the 10-bit threshold measurement as output on the SPORT . Bits [3:2]—SPORT SMI SCLK Divide The values of these bits set the SPORT SMI SCLK divide ratio from the input clock. A value of 0x01 sets divide by 2 (default), a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8. Bit 1— SPORT SMI SCLK Sleep Setting Bit 1 high causes the SMI SCLK to remain low when the signal monitor block has no data to transfer. Bit 0—Signal Monitor SPORT Output Enable When set, Bit 0 enables the SPORT output of the signal monitor to begin shifting out the result data from the signal monitor block. Signal Monitor Control (Register 0x112) Bit 7—Complex Power Calculation Mode Enable This mode assumes that I data is present on one channel and Q data is present on the opposite channel. The result reported is the complex power, measured as 2 2Q I+ Bits [6:4]—Reserved Bit 3—Signal Monitor RMS/MS Select Setting Bit 3 low selects rms power measurement mode. Setting Bit 3 high selects ms power measurement mode. Bits [2:1]—Signal Monitor Mode Bit 2 and Bit 1 set the mode of the signal monitor for the data output of Register 0x116 to Register 0x11B. Setting Bit 2 and Bit 1 to 00 selects rms/ms magnitude output, setting these bits to 01 selects peak power output, and setting to 10 or 11 selects threshold crossing output. Bit 0—Signal Monitor Enable Setting Bit 0 high enables the signal monitor block.

Rev. B | Page 46 of 72 Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits [7:0]—Signal Monitor Period [7:0] Register 0x114, Bits [7:0]—Signal Monitor Period [15:8] Register 0x115, Bits [7:0]—Signal Monitor Period [23:16] This 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. Although this register defaults to 64 (0x40), the minimum value for this register is 128 (0x80) cycles—writing values less than 128 can cause inaccurate results. Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits [7:0]—Signal Monitor Result Ch annel A [7:0] Register 0x117, Bits [7:0]—Signal Monitor Result Ch annel A [15:8] Register 0x118, Bits [7:4]—Reserved Register 0x118, Bits [3:0]—Signal Monitor Result Ch annel A [19:16] This 20-bit value contains the result calculated by the signal monitoring block for Channel A. The content is dependent on the settings in Bits [2:1] of Register 0x112. Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x119, Bits [7:0]— Signal Monitor Result Ch annel B [7:0] Register 0x11A, Bits [7:0]—Signal Monitor Result Ch annel B [15:8] Register 0x11B, Bits [7:4]—Reserved Register 0x11B, Bits [3:0]—Signal Monitor Result Ch annel B [19:16] This 20-bit value contains the result calculated by the signal monitoring block for Channel B. The content is dependent on the settings in Bits [2:1] of Register 0x112.

Rev. B | Page 47 of 72 APPLICATIONS INFORMATION DESIGN GUIDELINES When designing the AD9600 into a system, the designer should, before starting design and layout, become familiar with these guidelines, which discuss the special circuit connections and layout requirements for certain pins. Power and Ground Recommendations When connecting power to the AD9600, the designer should use two separate 1.8 V supplies: one supply should be used for A VDD and DVDD and a separate supply for DRVDD. The AVDD and DVDD supplies, although derived from the same source, should be isolated with a ferrite bead or filter choke and have separate decoupling capacitors. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the part’s pins with minimal trace length. A single PC board ground plane should be sufficient when using the AD9600. With proper decoupling and smart parti- tioning of the PC board’s analog, digital, and clock sections, optimum performance can be easily achieved. Exposed Paddle Thermal Heat Slug Recommendations To achieve the best electrical and thermal performance of the AD9600, the exposed paddle on the underside of the ADC must be connected to analog ground (AGND). A continuously exposed (no solder mask) copper plane on the PCB should mate to the exposed paddle, Pin 0, of the AD9600. In addition, the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB, and these vias should be filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and PCB, overlay a silkscreen to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and PCB. See the evaluation board layout figures (Figure 84 to Figure 91) for an example of a PCB layo ut. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). CML The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 47. RBIAS The AD9600 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This register sets the master current reference of the ADC core and should have at least a 1% tolerance. Reference Decoupling The VREF pin should be externally decoupled to ground with a low-ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic low- ESR capacitor. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade the converter’s performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9600 in order to keep these signals from transitioning at the converter inputs during critical sampling periods.

Rev. B | Page 49 of 72 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings, or modes, allowed on the AD9600 evaluation board. POWER Connect the switching power supply that is provided with the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P500. VIN The evaluation board is set up for a double-balun configur- ation analog input with an optimum 50 Ω impedance matching from 70 MHz to 200 MHz. For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed (see Table 10). The common mode of the analog inputs is de veloped from the center tap of the transformer via the CML pin of the ADC (see the Analog Input Considerations section). VREF VREF is set to 1.0 V by tying the SENSE pin to ground and adding a jumper on Header J5 (Pin 1 to Pin 2). This causes the ADC to operate in the 2.0 V p-p full-scale range. To place the ADC in the 1.0 V p-p mode (VREF = 0.5 V), a jumper should be placed on Header J4. A separate external reference option is also included on the evaluation board. To use an external reference, connect Pin 1 of J6 to Pin 2 of J6 and provide an external reference at TP5. Proper use of the VREF options is detailed in the Voltage Reference section. RBIAS RBIAS requires that a 10 kΩ resistor (R503) be connected to ground. This pin is used to set the ADC core bias current. CLOCK The default clock input circuitry is derived from a simple balun- coupled circuit using a high bandwidth 1:1 impedance ratio balun (T5) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single- ended sine wave inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. When the AD9600 input clock divider is used, clock frequencies up to 625 MHz can be input into the evaluation board through Connector S5. PDWN To enable the power-down feature, connect J7, shorting the PDWN pin to AVDD. CSB The CSB pin is internally pulled up, setting the chip into external pin mode, to ignore the SDIO and SCLK information. To connect the control of the CSB pin to the SPI circuitry on the evaluation board, connect Pin 1 of J21 to Pin 2 of J21. SCLK/DFS If the SPI port is in external pin mode, the SCLK/DFS pin sets the data format of the outputs. If the pin is left floating, the pin is internally pulled down, setting the default data format condition to offset binary. Connecting Pin 1 of J2 to Pin 2 of J2 sets the format to twos complement. If the SPI port is in serial pin mode, connecting Pin 2 of J2 to Pin 3 of J2 connects the SCLK pin to the on-board SPI circuitry (see the Serial Port Interface (SP I) section). SDIO/DCS If the SPI port is in external pin mode, the SDIO/DCS pin acts to set the duty cycle stabilizer. If the pin is left floating, the pin is internally pulled up, setting the default condition to DCS enabled. To disable the DCS, connect Pin 1 of J1 to Pin 2 of J1. If the SPI port is in serial pin mode, connecting Pin 2 of J1 to Pin 3 of J1 connects the SDIO pin to the on-board SPI circuitry (see the Serial Port Interface (SPI) section). ALTERNATIVE CLOCK CONFIGURATIONS Two clocking options are provided on the AD9600 evaluation board. The first option is to use the on-board crystal oscillator (Y1) to provide the clock input to the part. To enable this crystal, Resistors R8 (0 Ω) and R85 (10 kΩ) should be installed and Resistors R82 and R30 should be removed. The second option is to use a differential LVPECL clock to drive the ADC input using the AD9516-4 (U2). When using thi s option, the AD9516-4 charge-pump filter components need to b e populated (see Figure 78). Consult the AD9516-4 dat a sheet for more information. To configure the clock input (from S5) to drive the AD9516 ref erence input instead of directly driving the ADC, the following components need to be added, removed, and/or changed. 1. Remove R32, R33, R99, and R101 in the default clock path. 2. Populate C78 and C79 with 0.001 μF capacitors and R78 and R79 with 0 Ω resistors in the clock path. Additionally, unused AD9516 outputs (one LVDS and one LVPECL) are routed to optional Connectors S8 through S11 on the evaluation board.

Rev. B | Page 50 of 72 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this d rive option, some additional components need to be populated. For more details on the AD8352 differential driver, including how it works and its optional pin settings, consult the AD8352 data sheet. To configure the analog input to drive the AD8352 instead of the default transformer option, the following components need to be added, removed, and/or changed for Channel A. In addition, the corresponding components for Channel B should be changed. 1. Remove C1, C17, C18, and C117 in the default analog input path. Populate C8 and C9 with 0.1 μF capacitors in the analog input path. To drive the AD8352 in the differential input mo de populate Transformer T10; Resistors R1, R37, R39, R126, and R127; and Capacitors C10, C11, and C125. 3. Populate the optional amplifier output path with the desired components, including an optional low-pass filter. Install 0 Ω Resistors R44 and R48. Resistors R43 and R47 should be increased (typically to 100 Ω) to increase the output impedance seen by the AD8352 to 200 Ω.

Figure 74. Evaluation Board Schematic, Channel A Analog Inputs

Figure 75. Evaluation Board Schematic, Channel B Analog Inputs

Figure 76. Evaluation Board Schematic, DUT Clock Input

Figure 77. Evaluation Board Schematic, Optional AD9516 Clock Circuit

Figure 78. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input

1 TP3

Figure 79. Evaluation Board Schematic, DUT

Figure 80. Evaluation Board Schematic, Digital Output Interface

Figure 81. Evaluation Board Schematic, SPI Circuitry

Figure 82. Evaluation Board Schematic, Power Supply

3 ADP333 9

Figure 83. Evaluation Board Schematic, Power Supply (Continued)

Figure 84. Evaluation Board Layout, Primary Side

Figure 85. Evaluation Board Layout, Ground Plane

Figure 86. Evaluation Board Layout, Power Plane

Figure 87. Evaluation Board Layout, Power Plane

Figure 88. Evaluation Board Layout, Ground Plane

Figure 89. Evaluation Board Layout, Secondary Side (Mirrored Image)

Figure 90. Evaluation Board Layout, Silkscreen, Primary Side

Figure 91. Evaluation Board Layout, Silk Screen, Secondary Side

Table 23. Evaluation Board Bill of Materials (BOM)1, 2

Rev. B | Page 70 of 72 Item Qty Reference Designator Description Package Manufacturer Mfg. Part Number 26 1 R16 261 Ω, 0603, 1/10 W, 1% resistor R0603 NIC Components NRC06F2610TRF 27 3 R17, R22, R23 100 kΩ, 0603, 1/10 W, 1% resistor R0603 NIC Components NRC06F 1003TRF 28 7 R18, R24, R63, R65, R82, R118, R140 10 kΩ, 0402, 1/16 W, 1% resistor R0402SM NIC Components NRC04F 1002TRF 29 3 R19, R20, R21 1 kΩ, 0603, 1/10 W, 1% resistor R0603 NIC Components NRC06F 1001TRF 30 9 R26, R27, R43, R46, R47, R70, R71, R73, R74 33 Ω, 0402, 1/16 W, 5% resistor R0402SM NIC Components NRC04J330TRF 31 5 R57, R59 to R62 22 Ω, 16-pin, 8-resistor, resistor array R_742 CTS Corporation 742C163220JPTR 32 1 R58 22 Ω, 8-pin, 4-resistor, resistor array RES_ARRY CTS Corporation 742C083220JPTR 33 1 R76 200 Ω, 0402, 1/16 W, 1% resistor R0402SM NIC Components NCR04F2000TRF 34 4 S2, S3, S5 ,S12 SMA, inline, male, coaxial connector SMA_EDGE Emerson Network Power 142-0701-201 35 1 SJ35 0 Ω, 1/8 W, 1% resistor SLDR_PAD2MUYLAR NIC Components NRC10ZOTRF 36 5 T1 to T5 Balun TRAN6B M/A-COM MABA-007159-000000 37 1 U1 IC, AD9600 LFCSP64-9X9-9E Analog Devices AD9600BCPZ/AD9600AB CPZ 38 1 U2 Clock distribution, PLL IC LFCSP64-9X9 Analog Devices AD9516-4BCPZ 39 1 U3 Dual inverter IC SC70_6 Fairchild Semiconductor NC7WZ04P6X_NL 40 1 U7 Dual buffer IC, open-drain circuits SC70_6 Fairchild Semiconductor NC7WZ07P6X_NL 41 1 U8 UHS dual buffer IC SC70_6 Fairchild Semiconductor NC7WZ16P6X_NL 42 3 U15 to U17 16-bit CMOS buffer IC TSOP48_8_1MM Fairchild Semiconductor 74VCX16244MTDX_NL 43 2 VR1, VR2 Adjustable regulator LFC SP8-3X3 Analog Devices ADP3334ACPZ 44 1 VR3 1.8 V high accuracy regulator SO T223-HS Analog Devices ADP3339AKCZ-1.8 45 1 VR4 5.0 V high accuracy regulator SOT223-HS Analog Devices ADP3339AKCZ-5.0 46 2 VR5, VR6 3.3 V high accuracy regulato r SOT223-HS Analog Devices ADP3339AKCZ-3.3 47 1 Y1 Oscillator clock, VFAC3 OSC-CTS-CB3 Valpey Fisher VFAC3-BHL 48 2 Z1, Z2 High speed IC, op amp LFCSP16-3X3-PAD Analog Devices AD8352ACPZ 1 This bill of materials is RoHS compliant. 2 The bill of materials lists only those items that are normally installed in the default condition. Items that are not installed are not included in the BOM.

0.25 MIN

0.20 REF

0.65 TYP

0.05 MAX

0.02 NOM

0.60 MAX

Figure 92. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Figure 93. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. B | Page 72 of 72 ORDERING GUIDE Model Temperature Range Package Description Package Option AD9600ABCPZ-1501,2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9600ABCPZ-1251,2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9600ABCPZ-1051,2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6 AD9600BCPZ-1501 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3 AD9600BCPZ-1251 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3 AD9600BCPZ-1051 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3 AD9600-150EBZ1 Evaluation Board with AD9600 and Software 1 Z = RoHS Compliant Part. 2 Recommended for use in new designs; reference PCN 09_0156. ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06909-0-12/09(B)