AD9520-0BCPZ

AD9520-0 AD | Alldatasheet

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Technical content

12 LVPECL/24 CMOS Output Clock

Generator with Integrated 2.8 GHz VCO AD9520-0 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.

FEATURES

Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.53 GHz to 2.95 GHz Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.67 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Auto and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 1.6 GHz LVPECL outputs divided into 4 groups Each group of 3 has a 1-to-32 divider with phase delay Additive output jitter as low as 225 fs rms Channel-to-channel skew grouped outputs <16 ps Each LVPECL output can be configured as 2 CMOS outputs (for f OUT ≤ 250 MHz) Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed SPI- and I²C-compatible serial control port 64-lead LFCSP Nonvolatile EEPROM stores configuration settings

APPLICATIONS

Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures GENERAL DESCRIPTION The AD9520-01 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHz to 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used. FUNCTIONAL BLOCK DIAGRAM OPTIONAL REF1 REF2 CLK LF SWITCHOVER AND MONITOR PLL DIVIDER AND MUXES ZERO DELAY CP VCO STATUS MONITOR SPI/I2C CONTROL PORT AND DIGITAL LOGIC EEPROM AD9520 OUT0 OUT1 OUT2 DIV/Φ OUT3 OUT4 OUT5 DIV/Φ OUT6 OUT7 OUT8 DIV/Φ OUT9 OUT10 OUT11 DIV/Φ LVPECL/ CMOS REFIN REFIN 07213-001 Figure 1. The AD9520 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset. The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs. Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set. The AD9520 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V . A separate output driver power supply can be from 2.375 V to 3.465 V . The AD9520 is specified for operation over the standard industrial range of −40°C to +85°C. 1 The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-0 is used, it is referring to that specific member of the AD9520 family.

Rev. 0 | Page 2 of 84 TABLE OF CONTENTS Clock Output Additive Phase Noise (Distribution Only; Clock Output Absolute Phase Noise (Internal VCO Used) .. 11 Clock Output Absolute Time Jitter (Clock Generation Clock Output Absolute Time Jitter (Clock Cleanup Clock Output Absolute Time Jitter (Clock Generation Clock Output Additive Time Jitter (VCO Divider Mode 1: Clock Distribution or External VCO Mode 2: High Frequency Clock Distribution—

Rev. 0 | Page 3 of 84 Soft Reset to Settings in EEPROM when Using the AD9520 Outputs for ADC Clock Applications .... 82

REVISION HISTORY

9/08—Revision 0: Initial Version

Rev. 0 | Page 4 of 84 SPECIFICATIONS Typical (typ) is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments VS 3.135 3.3 3.465 V 3.3 V ± 5% VS_DRV 2.375 VS V This is nominally 2.5 V to 3.3 V ± 5% VCP VS 5.25 V This is nominally 3.3 V to 5.0 V ± 5% RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 5.1 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA); actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground PLL CHARACTERISTICS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments VCO (ON-CHIP) Frequency Range 2530 2950 MHz See Figure 13 VCO Gain (KVCO) 52 MHz/V See Figure 8 Tuning Voltage (VT) 0.5 VCP − 0.5 V VCP ≤ VS when using internal VCO Frequency Pushing (Open-Loop) 1 MHz/V Phase Noise @ 1 kHz Offset −51 dBc/Hz f = 2550 MHz Phase Noise @ 100 kHz Offset −108 dBc/Hz f = 2550 MHz Phase Noise @ 1 MHz Offset −127 dBc/Hz f = 2550 MHz REFERENCE INPUTS Differential Mode (REFIN, REFIN) Differential mode (can accommodate single-ended input by ac grounding undriven input) Input Frequency 0 250 MHz Frequencies below about 1 MHz should be dc-coupled; be careful to match VCM (self-bias voltage) Input Sensitivity 280 mV p-p Self-Bias Voltage, REFIN 1.34 1.60 1.75 V Self-bias voltage of REFIN1 Self-Bias Voltage, REFIN 1.30 1.50 1.60 V Self-bias voltage of REFIN1 Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased1 Input Resistance, REFIN 4.4 5.3 6.4 kΩ Self-biased1 Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs Input Frequency (AC-Coupled with DC Offset Off) 10 250 MHz Slew rate must be > 50 V/μs Input Frequency (AC-Coupled with DC Offset On)

250 MHz Slew rate must be > 50 V/μs, and input amplitude

sensitivity specification must be met; see input sensitivity Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/μs; CMOS levels Input Sensitivity (AC-Coupled with DC Offset Off) 0.55 3.28 V p-p VIH should not exceed VS Input Sensitivity (AC-Coupled with DC Offset On) 1.5 2.78 V p-p VIH should not exceed VS Input Logic High, DC Offset Off 2.0 V Input Logic Low, DC Offset Off 0.8 V Input Current −100 +100 μA Input Capacitance 2 pF Each pin, REFIN (REF1)/REFIN (REF2)

Rev. 0 | Page 5 of 84 Parameter Min Typ Max Unit Test Conditions/Comments Crystal Oscillator Crystal Resonator Frequency Range 16.67 33.33 MHz Maximum Crystal Motional Resistance 30 Ω PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pulse width = 6.0 ns Reference Input Clock Doubler Frequency 0.004 50 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns Antibacklash Pulse Width 1.3 ns 0x017[1:0] = 01b 2.9 ns 0x017[1:0] = 00b; 0x017[1:0] = 11b 6.0 ns 0x017[1:0] = 10b CHARGE PUMP (CP) ICP Sink/Source Programmable High Value 4.8 mA With CPRSET = 5.1 kΩ; higher ICP is possible by changing CPRSET Low Value 0.60 mA With CPRSET = 5.1 kΩ; lower ICP is possible by changing CPRSET Absolute Accuracy 2.5 % Charge pump voltage set to VCP/2 CPRSET Range 2.7 10 kΩ ICP High Impedance Mode Leakage 1 nA Sink-and-Source Current Matching 1 % 0.5 V < VCP < VCP − 0.5 V; VCP is the voltage on the CP (charge pump) pin; VCP is the voltage on the VCP power supply pin ICP vs. VCP 1.5 % 0.5 V < VCP < VCP − 0.5 V ICP vs. Temperature 2 % VCP = VCP/2 V PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 1 FD 300 MHz P = 2 FD 600 MHz P = 3 FD 900 MHz P = 2 DM (2/3) 600 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 2400 MHz P = 16 DM (16/17) 3000 MHz P = 32 DM (32/33) 3000 MHz Prescaler Output Frequency 300 MHz A, B counter input frequency (prescaler input frequency divided by P) PLL N DIVIDER DELAY Register 0x019[2:0]; see Table 53

000 Off

PLL R DIVIDER DELAY Register 0x019[5:3]; see Table 53

Rev. 0 | Page 6 of 84 Parameter Min Typ Max Unit Test Conditions/Comments PHASE OFFSET IN ZERO DELAY REF refers to REFIN (REF1)/REFIN (REF2) Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode 560 1060 1310 ps When N delay and R delay are bypassed Phase Offset (REF-to-LVPECL Clock Output Pins) in Internal Zero Delay Mode −320 +50 +240 ps When N delay = Setting 110 and R delay is bypassed Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode 140 630 870 ps When N delay and R delay are bypassed Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode −460 −20 +200 ps When N delay = Setting 011 and R delay is bypassed NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider) @ 500 kHz PFD Frequency −165 dBc/Hz @ 1 MHz PFD Frequency −162 dBc/Hz @ 10 MHz PFD Frequency −152 dBc/Hz @ 50 MHz PFD Frequency −144 dBc/Hz PLL Figure of Merit (FOM) −222 dBc/Hz Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is an approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed-loop, the phase noise, as observed at the VCO output, is increased by 20 log(N); PLL figure of merit decreases with decreasing slew rate; see Figure 12 PLL DIGITAL LOCK DETECT WINDOW2 Signal available at LD, STATUS, and REFMON pins when selected by appropriate register settings; lock detect window settings can be varied by changing the CPRSET resistor Lock Threshold (Coincidence of Edges) Selected by 0x017[1:0] and 0x018[4] (This is the threshold to go from unlock to lock) Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns 0x017[1:0] = 00b, 01b,11b; 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b High Range (ABP 6.0 ns) 3.5 ns 0x017[1:0] = 10b; 0x018[4] = 0b Unlock Threshold (Hysteresis)2 Selected by 0x017[1:0] and 0x018[4](This is the threshold to go from lock to unlock) Low Range (ABP 1.3 ns, 2.9 ns) 7 ns 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 15 ns 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b High Range (ABP 6.0 ns) 11 ns 0x017[1:0] = 10b; 0x018[4] = 0b 1 The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. 2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

Rev. 0 | Page 7 of 84 CLOCK INPUTS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments CLOCK INPUTS (CLK, CLK) Differential input Input Frequency 01 2.4 GHz High frequency distribution (VCO divider) 0 1

1.6 GHz Distribution only (VCO divider bypassed); this is the

frequency range supported by the channel divider Input Sensitivity, Differential 150 mV p-p Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns Input Level, Differential 2 V p-p Larger voltage swings can turn on the protection diodes and can degrade jitter performance Input Common-Mode Voltage, VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling Input Common-Mode Range, VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLK ac-bypassed to RF ground Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF 1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM. CLOCK OUTPUTS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS_DRV − 2 V OUT0, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, OUT10, OUT11 Differential (OUT, OUT) Output Frequency, Maximum 2400 MHz Using direct to output; see Figure 21 (higher frequencies are possible, but amplitude will not meet the V OD specification); the maximum output frequency is limited by either the maximum VCO frequency or the frequency at the CLK inputs, depending on the AD9520 configuration Output High Voltage, VOH VS_DRV − 1.07 VS_DRV − 0.96 VS_DRV − 0.84 V Output Low Voltage, VOL VS_DRV − 1.95 VS_DRV − 1.79 VS_DRV − 1.64 V Output Differential Voltage, VOD 660 820 950 mV CMOS CLOCK OUTPUTS OUT0A, OUT0B, OUT1A, OUT1B, OUT2A, OUT2B, OUT3A, OUT3B, OUT4A, OUT4B, OUT5A, OUT5B, OUT6A, OUT6B, OUT7A, OUT7B, OUT8A, OUT8B, OUT9A, OUT9B, OUT10A, OUT10B, OUT11A, OUT11B Single-ended; termination = 10 pF Output Frequency 250 MHz See Figure 22 Output Voltage High, VOH VS − 0.1 V @ 1 mA load, VS_DRV = 3.3 V/2.5 V Output Voltage Low, VOL 0.1 V @ 1 mA load, VS_DRV = 3.3 V/2.5 V Output Voltage High, VOH 2.7 V @ 10 mA load, VS_DRV = 3.3 V Output Voltage Low, VOL 0.5 V @ 10 mA load, VS_DRV = 3.3 V Output Voltage High, VOH 1.8 V @ 10 mA load, VS_DRV = 2.5 V Output Voltage Low, VOL 0.6 V @ 10 mA load, VS_DRV = 2.5 V

Rev. 0 | Page 8 of 84 TIMING CHARACTERISTICS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT RISE/FALL TIMES Termination = 50 Ω to VS_DRV − 2 V Output Rise Time, tRP 130 170 ps 20% to 80%, measured differentially (rise/fall times are independent of VS and are valid for VS_DRV = 3.3 V and 2.5 V) Output Fall Time, tFP 130 170 ps 80% to 20%, measured differentially (rise/fall times are independent of VS and are valid for VS_DRV = 3.3 V and 2.5 V) PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT For All Divide Values 850 1050 1280 ps High frequency clock distribution configuration 800 970 1180 ps Clock distribution configuration Variation with Temperature 1.0 ps/°C OUTPUT SKEW, LVPECL OUTPUTS1 Termination = 50 Ω to VS_DRV − 2 V LVPECL Outputs That Share the Same Divider 5 16 ps VS_DRV = 3.3 V 5 20 ps VS_DRV = 2.5 V LVPECL Outputs on Different Dividers 5 45 ps VS_DRV = 3.3 V 5 60 ps VS_DRV = 2.5 V All LVPECL Outputs Across Multiple Parts 190 ps VS_DRV = 3.3 V and 2.5 V CMOS OUTPUT RISE/FALL TIMES Termination = open Output Rise Time, tRC 750 960 ps 20% to 80%; CLOAD = 10 pF; VS_DRV = 3.3 V Output Fall Time, tFC 715 890 ps 80% to 20%; CLOAD = 10 pF; VS_DRV = 3.3 V Output Rise Time, tRC 965 1280 ps 20% to 80%; CLOAD = 10 pF; VS_DRV = 2.5 V Output Fall Time, tFC 890 1100 ps 80% to 20%; CLOAD = 10 pF; VS_DRV = 2.5 V PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT Clock distribution configuration For All Divide Values 2.1 2.75 3.55 ns VS_DRV = 3.3 V 3.35 ns VS_DRV = 2.5 V Variation with Temperature 2 ps/°C VS_DRV = 3.3 V and 2.5 V OUTPUT SKEW, CMOS OUTPUTS1 CMOS Outputs That Share the Same Divider 7 85 ps VS_DRV = 3.3 V 10 105 ps VS_DRV = 2.5 V All CMOS Outputs on Different Dividers 10 240 ps VS_DRV = 3.3 V 10 285 ps VS_DRV = 2.5 V All CMOS Outputs Across Multiple Parts 600 ps VS_DRV = 3.3 V 620 ps VS_DRV = 2.5 V OUTPUT SKEW, LVPECL-TO-CMOS OUTPUT1 All settings identical; different logic type Outputs That Share the Same Divider 1.18 1.76 2.48 ns LVPECL to CMOS on same part Outputs That Are on Different Dividers 1.20 1.78 2.50 ns LVPECL to CMOS on same part 1 The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.

Rev. 0 | Page 10 of 84 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter Min Typ Max Unit Test Conditions/Comments CLK-TO-LVPECL ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, Output = 1 GHz Input slew rate > 1 V/ns Divider = 1 @ 10 Hz Offset −107 dBc/Hz @ 100 Hz Offset −117 dBc/Hz @ 1 kHz Offset −127 dBc/Hz @ 10 kHz Offset −135 dBc/Hz @ 100 kHz Offset −142 dBc/Hz @ 1 MHz Offset −145 dBc/Hz @ 10 MHz Offset −147 dBc/Hz @ 100 MHz Offset −150 dBc/Hz CLK = 1 GHz, Output = 200 MHz Input slew rate > 1 V/ns Divider = 5 @ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −143 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −156 dBc/Hz @ 1 MHz Offset −157 dBc/Hz >10 MHz Offset −157 dBc/Hz CLK-TO-CMOS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, Output = 250 MHz Input slew rate > 1 V/ns Divider = 4 @ 10 Hz Offset −107 dBc/Hz @ 100 Hz Offset −119 dBc/Hz @ 1 kHz Offset −125 dBc/Hz @ 10 kHz Offset −134 dBc/Hz @ 100 kHz Offset −144 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −154 dBc/Hz CLK = 1 GHz, Output = 50 MHz Input slew rate > 1 V/ns Divider = 20 @ 10 Hz Offset −126 dBc/Hz @ 100 Hz Offset −133 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −148 dBc/Hz @ 100 kHz Offset −157 dBc/Hz @ 1 MHz Offset −160 dBc/Hz >10 MHz Offset −163 dBc/Hz

Rev. 0 | Page 11 of 84 CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL ABSOLUTE PHASE NOISE Internal VCO; direct-to-LVPECL output and for loop bandwidths < 1 kHz VCO = 2.95 GHz; Output = 2.95 GHz @ 1 kHz Offset −46 dBc/Hz @ 10 kHz Offset −78 dBc/Hz @ 100 kHz Offset −104 dBc/Hz @ 1 MHz Offset −123 dBc/Hz @ 10 MHz Offset −139 dBc/Hz @ 40 MHz Offset −145 dBc/Hz VCO = 2.75 GHz; Output = 2.75 GHz @ 1 kHz Offset −49 dBc/Hz @ 10 kHz Offset −80 dBc/Hz @ 100 kHz Offset −106 dBc/Hz @ 1 MHz Offset −125 dBc/Hz @ 10 MHz Offset −140 dBc/Hz @ 40 MHz Offset −146 dBc/Hz VCO = 2.55 GHz; Output = 2.55 GHz @ 1 kHz Offset −51 dBc/Hz @ 10 kHz Offset −82 dBc/Hz @ 100 kHz Offset −108 dBc/Hz @ 1 MHz Offset −127 dBc/Hz @ 10 MHz Offset −140 dBc/Hz @ 40 MHz Offset −146 dBc/Hz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter Min Typ Max Unit Test Conditions/Comments setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R DIV = 1 VCO = 2.949 GHz; LVPECL = 245.76 MHz; PLL LBW = 63 kHz 176 fs rms Integration BW = 200 kHz to 10 MHz 351 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.703 GHz; LVPECL = 122.88 MHz; PLL LBW = 63 kHz 158 fs rms Integration BW = 200 kHz to 10 MHz 324 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.703 GHz; LVPECL = 61.44 MHz; PLL LBW = 63 kHz 177 fs rms Integration BW = 200 kHz to 10 MHz 330 fs rms Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9. Parameter Min Typ Max Unit Test Conditions/Comments setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 19.44 MHz; R DIV = 162 VCO = 2.799 GHz; LVPECL = 155.52 MHz; PLL LBW = 1.8 kHz 652 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.703 GHz; LVPECL = 122.88 MHz; PLL LBW = 2.1 kHz 607 fs rms Integration BW = 12 kHz to 20 MHz

Rev. 0 | Page 12 of 84 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 10. Parameter Min Typ Max Unit Test Conditions/Comments external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R DIV = 1 LVPECL = 245.76 MHz; PLL LBW = 125 Hz 54 fs rms Integration BW = 200 kHz to 5 MHz 77 fs rms Integration BW = 200 kHz to 10 MHz 109 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 122.88 MHz; PLL LBW = 125 Hz 79 fs rms Integration BW = 200 kHz to 5 MHz 114 fs rms Integration BW = 200 kHz to 10 MHz 163 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 61.44 MHz; PLL LBW = 125 Hz 124 fs rms Integration BW = 200 kHz to 5 MHz 176 fs rms Integration BW = 200 kHz to 10 MHz 259 fs rms Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; measured at rising edge of clock signal CLK = 622.08 MHz 46 fs rms Integration bandwidth = 12 kHz to 20 MHz Any LVPECL Output = 622.08 MHz Divide Ratio = 1 CLK = 622.08 MHz 64 fs rms Integration bandwidth = 12 kHz to 20 MHz Any LVPECL Output = 155.52 MHz Divide Ratio = 4 CLK = 1000 MHz 223 fs rms Calculated from SNR of ADC method Any LVPECL Output = 100 MHz Broadband jitter Divide Ratio = 10 CLK = 500 MHz 209 fs rms Calculated from SNR of ADC method Any LVPECL Output = 100 MHz Broadband jitter Divide Ratio = 5 CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO CLK = 200 MHz 325 fs rms Calculated from SNR of ADC method Any CMOS Output Pair = 100 MHz Broadband jitter Divide Ratio = 2

Rev. 0 | Page 13 of 84 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 12. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz; Channel Divider = 2; Duty-Cycle Correction = Off 230 fs rms Calculated from SNR of ADC method (broadband jitter) CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = On 215 fs rms Calculated from SNR of ADC method (broadband jitter) CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = Off 326 fs rms Calculated from SNR of ADC method (broadband jitter) CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz; Channel Divider = 8; Duty-Cycle Correction = Off 362 fs rms Calculated from SNR of ADC method (broadband jitter) SERIAL CONTROL PORT—SPI MODE Table 13. Parameter Min Typ Max Unit Test Conditions/Comments CS (INPUT) CS has an internal 30 kΩ pull-up resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 μA Input Logic 0 Current −110 μA The minus sign indicates that current is flowing out of the AD9520, which is due to the internal pull-up resistor Input Capacitance 2 pF SCLK (INPUT) IN SPI MODE SCLK has an internal 30 kΩ pull-down resistor in SPI mode, but not in I2C mode Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF SDIO (WHEN AN INPUT IN BIDIRECTIONAL MODE) Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 1 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V TIMING Clock Rate (SCLK, 1/tSCLK) 25 MHz Pulse Width High, tHIGH 16 ns Pulse Width Low, tLOW 16 ns SDIO to SCLK Setup, tDS 4 ns SCLK to SDIO Hold, tDH 0 ns SCLK to Valid SDIO and SDO, tDV 11 ns CS to SCLK Setup and Hold, tS, tC 2 ns CS Minimum Pulse Width High, tPWH 3 ns

Rev. 0 | Page 14 of 84 SERIAL CONTROL PORT—I²C MODE Table 14. Parameter Min Typ Max Unit Test Conditions/Comments SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage 0.7 × VS V Input Logic 0 Voltage 0.3 × VS V Input Current with an Input Voltage Between 0.1 × VS and 0.9 × VS −10 +10 μA Hysteresis of Schmitt Trigger Inputs 0.015 × VS V Pulse Width of Spikes That Must Be Suppressed by the Input Filter, tSPIKE 50 ns SDA (WHEN OUTPUTTING DATA) Output Logic 0 Voltage at 3 mA Sink Current 0.4 V Output Fall Time from VIHMIN to VILMAX with a Bus Capacitance from 10 pF to 400 pF 20 + 0.1 Cb 250 ns Cb = capacitance of one bus line in pF TIMING Note that all I2C timing values are referred to VIHMIN (0.3 × VS) and VILMAX levels (0.7 × VS) Clock Rate (SCL, fI2C) 400 kHz Bus Free Time Between a Stop and Start Condition, tIDLE 1.3 μs Setup Time for a Repeated Start Condition, tSET; STR 0.6 μs Hold Time (Repeated) Start Condition (After This Period, the First Clock Pulse Is Generated), tHLD; STR 0.6 μs Setup Time for Stop Condition, tSET; STP 0.6 μs Low Period of the SCL Clock, tLOW 1.3 μs High Period of the SCL Clock, tHIGH 0.6 μs SCL, SDA Rise Time, tRISE 20 + 0.1 Cb 300 ns SCL, SDA Fall Time, tFALL 20 + 0.1 Cb 300 ns Data Setup Time, tSET; DAT 120 ns This is a minor deviation from the original I²C specification of 100 ns minimum Data Hold Time, tHLD; DAT 140 880 ns This is a minor deviation from the original I²C specification of 0 ns minimum1 Capacitive Load for Each Bus Line, Cb 400 pF 1 According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL falling edge.

Rev. 0 | Page 15 of 84 PD, SYNC, AND RESET PINS Table 15. Parameter Min Typ Max Unit Test Conditions/Comments INPUT CHARACTERISTICS These pins each have a 30 kΩ internal pull-up resistor Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 1 μA Logic 0 Current −110 μA The minus sign indicates that current is flowing out of the AD9520, which is due to the internal pull-up resistor Capacitance 2 pF RESET TIMING Pulse Width Low 50 ns RESET Inactive to Start of Register Programming 100 ns SYNC TIMING Pulse Width Low 1.3 ns High speed clock is CLK input signal SERIAL PORT SETUP PINS: SP1, SP0 Table 16. Parameter Min Typ Max Unit Test Conditions/Comments SP1, SP0 These pins do not have internal pull-up/pull-down resistors Logic Level 0 0.25 × VS V VS is the voltage on the VS pin Logic Level ½ 0.4 × VS 0.65 × VS V User can float these pins to obtain Logic Level ½; if floating this pin, user should connect a capacitor to ground Logic Level 1 0.8 × VS V LD, STATUS, AND REFMON PINS Table 17. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT CHARACTERISTICS When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 53, 0x017, 0x01A, and 0x01B Output Voltage High, VOH 2.7 V Output Voltage Low, VOL 0.4 V MAXIMUM TOGGLE RATE 100 MHz Applies when mux is set to any divider or counter output, or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs can couple to output when any of these pins are toggling ANALOG LOCK DETECT Capacitance 3 pF On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor REF1, REF2, AND VCO FREQUENCY STATUS MONITOR Normal Range 1.02 MHz Frequency above which the monitor indicates the presence of the reference Extended Range 8 kHz Frequency above which the monitor indicates the presence of the reference LD PIN COMPARATOR Trip Point 1.6 V Hysteresis 260 mV

Rev. 0 | Page 16 of 84 POWER DISSIPATION Table 18. Parameter Min Typ Max Unit Test Conditions/Comments POWER DISSIPATION, CHIP Does not include power dissipated in external resistors; all LVPECL outputs terminated with 50 Ω to VCC − 2 V; all CMOS outputs have 10 pF capacitive loading; VS_DRV = 3.3 V Power-On Default 1.32 1.5 W No clock; no programming; default register values PLL Locked; One LVPECL Output Enabled 0.55 0.64 W fREF = 25 MHz; fOUT = 250 MHz; VCO = 2.75 GHz; VCO divider = 2; one LVPECL output and output divider enabled; zero delay off; ICP = 4.8 mA PLL Locked; One CMOS Output Enabled 0.52 0.62 W fREF = 25 MHz; fOUT = 62.5 MHz; VCO = 2.75 GHz; VCO divider = 2; one CMOS output and output divider enabled; zero delay off; ICP = 4.8 mA Distribution Only Mode; VCO Divider On; One LVPECL Output Enabled 0.39 0.46 W fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider = 2; one LVPECL output and output divider enabled; zero delay off Distribution Only Mode; VCO Divider Off; One LVPECL Output Enabled 0.36 0.42 W fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider bypassed; one LVPECL output and output divider enabled; zero delay off Maximum Power, Full Operation 1.5 1.7 W PLL on; internal VCO = 2750 MHz; VCO divider = 2; all channel dividers on; 12 LVPECL outputs @ 125 MHz; zero delay on PD Power-Down 60 80 mW PD pin pulled low; does not include power dissipated in termination resistors PD Power-Down, Maximum Sleep 24 33 mW PD pin pulled low; PLL power-down, 0x010[1:0] = 01b; power- down SYNC, 0x230[2] = 1b; power-down distribution reference, 0x230[1] = 1b VCP Supply 4 4.8 mW PLL operating; typical closed-loop configuration POWER DELTAS, INDIVIDUAL FUNCTIONS Power delta when a function is enabled/disabled VCO Divider On/Off 32 40 mW VCO divider not used REFIN (Differential) Off 25 30 mW Delta between reference input off and differential reference input mode REF1, REF2 (Single-Ended) On/Off 15 20 mW Delta between reference inputs off and one singled-ended reference enabled; double this number if both REF1 and REF2 are powered up VCO On/Off 67 104 mW Internal VCO disabled; CLK input selected PLL Dividers and Phase Detector On/Off 51 63 mW PLL off to PLL on, normal operation; no reference enabled LVPECL Channel 121 144 mW No LVPECL output on to one LVPECL output on; channel divider set to 1 LVPECL Driver 51 73 mW Second LVPECL output turned on, same channel CMOS Channel 145 180 mW No CMOS output on to one CMOS output on; channel divider set to 1; fOUT = 62.5 MHz and 10 pF of capacitive loading CMOS Driver On/Off 11 24 mW Additional CMOS outputs within the same channel turned on Channel Divider Enabled 40 57 mW Delta between divider bypassed (divide-by-1) and divide-by-2 to divide-by-32 Zero Delay Block On/Off 30 34 mW

Rev. 0 | Page 17 of 84 ABSOLUTE MAXIMUM RATINGS Table 19. Parameter or Pin With Respect to Rating VS GND −0.3 V to +3.6 V VCP , CP GND −0.3 V to +5.8 V VS_DRV GND −0.3 V to +3.6 V REFIN, REFIN GND −0.3 V to VS + 0.3 V RSET, LF , BYPASS GND −0.3 V to VS + 0.3 V CPRSET GND −0.3 V to VS + 0.3 V CLK, CLK GND −0.3 V to VS + 0.3 V CLK CLK −1.2 V to +1.2 V SCLK/SCL, SDIO/SDA, SDO, CS GND −0.3 V to VS + 0.3 V OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, OUT9, OUT9, OUT10, OUT10, OUT11, OUT11 GND −0.3 V to VS + 0.3 V SYNC, RESET, PD GND −0.3 V to VS + 0.3 V REFMON, STATUS, LD GND −0.3 V to VS + 0.3 V SP0, SP1, EEPROM GND −0.3 V to VS + 0.3 V Junction Temperature1 150°C Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C 1 See Table 20 for θJA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Thermal impedance measurements were taken on a JEDEC 51-5 2S2P test board in still air in accordance with JEDEC JESD51-2. See the Thermal Performance section for more details. Table 20. Package Type θJA Unit 64-Lead LFCSP (CP-64-4) 22 °C/W ESD CAUTION

1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.

Figure 5. Pin Configuration Table 21. Pin Function Descriptions I Power VS 3.3 V Power Pins. 2 O 3.3 V CMOS REFMON Reference Monitor (Output). This pin has multiple selectable outputs. 3 O 3.3 V CMOS LD Lock Detect (Output). This pin has multiple selectable outputs. connected to 3.3 V if PLL is not used. left unconnected if the PLL is not used. internal 30 kΩ pull-up resistor. 9 I Loop filter LF Loop Filter (Input). It connects internally to the VCO control voltage node. 10 O Loop filter BYPASS This pin is for bypassing the LDO to ground with a 220 nF capacitor.

14 I Differential

CLK Along with CLK, this pin is the differential input for the clock distribution section.

Rev. 0 | Page 19 of 84 Pin No. Input/ Output Pin Type Mnemonic Description 15 I 3.3 V CMOS CS Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor. 16 I 3.3 V CMOS SCLK/SCL Serial Control Port Clock Signal. This pin has an internal 30 kΩ pull-down resistor in SPI mode, but is high impedance in I²C mode. 17 I/O 3.3 V CMOS SDIO/SDA Serial Control Port Bidirectional Serial Data In/Out. 18 O 3.3 V CMOS SDO Serial Control Port Unidirectional Serial Data Out. 19, 59 I GND GND Ground Pins.

20 I Three-level

SP1 Select SPI or I²C as serial interface port and select I²C slave address in I²C mode. Three-level logic. This pin is internally biased for the open logic level.

21 I Three-level

SP0 Select SPI or I²C as serial interface port and select I²C slave address in I²C mode. Three-level logic. This pin is internally biased for the open logic level. 22 I 3.3 V CMOS EEPROM Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9520 to load the hard-coded default register values at power-up/reset. This pin has an internal 30 kΩ pull-down resistor. 23 I 3.3 V CMOS RESET Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor. 24 I 3.3 V CMOS PD Chip Power-Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.

25 O LVPECL or

OUT9 (OUT9A) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

26 O LVPECL or

OUT9 (OUT9B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output. 27, 35, 46, 54 I Power VS_DRV Output Driver Power Supply Pins. As a group, these pins can be set to either 2.5 V or 3.3 V. All four pins must be set to the same voltage.

28 O LVPECL or

(OUT10A) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

29 O LVPECL or

OUT10 (OUT10B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

30 O LVPECL or

(OUT11A) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

31 O LVPECL or

OUT11 (OUT11B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

33 O LVPECL or

OUT6 (OUT6A) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

34 O LVPECL or

(OUT6B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

36 O LVPECL or

OUT7 (OUT7A) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

37 O LVPECL or

OUT7 (OUT7B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

38 O LVPECL or

OUT8 (OUT8A) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

39 O LVPECL or

OUT8 (OUT8B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

42 O LVPECL or

OUT5 (OUT5B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

43 O LVPECL or

OUT5 (OUT5A) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

44 O LVPECL or

OUT4 (OUT4B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

45 O LVPECL or

OUT4 (OUT4A) Clock Output. This pin can be configured as one side of a differential LVPECL Output or as a single-ended CMOS output.

47 O LVPECL or

OUT3 (OUT3B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

Rev. 0 | Page 20 of 84 Pin No. Input/ Output Pin Type Mnemonic Description

48 O LVPECL or

OUT3 (OUT3A) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

50 O LVPECL or

(OUT2B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

51 O LVPECL or

OUT2 (OUT2A) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

52 O LVPECL or

(OUT1B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

53 O LVPECL or

OUT1 (OUT1A) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

55 O LVPECL or

OUT0 (OUT0B) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

56 O LVPECL or

OUT0 (OUT0A) Clock Output. This pin can be configured as one side of a differential LVPECL output or as a single-ended CMOS output.

58 O Current set

RSET Clock Distribution Current Set Resistor. Connect a 4.12 kΩ resistor from this pin to GND.

62 O Current set

CPRSET Charge Pump Current Set Resistor. Connect a 5.1 kΩ resistor from this pin to GND. This resistor can be omitted if the PLL is not used.

63 I Reference

(REF2) Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF2.

64 I Reference

REFIN (REF1) Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1. EP AD GND GND Exposed die pad must be connected to GND.

3 CHANNELS—6 LVPECL

3 CHANNELS—3 LVPECL

2 CHANNELS—2 LVPECL

1 CHANNEL—1 LVPECL

Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off),

3 CHANNELS—6 CMOS

3 CHANNELS—3 CMOS

2 CHANNELS—2 CMOS

1 CHANNEL—1 CMOS

Figure 7. Total Current vs. Frequency, CLK-to-Output (PLL Off), Figure 8. KVCO vs. VCO Frequency Figure 9. Charge Pump Characteristics @ VCP = 3.3 V Figure 10. Charge Pump Characteristics @ VCP = 5.0 V Figure 11. PFD Phase Noise Referred to PFD Input vs. PFD Frequency

Figure 24. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL @ 2750 MHz Figure 25. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL @ 2950 MHz Figure 26. Additive (Residual) Phase Noise, CLK-to-LVPECL @

245.76 MHz, Divide-by-1

Figure 27. Additive (Residual) Phase Noise, CLK-to-LVPECL @

200 MHz, Divide-by-5

Figure 28. Additive (Residual) Phase Noise, CLK-to-LVPECL @

1600 MHz, Divide-by-1

Figure 29. Additive (Residual) Phase Noise, CLK-to-CMOS @

50 MHz, Divide-by-20

Figure 30. Additive (Residual) Phase Noise, CLK-to-CMOS @

250 MHz, Divide-by-4

Figure 31. Phase Noise (Absolute) Clock Generation; Internal VCO @ Figure 32. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 2.799 GHz; Figure 33. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) Figure 34. PLL Loop Filter Used for Clock Generation Plot (see Figure 31) Figure 35. PLL Loop Filter Used for Clock Cleanup Plot (see Figure 32)

Rev. 0 | Page 26 of 84 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in decibels) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal-to-noise ratio (SNR) and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.

Rev. 0 | Page 27 of 84 DETAILED BLOCK DIAGRAM PROGRAMMABLE N DELAY REFIN CLK CLK REF1 REF2 BUF AMP AD9520 STATUS STATUS R DIVIDER CLOCK DOUBLER STATUS PROGRAMMABLE R DELAY REFERENCE SWITCHOVER REF_SEL CPRSET VCPVS GND RSET DISTRIBUTION REFERENCE REFMON CP VS_DRV STATUS LD P, P + 1 PRESCALER A/B COUNTERS N DIVIDER BYPASS LF LOW DROPOUT REGULATOR (LDO) PHASE FREQUENCY DETECTOR LOCK DETECT CHARGE PUMP PLL REFERENCE HOLD 0 1 DIVIDE BY 1, 2, 3, 4, 5, OR 6 PD SYNC REFIN RESET EEPROM DIGITAL LOGIC EEPROM DIVIDE BY

1 TO 32

Figure 36.

configuration without user intervention. VCO (0x018[0]) to ensure optimal performance. register settings shown in Table 22 should be used. Table 22. Settings When Using Internal VCO

Figure 37. Internal VCO and Clock Distribution (Mode 0)

VCO divider can be used. This is the only difference from Mode 2. allowed at the channel dividers). <1600 MHz, the register settings shown in Table 23 should be used. Table 23. Settings for Clock Distribution < 1600 MHz Table 24. Settings for Using Internal PLL with External VCO Table 25. Setting the PFD Polarity

Figure 38. Clock Distribution or External VCO < 1600 MHz (Mode 1)

down before reaching the channel dividers. PLL with an external VCO or VCXO with a frequency <2400 MHz. off. The external VCO/VCXO feeds directly into the prescaler. these registers at power-up or after a reset operation. Table 26. Default Register Settings for Clock Distribution Table 27. Settings When Using an External VCO Table 28. Setting the PFD Polarity

Figure 39. High Frequency Clock Distribution or External VCO > 1600 MHz (Mode 2)

Figure 40. PLL Functional Block The AD9520 includes an on-chip PLL with an on-chip VCO. usually consists of a small number of capacitors and resistors. establish the loop bandwidth and stability of the operating PLL. by the design of the external loop filter. the proper operation of the PLL. the AD9520 loop filter. It is available at www.analog.com/clocks. delay element that controls the width of the antibacklash pulse. spurs. The antibacklash pulse width is set by 0x017[1:0]. in the phase/frequency detector (PFD) parameter in Table 2.

lock the PLL loop), for pump-up, or for pump-down (test modes). by the CPRSET resistor, which is nominally 5.1 kΩ. priority in the design of the VCO. the VCO from variations in the power supply voltage level. Devices, Inc., making it insensitive to the type of capacitor used. Driving an external load from the BYPASS pin is not supported. current, the desired loop bandwidth, and the desired phase margin. according to the application requirements. Figure 41. Example of External Loop Filter for PLL frequency range for the reference inputs is specified in Table 2. allowing for easy ac coupling of input signals. enabled. All PLL reference inputs are off by default. specification for this voltage level can be found in Table 2. the driver to overcome the offset. CMOS level signal or an ac-coupled sine wave or square wave. selected, the single-ended inputs are powered down.

modes are available at all frequencies (see Table 2). When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32. counter, A = 0 is actually zero. because the frequency going to the A/B counter is too high. that these reset bits are not self-clearing. SYNC pin. This function is controlled by 0x019[7:6] (see ). SYNC pin reset is disabled by default. Both the R and N dividers feature a programmable delay cell. range is about 1 ns. See 0x019 in Table 53. Table 29. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N

distribution section. This input can receive up to 2.4 GHz. be ac-coupled via capacitors. Figure 45. CLK Equivalent Input Circuit to put the part into holdover, the distribution outputs turn off. Divider 1, Channel Divider 2, and Channel Divider 3, respectively. constant frequency even though there is no reference clock. pump into a high impedance state when the loop loses lock. frequency before the reference clock disappeared. holdover function must be enabled (0x01D[0]). operation is shown in Figure 46.

LOCK WAS PREVIOUSLY ACHIEVED.

5 TO 255 CYCLES (PROGRAMMING OF THE DLD

Figure 46. Flowchart of Automatic/Internal Holdover Mode Current Source Digital Lock Detect (CSDLD) section). impedance state as long as there is no reference clock present. difference for the loop to settle out.

holdover (CP high impedance).

• 0x018[6:5]—lock detect counter. This changes how many consecutive PFD cycles with edges inside the lock detect window are required for the DLD indicator to indicate lock. This impacts the time required before the LD pin can begin to charge as well as the delay from the end of a holdover event until the holdover function can be reengaged.
• 0x018[3]—disable digital lock detect. This bit must be set to a 0 to enable the DLD circuit. Internal/automatic holdover does not operate correctly without the DLD function enabled.
• 0x01A[5:0]—lock detect pin control. Set this to 000100b to put it in the current source lock detect mode if using the LD pin comparator. Load the LD pin with a capacitor of an appropriate value.
• 0x01D[3]—LD pin comparator enable. 1 = enable; 0 = disable. When disabled, the holdover function always senses the LD pin as high.
• 0x01D[1]—external holdover control.
• 0x01D[0]—holdover enable and ignore reference frequency status. If holdover is disabled, both external and automatic/ internal holdover are disabled. In the following example, automatic holdover is configured with
• Automatic reference switchover, prefer REF1.
• Digital lock detect: five PFD cycles, high range window.
• Automatic holdover using the LD pin comparator. The following registers are set (in addition to the normal PLL registers):
• 0x018[6:5] = 00b; lock detect counter = five cycles.
• 0x018[4] = 0b; digital lock detect window = high range.
• 0x018[3] = 1b; disable DLD normal operation.
• 0x01A[5:0] = 000100b; program LD pin control to current source lock detect mode.
• 0x01C[4] = 1b; enable automatic switchover.
• 0x01C[3] = 0b; prefer REF1.
• 0x01C[2:1] = 11b; enable REF1 and REF2 input buffers.
• 0x01D[3] = 1b; enable LD pin comparator.
• 0x01D[1] = 0b; disable external holdover mode and use automatic/internal holdover mode.
• 0x01D[0] = 1b; enable holdover. Frequency Status Monitors The AD9520 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency. A diagram showing their location in the PLL is shown in Figure 47. The PLL reference monitors have two threshold frequencies: normal and extended (see Table 17). The reference frequency monitor thresholds are selected in 0x01F. PROGRAMMABLE N DELAY CLK CLK REF1 REF2 BUF STATUS STATUS R DIVIDER CLOCK DOUBLER VCO STATUS PROGRAMMABLE R DELAY REFERENCE SWITCHOVER REF_SEL CPRSET VCPVS GND RSET DISTRIBUTION REFERENCE REFMON CP STATUS LD P, P + 1 PRESCALER A/B COUNTERS N DIVIDER BYPASS LF LOW DROPOUT REGULATOR (LDO) PHASE FREQUENCY DETECTOR LOCK DETECT CHARGE PUMP PLL REFERENCE HOLD 0 1 DIVIDE BY 1, 2, 3, 4, 5, OR 6 ZERO DELAY BLOCK FROM CHANNEL DIVIDER 0 VS_DRV REFIN OPTIONAL REFIN 07213-070

Figure 47. Reference and VCO Status Monitors

the user must calibrate the VCO manually. setup before executing update registers (0x232[0] = 1b). VCO calibration is finished by returning a logic true (that is, 1b).

1. Program the PLL registers to the proper values for the PLL

to static during VCO calibration.

1. For the initial setting of the registers after a power-up or

reset, initiate a VCO calibration by setting 0x018[0] = 1b. 0b, update registers and set 0x018[0] = 1b, update registers.

1. A SYNC operation is initiated internally, causing the
2. VCO is calibrated to the desired setting for the requested
3. Internally, the SYNC signal is released, allowing outputs to

which prevents unwanted frequencies from being produced. resume clocking before the PLL loop is completely settled. longer times for a calibration to be completed. fREFIN is the frequency of the REFIN signal. R is the value of the R counter. appropriate value for the calibration divider. Table 30. VCO Calibration Divider Values for Different automatically placed in SYNC until the calibration is finished. Therefore, this temporary loss of outputs must be expected.

• After changing any of the PLL R, P , B, and A divider settings, or after a change in the PLL reference clock frequency. This, in effect, means any time a PLL register or reference clock is changed such that a different VCO frequency results.
• Whenever system calibration is desired. The VCO is designed to operate properly over extremes of temperature even when it is first calibrated at the opposite extreme. However, a VCO calibration can be initiated at any time, if desired.

Figure 48. Zero Delay Function zero delay modes on the AD9520: internal and external. zero delay mode is shown in blue. of Channel Divider 0 with the phase/edge of the reference input. value in Register 0x01E[4:3]. input to achieve zero delay. routing for external zero delay mode is shown in red. External zero delay mode is selected by setting 0x01E[2:1] = 11. phase offset between the feedback clock and the reference input.

Figure 49. Simplified Diagram of the Three Clock Distribution Operation Modes output consists of the drivers that connect to the output pins. The clock outputs have either LVPECL or CMOS at the pins. by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers. maximum input frequency of the channel dividers to 1.6 GHz. frequencies than would be possible with only a simple post divider. be high for three divider input cycles and low for two cycles. Other combinations are also possible. division be set by M = N + 1. divider outputs can also be set to start high or to start low. and use the signal provided on the CLK/CLK pins. and sends the VCO signal directly to the drivers. Table 31 shows how the VCO, CLK, and VCO divider are selected. VCO without using the VCO divider. Table 31. Operation Modes OD specification in Table 4 at the highest frequencies.

section, even if no channel uses it. Table 32. Routing VCO Divider Input Directly to the Outputs frequency division for a channel is set. Table 33. Frequency Division

1 Bypass Disable Output static

1 The bypass VCO divider (0x1E1[0] = 1) is not the same as VCO divider = 1. and control registers (see Table 49 through Table 60). output dividers can be bypassed. the VCO calibration is complete. A channel divider drives each group of three LVPECL outputs. used for setting the division and other functions of these dividers. Table 34. Setting D each channel divider to divide by any integer from 1 to 32.

• The M and N values for the channel
• DCC enabled/disabled
• VCO divider enabled/bypassed
• The CLK input duty cycle (note that the internal VCO has a 50% duty cycle) The DCC function is enabled by default for each channel divider. However, the DCC function can be disabled individually for each channel divider by setting the disable divider DCC bit for that channel. Certain M and N values for a channel divider result in a non- 50% duty cycle. A non-50% duty cycle can also result with an even division, if M ≠ N. The duty-cycle correction function automatically corrects non-50% duty cycles at the channel divider output to 50% duty cycle. Duty-cycle correction requires the following channel divider conditions:
• An even division must be set as M = N
• An odd division must be set as M = N + 1 When not bypassed or corrected by the DCC function, the duty cycle of each channel divider output is the numerical value of (N + 1)/(N + M + 2) expressed as a percent. The duty cycle at the output of the channel divider for various configurations is shown in Table 35 to Table 38.

Table 35. Channel Divider Output Duty Cycle with VCO Table 36. Channel Divider Output Duty Cycle with VCO Table 37. Channel Divider Output Duty Cycle When the Note that the channel divider must be enabled when VCO divider = 1. Table 38. Channel Divider Output Duty Cycle When the

driver and approximately 1.5 ns for the CMOS driver. (0x232[0] = 1b) operation to take effect. and after synchronization, this allows for the setting of phase offsets. all of the drivers that belong to that channel divider. any SYNC operation by setting the ignore SYNC bit of the channel. outputs are not synchronized with those of the included channels.

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

Figure 51. SYNC Timing Pipeline Delay When VCO Divider Is Used—CLK or VCO Is Input

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

Figure 52. SYNC Timing Pipeline Delay When VCO Divider Is Not Used—CLK Input Only

Rev. 0 | Page 50 of 84 Soft Reset via the Serial Port The serial port control register allows for a soft reset by setting Bit 2 and Bit 5 in Register 0x000. When Bit 5 and Bit 2 are set, the chip enters a soft reset mode and restores the chip either to the setting stored in EEPROM (the EEPROM pin = 1) or to the on-chip setting (the EEPROM pin = 0), except for Register 0x000. These bits are self-clearing. During the internal reset, the outputs are held static. Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via the Serial Port The serial port control register allows the chip to be reset to settings in EEPROM when the EEPROM pin = 1 via 0xB02[1]. This bit is self-clearing. This bit does not have any effect when the EEPROM pin = 0. It takes ~20 ms for the outputs to begin toggling after the Soft_EEPROM register is cleared. POWER-DOWN MODES Chip Power-Down via PD The AD9520 can be put into a power-down condition by pulling the PD pin low. Power-down turns off most of the functions and currents inside the AD9520. The chip remains in this power-down state until PD is brought back to logic high. When taken out of power-down mode, the AD9520 returns to the settings programmed into its registers prior to the power- down, unless the registers are changed by new programming while the PD pin is held low. Powering down the chip shuts down the currents on the chip, except for the bias current necessary to maintain the LVPECL outputs in a safe shutdown mode. The LVPECL bias currents are needed to protect the LVPECL output circuitry from damage that can be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode. The AD9520 contains special circuitry to prevent runt pulses on the outputs when the chip is entering or exiting sleep mode. When the AD9520 is in a PD power-down, the chip is in the following state:

• The PLL is off (asynchronous power-down).
• The VCO is off.
• The CLK input buffer is off, but the CLK input dc bias circuit is on.
• In differential mode, the reference input buffer is off, and the dc bias circuit is still on.
• In singled-ended mode, the reference input buffer is off, but the dc bias circuit is off.
• All dividers are off.
• All CMOS outputs are tristated.
• All LVPECL outputs are in safe off mode.
• The serial control port is active, and the chip responds to commands. PLL Power-Down The PLL section of the AD9520 can be selectively powered down. There are two PLL power-down modes set by Register 0x010[1:0]: asynchronous and synchronous. In asynchronous power-down mode, the device powers down as soon as the registers are updated. In synchronous power-down mode, the PLL power-down is gated by the charge pump to prevent unwanted frequency jumps. The device goes into power- down on the occurrence of the next charge pump event after the registers are updated. Distribution Power-Down The distribution section can be powered down by writing 0x230[1] = 1b, which turns off the bias to the distribution section. If the LVPECL power-down mode is normal operation (0b), it is possible for a low impedance load on that LVPECL output to draw significant current during this power-down. If the LVPECL power-down mode is set to 1b, the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions. Individual Clock Output Power-Down Any of the clock distribution outputs can be powered down into safe power-down mode by individually writing to the appropriate registers. The register map details the individual power-down settings for each output. These settings are found in Register 0x0F0[0] to Register 0x0FD[0]. Individual Clock Channel Power-Down Any of the clock distribution channels can be powered down individually by writing to the appropriate registers. Powering down a clock channel is similar to powering down an individual driver, but it saves more power because the dividers are also powered down. Powering down a clock channel also automatically powers down the drivers connected to it. The register map details the individual power-down settings for each output channel. These settings are found in 0x192[2], 0x195[2], 0x198[2], and 0x19B[2].

Send byte format—the send byte protocol is used to set up the register address for subsequent commands. Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address. Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address. Read byte format—the combined format of the send byte and the receive byte. Figure 60. I²C Serial Port Timing Table 42. I2C Timing Definitions

SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. internally pulled down by a 30 kΩ resistor to ground. bidirectional I/O mode (0x000[7] = 0). mode (0x000[7]) as a separate output pin for reading back data. Figure 61. Serial Control Port long (16-bit) instruction mode is supported. boundary terminates the serial transfer and flushes the buffer. of the last byte to be transferred, thereby ending streaming mode. There are two parts to a communication cycle with the AD9520. the first byte of the data transfer. AD9520. Data bits are registered on the rising edge of SCLK. mode) is indicated by two bits (W1:W0) in the instruction byte. the CS pin on a nonbyte boundary resets the serial control port. the part. It does not matter what data is written to blank registers. instruction word, where N is 1 to 3 as determined by W1:W0.

upper four bits ([7:4]) must mirror the lower four bits ([3:0]). instruction mode, which is the default and only mode supported. port buffer area, or the data in the active registers (see Figure 62). Readback of the buffer or active registers is controlled by 0x004[0]. The default for the AD9520 is MSB first. control port and does not require that an update be executed. Figure 62. Relationship Between Serial Control Port Buffer Registers and address generator of the serial port increments for each byte. bytes of data indicated by Bits[W1:W0], see Table 43. Table 43. Byte Transfer Count Table 44. Streaming Mode (No Addresses Are Skipped) the range of the 0x232 registers used by the AD9520. bytes increment the address. Table 45. Serial Control Port, 16-Bit Instruction Word, MSB First

Figure 68. Serial Control Port Timing—Write Table 46. Serial Control Port Timing

Rev. 0 | Page 58 of 84 EEPROM OPERATIONS The AD9520 contains an internal EEPROM (nonvolatile memory). The EEPROM can be programmed by customers to create and store a user-defined register setting file when the power is off. This setting file can be used for power-up and chip reset as a default setting. The EEPROM size is 512 bytes. During the data transfer process, the write and read registers via the serial port are generally not available except for one readback register, STATUS_EEPROM. To determine the data transfer state through the serial port in SPI mode, users can read the value of STATUS_EEPROM (1 = in process, and 0 = completed). In I2C mode, the user can address the AD9520 slave port with the external I2C master (send an address byte to the AD9520). If the AD9520 responds with a no acknowledge bit, the data transfer process is not done. If the AD9520 responds with an acknowledge bit, the data transfer process is completed. The user can monitor the STATUS_EEPROM register or program the STATUS pin to monitor the status of the data transfer. WRITING TO THE EEPROM The EEPROM cannot be programmed directly through the serial port interface. To program the EEPROM and store a register setting file, do the following: 1. Program the AD9520 registers to the desired circuit state. If the user wants the PLL to lock automatically after power-up, the VCO calibration now bit (0x018[0]) must be set to 1. This allows VCO calibration to start automatically after register loading. Note that a valid input reference signal must be present during VCO calibration. 2. Program the EEPROM buffer registers, if necessary (see the Programming the EEPROM Buffer Segment section). This is only necessary if users want to use the EEPROM to control the default setting of some (but not all) of the AD9520 registers, or if they want to control the register setting update sequence during power-up or chip reset. 3. Set the enable EEPROM write bit (0xB02[0]) to 1 to enable the EEPROM. 4. Set the REG2EEPROM bit (0xB03[0]) to 1. 5. Set the IO_UPDATE bit (0x232[0]) to 1, which starts the process of writing data into the EEPROM to create the EEPROM setting file. This enables the AD9520 EEPROM controller to transfer the current register values, as well as the memory address and instruction bytes from the EEPROM buffer segment into the EEPROM. After the write process is completed, the internal controller sets 0xB03[0] (REG2EEPROM) back to 0. The readback register STATUS_EEPROM (0xB00[0]) is used to indicate the data transfer status between the EEPROM and the control registers (0 = done/inactive; 1 = in process/ active). At the beginning of the data transfer, STATUS_EEPROM is set to 1 by the EEPROM controller and cleared to 0 at the end of the data transfer. The user can access STATUS_EEPROM through the STATUS pin when the STATUS pin is programmed to monitor STATUS_EEPROM. Alternatively, the user can monitor the STATUS_EEPROM bit. 6. After the data transfer process is done (0xB00[0] = 0), set the enable EEPROM write register (0xB02[0]) to 0 to disable writing to the EEPROM. T o verify that the data transfer has completed correctly, the user can verify that 0xB01[0] = 0. A value of 1 in this register indicates a data transfer error. READING FROM THE EEPROM The following reset-related events can start the process of restoring the settings stored in EEPROM to control registers. When the EEPROM pin is set high, do any of the following: 1. Power up the AD9520 2. Perform a hardware chip reset by pulling the RESET pin low, and then releasing RESET 3. Set the self-clearing soft reset bit (0x000[5]) to 1 When the EEPROM pin is set low, set the self-clearing Soft_EEPROM bit (0xB02[1]) to 1. The AD9520 then starts to read the EEPROM and loads the values into the AD9520. If the EEPROM pin is low during reset or power-up, the EEPROM is not active, and the AD9520 default values are loaded instead. Note that when using the EEPROM to automatically load the AD9520 register values and lock the PLL, the VCO calibration now bit (0x018[0]) must be set to 1 when the register values are written to the EEPROM. This allows VCO calibration to start automatically after register loading. A valid input reference signal must be present during VCO calibration. T o verify that the data transfer has completed correctly, the user can verify that 0xB01[0] = 0. A value of 1 in this register indicates a data transfer error.

Rev. 0 | Page 59 of 84 PROGRAMMING THE EEPROM BUFFER SEGMENT The EEPROM buffer segment is a register space on the AD9520 that allows the user to specify which groups of registers are stored to the EEPROM during EEPROM programming. Normally, this segment does not need to be programmed by the user. Instead, the default power-up values for the EEPROM buffer segment allow the user to store all of the AD9520 register values from Register 0x000 to Register 0x231 to the EEPROM. For example, a user wants to load only the output driver settings from the EEPROM without disturbing the PLL register settings currently stored in the AD9520. The user can alter the EEPROM buffer segment to include only the registers that apply to the output drivers and exclude the registers that apply to the PLL configuration. There are two parts to the EEPROM buffer segment: register section definition groups and operational codes. Each register section definition group contains the starting address and number of bytes to be written to the EEPROM. If the AD9520 register map were continuous from Address 0x000 to Address 0x232, only one register section definition group would consist of a starting address of 0x000 and a length of 563 bytes. However, this is not the case. The AD9520 register map is noncontiguous, and the EEPROM is only 512 bytes long. Therefore, the register section definition group tells the EEPROM controller how the AD9520 register map is segmented. There are three operational codes: IO_UPDATE, end-of-data, and pseudo-end-of-data. It is important that the EEPROM buffer segment always have either an end-of-data or a pseudo-end-of-data operational code and that an IO_UPDATE operation code appear at least once before the end-of-data op code. Register Section Definition Group The register section definition group is used to define a continuous register section for the EEPROM profile. It consists of three bytes. The first byte defines how many continuous register bytes are in this group. If the user puts 0x000 in the first byte, it means that there is only one byte in this group. If the user puts 0x001, it means that there are two bytes in this group. The maximum number of registers in one group is 128. The next two bytes are the low byte and high byte of the memory address (16-bit) of the first register in this group. IO_UPDATE (Operational Code 0x80) The EEPROM controller uses this operational code to generate an IO_UPDATE signal to update the active control register bank from the buffer register bank during the download process. At a minimum, there should be at least one IO_UPDATE operational code after the end of the final register section definition group. The reason this is needed is so that at least one IO_UPDATE occurs after all of the AD9520 registers are loaded when the EEPROM is read. If this operational code is absent during a write to the EEPROM, the register values loaded from the EEPROM are not transferred to the active register space, and these values do not take effect after they are loaded from the EEPROM to the AD9520. End-of-Data (Operational Code 0xFF) The EEPROM controller uses this operational code to terminate the data transfer process between EEPROM and the control register during the upload and download process. The last item appearing in the EEPROM buffer segment should be either this operational code or the pseudo-end-of-data operational code. Pseudo-End-of-Data (Operational Code 0xFE) The AD9520 EEPROM buffer segment has 23 bytes that can contain up to seven register section definition groups. If users want to define more than seven register section definition groups, the pseudo-end-of-data operational code can be used. During the upload process, when the EEPROM controller receives the pseudo-end-of-data operational code, it halts the data transfer process, clears the REG2EEPROM bit, and enables the AD9520 serial port. Users can then program the EEPROM buffer segment again and reinitiate the data transfer process by setting the REG2EEPROM bit (0xB03) to 1 and the IO_UPDATE register (0x232) to 1. The internal I2C master then begins writing to the EEPROM starting from the EEPROM address held from the last writing. This sequence enables more discrete instructions to be written to the EEPROM than would otherwise be possible due to the limited size of the EEPROM buffer segment. It also permits the user to write the same register multiple times with a different value each time.

Table 47. Example of EEPROM Buffer Segment

Table 48. Thermal Parameters for 64-Lead LFCSP that TCASE is not exceeded, an airflow source can be used. TJ is the junction temperature (°C). ΨJT is the value from Table 48. where TA is the ambient temperature (°C). design considerations when an external heat sink is required.

marked unused also has no effect. Table 49. Register Map Overview

000 Serial port config

001 Unused N/A

002 Reserved N/A

003 Reserved N/A

004 Readback

005 EEPROM

006 EEPROM customer version ID (MSB) 00

010 PFD charge

011 R counter 14-bit R counter, Bits[7:0] (LSB) 01

012 Unused 14-bit R counter, Bits[13:8] (MSB) 00

013 A counter Unused 6-bit A counter 00

014 B counter 13-bit B counter, Bits[7:0] (LSB) 03

015 Unused 13-bit B counter, Bits[12:8] (MSB) 00

016 PLL_CTRL_1 Set CP pin

017 PLL_CTRL_2 STATUS pin control Antibacklash pulse width 00

018 PLL_CTRL_3 Enable CMOS

019 PLL_CTRL_4 R, A, B counters

Rev. 0 | Page 63 of 84 Addr (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) 01E PLL_CTRL_9 Unused External zero delay feedback channel divider select Enable external zero delay Enable zero delay Unused 00 01F PLL_Readback (read-only) Unused VCO cal finished Holdover active REF2 selected VCO freq > threshold REF2 freq > threshold REF1 freq > threshold Digital lock detect N/A Output Driver Control 0F0 OUT0 control OUT0 format OUT0 CMOS configuration OUT0 polarity OUT0 LVPECL differential voltage OUT0 LVPECL power-down 0F1 OUT1 control OUT1 format OUT1 CMOS configuration OUT1 polarity OUT1 LVPECL differential voltage OUT1 LVPECL power-down 0F2 OUT2 control OUT2 format OUT2 CMOS configuration OUT2 polarity OUT2 LVPECL differential voltage OUT2 LVPECL power-down 0F3 OUT3 control OUT3 format OUT3 CMOS configuration OUT3 polarity OUT3 LVPECL differential voltage OUT3 LVPECL power-down 0F4 OUT4 control OUT4 format OUT4 CMOS configuration OUT4 polarity OUT4 LVPECL differential voltage OUT4 LVPECL power-down 0F5 OUT5 control OUT5 format OUT5 CMOS configuration OUT5 polarity OUT5 LVPECL differential voltage OUT5 LVPECL power-down 0F6 OUT6 control OUT6 format OUT6 CMOS configuration OUT6 polarity OUT6 LVPECL differential voltage OUT6 LVPECL power-down 0F7 OUT7 control OUT7 format OUT7 CMOS configuration OUT7 polarity OUT7 LVPECL differential voltage OUT7 LVEPCL power-down 0F8 OUT8 control OUT8 format OUT8 CMOS configuration OUT8 polarity OUT8 LVPECL differential voltage OUT8 LVPECL power-down 0F9 OUT9 control OUT9 format OUT9 CMOS configuration OUT9 polarity OUT9 LVPECL differential voltage OUT9 LVPECL power-down 0FA OUT10 control OUT10 format OUT10 CMOS configuration OUT10 polarity OUT10 LVPECL differential voltage OUT10 LVPECL power-down 0FB OUT11 control OUT11 format OUT11 CMOS configuration OUT11 polarity OUT11 LVPECL differential voltage OUT11 LVPECL power-down 0FC Enable output on CSDLD CSDLD En Out 7 CSDLD En OUT6 CSDLD En OUT5 CSDLD En OUT4 CSDLD En OUT3 CSDLD En OUT2 CSDLD En OUT1 CSDLD En OUT0 0FD Enable output on CSDLD Unused Unused Unused Unused CSDLD En OUT11 CSDLD En OUT10 CSDLD En OUT9 CSDLD En OUT8 0FE to 18F Unused 00 LVPECL Channel Dividers

190 Divider 0 (PECL) Divider 0 low cycles Divider 0 high cycles 77

191 Divider 0

192 Unused Unused Channel 0

Rev. 0 | Page 64 of 84 Addr (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex)

193 Divider 1 (PECL) Divider 1 low cycles Divider 1 high cycles 33

194 Divider 1

195 Unused Unused Channel 1

196 Divider 2 (PECL) Divider 2 low cycles Divider 2 high cycles 11

197 Divider 2

198 Unused Unused Channel 2

199 Divider 3 (PECL) Divider 3 low cycles Divider 3 high cycles 00

19B Unused Unused Channel 3 power- down Channel 3 direct-to- output Disable Divider 3 DCC 19C to 1DF Unused 00 VCO Divider and CLK Input 1E0 VCO divider Unused Unused VCO divider 00 1E1 Input CLKs Unused Unused (default = 1) Power - down clock input section Power- down VCO clock interface Power- down VCO and CLK Select VCO or CLK Bypass VCO divider 1E2 to 22A Unused 00 System

230 Power-down

231 Unused Unused 00

232 IO_UPDATE Unused IO_UPDATE

(self-clearing) 233 to 9FF Unused 00 EEPROM Buffer Segment A00 EEPROM Buffer Segment Register 1

0 EEPROM Buffer Segment Register 1 (default: number of bytes for Group 1) 00

EEPROM Buffer Segment Register 2 (default: Bits[15:8] of starting register address for Group 1) 00 A02 EEPROM Buffer Segment Register 3 EEPROM Buffer Segment Register 3 (default: Bits[7:0] of starting register address for Group 1) 00 A03 EEPROM Buffer Segment Register 4

0 EEPROM Buffer Segment Register 4 (default: number of bytes for Group 2) 02

EEPROM Buffer Segment Register 5 (default: Bits[15:8] of starting register address for Group 2) 00

Rev. 0 | Page 65 of 84 Addr (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) A05 EEPROM Buffer Segment Register 6 EEPROM Buffer Segment Register 6 (default: Bits[7:0] of starting register address for Group 2) 04 A06 EEPROM Buffer Segment Register 7

0 EEPROM Buffer Segment Register 7 (default: number of bytes for Group 3) 0E

EEPROM Buffer Segment Register 8 (default: Bits[15:8] of starting register address for Group 3) 00 A08 EEPROM Buffer Segment Register 9 EEPROM Buffer Segment Register 9 (default: Bits[7:0] of starting register address for Group 3) 10 A09 EEPROM Buffer Segment Register 10

0 EEPROM Buffer Segment Register 10 (default: number of bytes for Group 4) 0E

EEPROM Buffer Segment Register 11 (default: Bits[15:8] of starting register address for Group 4) 00 A0B EEPROM Buffer Segment Register 12 EEPROM Buffer Segment Register 12 (default: Bits[7:0] of starting register address for Group 4) F0 A0C EEPROM Buffer Segment Register 13

0 EEPROM Buffer Segment Register 13 (default: number of bytes for Group 5) 0B

EEPROM Buffer Segment Register 14 (default: Bits[15:8] of starting register address for Group 5) 01 A0E EEPROM Buffer Segment Register 15 EEPROM Buffer Segment Register 15 (default: Bits[7:0] of starting register address for Group 5) 90 A0F EEPROM Buffer Segment Register 16

0 EEPROM Buffer Segment Register 16 (default: number of bytes for Group 6) 01

EEPROM Buffer Segment Register 17 (default: Bits[15:8] of starting register address for Group 6) 01 A11 EEPROM Buffer Segment Register 18 EEPROM Buffer Segment Register 18 (default: Bits[7:0] of starting register address for Group 6) E0 A12 EEPROM Buffer Segment Register 19

0 EEPROM Buffer Segment Register 19 (default: number of bytes for Group 7) 01

EEPROM Buffer Segment Register 20 (default: Bits[15:8] of starting register address for Group 7) 02 A14 EEPROM Buffer Segment Register 21 EEPROM Buffer Segment Register 21 (default: Bits[7:0] of starting register address for Group 7) 30 A15 EEPROM Buffer Segment Register 22 EEPROM Buffer Segment Register 22 (default: IO_UPDATE from EEPROM) 80 A16 EEPROM Buffer Segment Register 23 EEPROM Buffer Segment Register 23 (default: end of data) FF A17 to AFF Unused 00

Rev. 0 | Page 66 of 84 Addr (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) EEPROM Control B00 EEPROM status (read-only) Unused Unused STATUS_ EEPROM B01 EEPROM error checking (read-only) Unused Unused EEPROM data error B02 EEPROM Control 1 Unused Soft_EEPROM (self-clearing) Enable EEPROM write B03 EEPROM Control 2 Unused Unused REG2EEPROM (self-clearing)

[5:2] refers to the range of bits from Bit 5 through Bit 2. Table 50. SPI Mode Serial Port Configuration 000 [7] SDO active Selects unidirectional or bidirectional data transfer mode. [7] = 0; SDIO pin used for write and read; SDO is high impedance (default). [7] = 1; SDO used for read; SDIO used for write; unidirectional mode. [6] = 0; data-oriented MSB first; addressing decrements (default). [6] = 1; data-oriented LSB first; addressing increments. 000 [5] Soft reset Soft reset. [5] = 1 (self-clearing). Soft reset; restores default values to internal registers. 004 [0] Readback active registers Select register bank used for a readback. [0] = 0; read back buffer registers (default). [0] = 1; read back active registers. Table 51. I 000 [5] Soft reset Soft reset. [5] = 1 (self-clearing). Soft reset; restores default values to internal registers. 004 [0] Readback active registers Select register bank used for a readback. [0] = 0; read back buffer registers (default). [0] = 1; read back active registers. Table 52. EEPROM ID EEPROM. It does not affect AD9520 operation in any way (default: 0x00). EEPROM. It does not affect AD9520 operation in any way (default: 0x00).

Table 53. PLL 010 [7] PFD polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires positive polarity, [7] = 0. [7] = 0; positive (higher control voltage produces higher frequency) (default). [7] = 1; negative (higher control voltage produces lower frequency). 010 [6:4] CP current Charge pump current (with CPRSET = 5.1 kΩ). 010 [3:2] CP mode Charge pump operating mode. 0 1 Force source current (pump up). 1 0 Force sink current (pump down). 1 1 Normal operation (default). 0 0 Normal operation; this mode must be selected to use the PLL. 0 1 Asynchronous power-down (default). 14 bits long. The lower eight bits are in this register (default: 0x01). 14 bits long. The upper six bits are in this register (default: 0x00). 013 [5:0] 6-bit A counter A counter (part of N divider). The N divider is also called the feedback divider (default: 0x00). B counter (part of N divider)—lower eight bits. The N divider is also called the feedback divider (default: 0x03). B counter (part of N divider)—upper five bits. The N divider is also called the feedback divider (default: 0x00). Sets the CP pin to one-half of the VCP supply voltage. [7] = 0; CP normal operation (default). 016 [6] Reset R counter Reset R counter (R divider). [6] = 1; hold R counter in reset. Reset A and B counters (part of N divider). [5] = 1; hold A and B counters in reset. [4] = 1; hold R, A, and B counters in reset.

Rev. 0 | Page 69 of 84 Reg. Addr (Hex) Bit(s) Name Description 016 [3] B counter bypass B counter bypass. This is only valid when operating the prescaler in FD mode. [3] = 0; normal (default). [3] = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider. 016 [2:0] Prescaler P Prescaler: DM = dual modulus and FD = fixed divide. The Prescaler P is part of the feedback divider. [2] [1] [0] Mode Prescaler 0 0 0 FD Divide-by-1. 0 0 1 FD Divide-by-2. 0 1 0 DM Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0. 0 1 1 DM Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0. 1 0 0 DM Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0. 1 0 1 DM Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0. 1 1 0 DM Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0 (default). 1 1 1 FD Divide-by-3. 017 [7:2] STATUS pin control Selects the signal that appears at the STATUS pin. 0x01D[7] must be 0 to reprogram the STATUS pin. Level or Dynamic Signal Signal at STATUS Pin 0 0 0 0 0 0 LVL Ground, dc (default). 0 0 0 0 0 1 DYN N divider output (after the delay). 0 0 0 0 1 0 DYN R divider output (after the delay). 0 0 0 0 1 1 DYN A divider output. 0 0 0 1 0 0 DYN Prescaler output. 0 0 0 1 0 1 DYN PFD up pulse. 0 0 0 1 1 0 DYN PFD down pulse. 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified. The selections that follow are the same as for REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status REF1 frequency (active high). 1 0 1 0 0 0 LVL Status REF2 frequency (active high). 1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of VCO frequency (active high). 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL DLD; active high. 1 0 1 1 1 0 LVL Holdover active (active high). 1 0 1 1 1 1 LVL N/A internal holdover comparator output (active high). 1 1 0 0 0 0 LVL VS (PLL power supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode).

Rev. 0 | Page 70 of 84 Reg. Addr (Hex) Bit(s) Name Description Level or Dynamic Signal Signal at STATUS Pin 1 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 1 0 1 0 LVL (DLD) AND (Status of selected reference) AND (status of VCO). 1 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 1 0 1 LVL DLD (active low). 1 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 1 LVL LD pin comparator output (active low). 017 [1:0] Antibacklash pulse width [1] [0] Antibacklash Pulse Width (ns) 0 0 2.9 (default) 0 1 1.3 1 0 6.0 1 1 2.9 018 [7] Enable CMOS reference input dc offset Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost. [7] = 0; disable dc offset (default). [7] = 1; enable dc offset. 018 [6:5] Lock detect counter Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked condition. [6] [5] PFD Cycles to Determine Lock 0 0 5 (default) 0 1 16 1 0 64 1 1 255 018 [4] Digital lock detect window If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold. [4] = 0; high range (default). [4] = 1; low range. 018 [3] Disable digital lock detect Digital lock detect operation. [3] = 0; normal lock detect operation (default). [3] = 1; disable lock detect. 018 [2:1] VCO calibration divider VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock (see the VCO Calibration section for the recommended setting of the VCO calibration divider based on the PFD rate). [2] [1] VCO Calibration Clock Divider 0 0 2 0 1 4 1 0 8 1 1 16 (default)

Rev. 0 | Page 71 of 84 Reg. Addr (Hex) Bit(s) Name Description 018 [0] VCO calibration now Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The sequence to initiate a calibration follows: program to 0, followed by an IO_UPDATE bit (Register 0x232[0]); then program to 1, followed by another IO_UPDATE bit (Register 0x232[0]). This sequence gives complete control over when the VCO calibration occurs relative to the programming of other registers that can impact the calibration (default = 0). Note that the VCO divider (Register 0x1E0[2:0]) must not be static during VCO calibration. 019 [7:6] R, A, B counters SYNC pin reset [7] [6] Action 0 0 Do nothing on SYNC (default). 0 1 Asynchronous reset. 1 0 Synchronous reset. 1 1 Do nothing on SYNC. 019 [5:3] R path delay R path delay, see Table 2 (default: 0x0). 019 [2:0] N path delay N path delay, see Table 2 (default: 0x0). 01A [7] Enable STATUS pin divider Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the R and N dividers. [7] = 0; divide-by-4 disabled on STATUS pin (default). [7] = 1; divide-by-4 enabled on STATUS pin. 01A [6] Ref freq monitor threshold Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO frequency monitor’s detection threshold (see Table 17, REF1, REF2, and VCO frequency status monitor parameter). [6] = 0; frequency valid if frequency is above 1.02 MHz (default). [6] = 1; frequency valid if frequency is above 6 kHz. 01A [5:0] LD pin control Selects the signal that is connected to the LD pin. Level or Dynamic Signal Signal at LD Pin 0 0 0 0 0 0 LVL Digital lock detect (high = lock; low = unlock, default). 0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 1 HIZ Tristate (high-Z) LD pin. 0 0 0 1 0 0 CUR Current source lock detect (110 μA when DLD is true). 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified. The selections that follow are the same as for REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status REF1 frequency (active high). 1 0 1 0 0 0 LVL Status REF2 frequency (active high). 1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of VCO frequency (active high). 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL DLD; active high. 1 0 1 1 1 0 LVL Holdover active (active high). 1 0 1 1 1 1 LVL N/A, do not use. 1 1 0 0 0 0 LVL VS (PLL supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode).

Rev. 0 | Page 72 of 84 Reg. Addr (Hex) Bit(s) Name Description Level or Dynamic Signal Signal at LD Pin 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 1 0 1 0 LVL (DLD) AND (Status of selected reference) AND (status of VCO). 1 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 1 0 1 LVL DLD; active low. 1 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 1 LVL N/A, do not use. 01B [7] Enable VCO frequency monitor Enables or disables VCO frequency monitor. [7] = 0; disable VCO frequency monitor (default). [7] = 1; enable VCO frequency monitor. 01B [6] Enable REF2 (REFIN frequency monitor Enables or disables REF2 frequency monitor. [6] = 0; disable REF2 frequency monitor (default). [6] = 1; enable REF2 frequency monitor. 01B [5] Enable REF1 (REFIN) frequency monitor REF1 (REFIN) frequency monitor enabled; this is for both REF1 (single-ended) and REFIN (differential) inputs (as selected by differential reference mode). [5] = 0; disable REF1 (REFIN) frequency monitor (default). [5] = 1; enable REF1 (REFIN) frequency monitor. 01B [4:0] REFMON pin control Selects the signal that is connected to the REFMON pin. Level or Dynamic Signal Signal at REFMON Pin 0 0 0 0 0 LVL Ground, dc (default). 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 0 0 1 1 1 LVL Status REF1 frequency (active high). 0 1 0 0 0 LVL Status REF2 frequency (active high). 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 0 1 0 1 1 LVL Status of VCO frequency (active high). 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 0 1 1 0 1 LVL DLD; active low.

Rev. 0 | Page 73 of 84 Reg. Addr (Hex) Bit(s) Name Description Level or Dynamic Signal Signal at REFMON Pin 0 1 1 1 0 LVL Holdover active (active high). 0 1 1 1 1 LVL N/A, do not use. 1 0 0 0 0 LVL VS (PLL supply). 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 0 1 LVL DLD; active low. 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 LVL N/A, do not use. 01C [7] Disable switchover deglitch Disables or enables the switchover deglitch circuit. [7] = 0; enable switchover deglitch circuit (default). [7] = 1; disable switchover deglitch circuit. 01C [6] Select REF2 If Register 0x01C[5] = 0, selects reference for PLL when in manual; register selected reference control. [6] = 0; select REF1 (default). [6] = 1; select REF2. 01C [5] Use REF_SEL pin If Register 0x01C[4] = 0 (manual), sets method of PLL reference selection. [5] = 0; use Register 0x01C[6] (default). [5] = 1; use REF_SEL pin. 01C [4] Enable automatic reference switchover Automatic or manual reference switchover. Single-ended reference mode must be selected by Register 0x01C[0] = 0. [4] = 0; manual reference switchover (default). [4] = 1; automatic reference switchover. Setting this bit also powers on REF1 and REF2, and overrides the settings in Register 0x01C[2:1]. 01C [3] Stay on REF2 Stays on REF2 after switchover. [3] = 0; return to REF1 automatically when REF1 status is good again (default). [3] = 1; stay on REF2 after switchover. Do not automatically return to REF1. 01C [2] Enable REF2 This bit turns the REF2 power on. This bit is overridden when automatic reference switchover is enabled. [2] = 0; REF2 power off (default). [2] = 1; REF2 power on. 01C [1] Enable REF1 This bit turns the REF1 power on. This bit is overridden when automatic reference switchover is enabled. [1] = 0; REF1 power off (default). [1] = 1; REF1 power on. 01C [0] Enable differential reference Selects the PLL reference mode, differential or single-ended. Register 0x01C[2:1] should be cleared when this bit is set. [0] = 0; single-ended reference mode (default). [0] = 1; differential reference mode.

Rev. 0 | Page 74 of 84 Reg. Addr (Hex) Bit(s) Name Description 01D [7] Enable Status_EEPROM at STATUS pin Enables the Status_EEPROM signal at the STATUS pin. [7] = 0; the STATUS pin is controlled by 0x017[7:2] selection. [7] = 1; select Status_EEPROM signal at STATUS pin. This bit overrides 0x017[7:2] (default). 01D [6] Enable XTAL OSC Enables the maintaining amplifier needed by a crystal oscillator at the PLL reference input. [6] = 0; crystal oscillator maintaining amplifier disabled (default). [6] = 1; crystal oscillator maintaining amplifier enabled. 01D [5] Enable clock doubler Enable PLL reference input clock doubler. [5] = 0; doubler disabled (default). [5] = 1; doubler enabled. 01D [4] Disable PLL status register Disables the PLL status register readback. [4] = 0; PLL status register enabled (default). [4] = 1; PLL status register disabled. If this bit is set, Register 01F is not automatically updated. 01D [3] Enable LD pin comparator Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode. When the AD9520 is in internal (automatic) holdover mode, this enables the use of the voltage on the LD pin to determine if the PLL was previously in a locked state (see Figure 46). Otherwise, this can be used with the REFMON and STATUS pins to monitor the voltage on this pin. [3] = 0; disable LD pin comparator and ignore the LD pin voltage; internal/automatic holdover controller treats this pin as true (high, default). [3] = 1; enable LD pin comparator (use LD pin voltage to determine if the PLL was previously locked). 01D [1] Enable external holdover Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.) [1] = 0; automatic holdover mode, holdover controlled by automatic holdover circuit (default). [1] = 1; external holdover mode, holdover controlled by SYNC pin. 01D [0] Enable holdover Enables the internally controlled holdover function. [0] = 0; holdover disabled (default). [0] = 1; holdover enabled. 01E [4:3] External zero delay feedback channel divider select [4] [3] Select Which Channel Divider to Use in the External Zero-Delay Path 0 0 Select Channel Divider 0 (default). 0 1 Select Channel Divider 1. 1 0 Select Channel Divider 2. 1 1 Select Channel Divider 3. 01E [2] Enable external zero delay Selects which zero delay mode to use. [2] = 0; enables internal zero delay mode if 0x01E[1] = 1 (default). [2] = 1; enables external zero delay mode if 0x01E[1] = 1. 01E [1] Enable zero delay Enables zero delay function. [1] = 0; disables zero delay function (default). [1] = 1; enables zero delay function. 01F [6] VCO calibration finished (read-only) Readback register. Indicates the status of the VCO calibration. [6] = 0; VCO calibration not finished. [6] = 1; VCO calibration finished. 01F [5] Holdover active (read-only) Readback register. Indicates if the part is in the holdover state (see Figure 46). This is not the same as holdover enabled. [5] = 0; not in holdover. [5] = 1; holdover state active. 01F [4] REF2 selected (read-only) Readback register. Indicates which PLL reference is selected as the input to the PLL. [4] = 0; REF1 selected (or differential reference if in differential mode). [4] = 1; REF2 selected. 01F [3] VCO frequency > threshold (read-only) Readback register. Indicates if the VCO frequency is greater than the threshold (see Table 17, REF1, REF2, and VCO frequency status monitor parameter). [3] = 0; VCO frequency is less than the threshold. [3] = 1; VCO frequency is greater than the threshold.

[2] = 0; REF2 frequency is less than the threshold frequency. [2] = 1; REF2 frequency is greater than the threshold frequency. [1] = 0; REF1 frequency is less than the threshold frequency. [1] = 1; REF1 frequency is greater than the threshold frequency. Readback register. Digital lock detect. Table 54. Output Driver Control 0F0 [7] OUT0 format Selects the output type for OUT0. Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1.

00 Tristate Tristate

01 On Tristate

10 Tristate On

0F0 [4:3] OUT0 polarity Sets the output polarity for OUT0.

0 X 1 LVPECL Inverting Noninverting

[0] = 0; normal operation (default). 0F1 [7:0] OUT1 control This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0. 0F2 [7:0] OUT2 control This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0. 0F3 [7:0] OUT3 control This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0. 0F4 [7:0] OUT4 control This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0. 0F5 [7:0] OUT5 control This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.

0F6 [7:0] OUT6 control This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0. 0F7 [7:0] OUT7 control This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0. 0F8 [7:0] OUT8 control This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0. 0F9 [7:0] OUT9 control This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0. 0FA [7:0] OUT10 control This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0. 0FB [7:0] OUT11 control This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0. 0FC [7] CSDLD En OUT7 OUT7 enabled only if CSDLD is high. 0 0 Not affected by CSDLD signal (default). 1 0 Asynchronous power-down. 1 1 Asynchronously enable OUT 7 if not powered down by other settings. and set the enable LD pin comparator bit (0x01D[3]). 0FC [6] CSDLD En OUT6 OUT6 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [5] CSDLD En OUT5 OUT5 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [4] CSDLD En OUT4 OUT4 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [3] CSDLD En OUT3 OUT3 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [2] CSDLD En OUT2 OUT2 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [1] CSDLD En OUT1 OUT1 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [0] CSDLD En OUT0 OUT0 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT11 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT10 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FD [1] CSDLD En OUT9 OUT9 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FD [0] CSDLD En OUT8 OUT8 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. Table 55. LVPECL Channel Dividers 190 [7:4] Divider 0 low cycles Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7). 190 [3:0] Divider 0 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x7 means the divider is high for eight input clock cycles (default: 0x7). 191 [7] Divider 0 bypass Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). 191 [6] Divider 0 ignore SYNC Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. 191 [5] Divider 0 force high Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 191 [4] Divider 0 start high Selects clock output to start high or start low. [4] = 0; start low (default). 191 [3:0] Divider 0 phase offset Phase offset (default: 0x0).

Rev. 0 | Page 77 of 84 Reg. Addr (Hex) Bit(s) Name Description 192 [2] Channel 0 power-down Channel 0 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into safe power- down mode by setting this bit.) 192 [1] Channel 0 direct-to-output Connects OUT0, OUT1, and OUT2 to Divider 0 or directly to VCO or CLK. [1] = 0; OUT0, OUT1, and OUT2 are connected to Divider 0 (default). [1] = 1; If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0, OUT1, and OUT2. If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0, OUT1, and OUT2. If 0x1E1[1:0] = 01b, there is no effect. 192 [0] Disable Divider 0 DCC Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. 193 [7:4] Divider 1 low cycles Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x3 means the divider is low for four input clock cycles (default: 0x3). 193 [3:0] Divider 1 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x3 means the divider is high for four input clock cycles (default: 0x3). 194 [7] Divider 1 bypass Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. 194 [6] Divider 1 ignore SYNC Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. 194 [5] Divider 1 force high Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 194 [4] Divider 1 start high Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 194 [3:0] Divider 1 phase offset Phase offset (default: 0x0). 195 [2] Channel 1 power-down Channel 1 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 are put into safe power- down mode by setting this bit.) 195 [1] Channel 1 direct-to-output Connects OUT3, OUT4, and OUT5 to Divider 1 or directly to VCO or CLK. [1] = 0; OUT3, OUT4, and OUT5 are connected to Divider 1 (default). [1] = 1; If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT3, OUT4, and OUT5. If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT3, OUT4, and OUT5. If 0x1E1[1:0] = 01b, there is no effect. 195 [0] Disable Divider 1 DCC Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. 196 [7:4] Divider 2 low cycles Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x1 means the divider is low for two input clock cycles (default: 0x1). 196 [3:0] Divider 2 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x1 means the divider is high for two input clock cycles (default: 0x1). 197 [7] Divider 2 bypass Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider.

Rev. 0 | Page 78 of 84 Reg. Addr (Hex) Bit(s) Name Description 197 [6] Divider 2 ignore SYNC Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. 197 [5] Divider 2 force high Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 197 [4] Divider 2 start high Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 197 [3:0] Divider 2 phase offset Phase offset (default: 0x0). 198 [2] Channel 2 power-down Channel 2 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 are put into safe power- down mode by setting this bit.) 198 [1] Channel 2 direct-to-output Connects OUT6, OUT7, and OUT8 to Divider 2 or directly to VCO or CLK. [1] = 0; OUT6, OUT7, and OUT8 are connected to Divider 2 (default). [1] = 1: If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT6, OUT7, and OUT8. If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT6, OUT7, and OUT8. If 0x1E1[1:0] = 01b, there is no effect. 198 [0] Disable Divider 2 DCC Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. 199 [7:4] Divider 3 low cycles Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x0 means the divider is low for one input clock cycle (default: 0x0). 199 [3:0] Divider 3 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x0 means the divider is high for one input clock cycle (default: 0x0). 19A [7] Divider 3 bypass Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. 19A [6] Divider 3 ignore SYNC Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. 19A [5] Divider 3 force high Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 19A [4] Divider 3 start high Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 19A [3:0] Divider 3 phase offset Phase offset (default: 0x0). 19B [2] Channel 3 power-down Channel 3 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are also put into safe power-down mode by setting this bit.)

19B [1] Channel 3 direct-to-output Connects OUT9, OUT10, and OUT11 to Divider 3 or directly to VCO or CLK. [1] = 0; OUT9, OUT10, and OUT11 are connected to Divider 3 (default). If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT9, OUT10, and OUT11. If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT9, OUT10, and OUT11. If 0x1E1[1:0] = 01b, there is no effect. 19B [0] Disable Divider 3 DCC Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. Table 56. VCO Divider and CLK Input 1E1 [4] Power-down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree). [4] = 0; normal operation (default). 1E1 [3] Power-down VCO clock interface Powers down the interface block between VCO and clock distribution. [3] = 0; normal operation (default). 1E1 [2] Power-down VCO and CLK Powers down both VCO and CLK input. [2] = 0; normal operation (default). 1E1 [1] Select VCO or CLK Selects either the VCO or the CLK as the input to VCO divider. [1] = 0; select external CLK as input to VCO divider (default). selected. This bit must be set to use the PLL with the internal VCO. 1E1 [0] Bypass VCO divider Bypasses or uses the VCO divider. [0] = 0; use VCO divider (default). [0] = 1; bypass VCO divider; cannot select VCO as input when this is selected.

Table 57. System 230 [3] Disable power-on SYNC Power-on SYNC mode. Used to disable the antiruntpulse circuitry. [3] = 0; enable the antiruntpulse circuitry (default). [3] = 1; disable the antiruntpulse circuitry. 230 [2] Power-down SYNC Powers down the SYNC function. [2] = 0; normal operation of the SYNC function (default). [2] = 1; power-down SYNC circuitry. 230 [1] Power-down distribution reference Powers down the reference for the distribution section. [1] = 0; normal operation of the reference for the distribution section (default). [1] = 1; powers down the reference for the distribution section. state, and a 1-to-0 transition triggers a SYNC. Table 58. Update All Registers on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0. [0] = 1 (self-clearing); update all active registers to the contents of the buffer registers. Table 59. EEPROM Buffer Segment Programming the EEPROM Buffer Segment section for more information.

Table 60. EEPROM Control [0] = 0; data transfer is done. [0] = 1; data transfer is not done. This read-only register indicates an error during the data transferred between the EEPROM and the buffer. [0] = 0; no error. Data is correct. [0] = 1; incorrect data detected. B02 [1] Soft_EEPROM When the EEPROM pin is tied low, setting Soft_EEPROM resets the AD9520 using the settings saved in EEPROM. [1] = 1; soft reset with EEPROM settings (self-clearing). Enables the user to write to the EEPROM. [0] = 0; EEPROM write protection is enabled. User cannot write to EEPROM (default). [0] = 1; EEPROM write protection is disabled. User can write to EEPROM. B03 [0] REG2EEPROM Transfers data from the buffer register to the EEPROM (self-clearing). it is reset by the I²C master after the data transfer is done.

0.25 MIN

0.20 REF

0.65 TYP

0.05 MAX

0.02 NOM

0.60 MAX

Figure 75. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the prop erty of their respective owners.