AD9517-0ABCPZ-RL7

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12-Output Clock Generator with Integrated 2.8 GHz VCO Data Sheet AD9517-0 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 © 2007–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.55 GHz to 2.95 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable 2 pairs of 1.6 GHz LVPECL outputs Each output pair shares a 1-to-32 divider with coarse phase delay Additive output jitter: 225 fs rms Channel-to-channel skew paired outputs of <10 ps 2 pairs of 800 MHz LVDS clock outputs Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay Additive output jitter: 275 fs rms Fine delay adjust (Δt) on each LVDS output Each LVDS output can be reconfigured as two 250 MHz CMOS outputs Automatic synchronization of all outputs on power-up Manual output synchronization available Available in a 48-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation GENERAL DESCRIPTION The AD9517-01 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz to 2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used. The AD9517-0 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements. FUNCTIONAL BLOCK DIAGRAM REFIN REF1 REF2 CLK LF SWITCHOVER AND MONITOR PLL DIVIDER AND MUXs CP VCO STATUS MONITOR LVPECL LVPECL LVDS/CMOS LVDS/CMOS SERIAL CONTROL PORT AND DIGITAL LOGIC AD9517-0 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 DIV/Φ DIV/Φ DIV/Φ DIV/Φ DIV/Φ DIV/Φ Δt Δt Δt Δt 06424-001 Figure 1. The AD9517-0 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz. For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs. Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024. The AD9517-0 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal). The AD9517-0 is specified for operation over the industrial range of −40°C to +85°C.

1 AD9517 is used throughout the data sheet to refer to all the members of the

AD9517 family. However, when AD9517-0 is used, it refers to that specific member of the AD9517 family.

Rev. E | Page 2 of 80 TABLE OF CONTENTS Clock Output Additive Phase Noise (Distribution Only; Clock Output Absolute Phase Noise (Internal VCO Used) .. 10 Clock Output Absolute Time Jitter (Clock Generation Clock Output Absolute Time Jitter (Clock Cleanup Clock Output Absolute Time Jitter (Clock Generation Clock Output Additive Time Jitter (VCO Divider Using the AD9517 Outputs for ADC Clock Applications .... 76

Rev. E | Page 3 of 80

REVISION HISTORY

3/13—Rev. D to Rev. E 1/12—Rev. C to Rev. D 5/11—Rev. B to Rev. C Changes to Features, Applications, and General Description Changes to Logic 1 Current and Logic 0 Current Changes to Prescaler Section and Change to Changes to Automatic/Internal Holdover Mode Section Changes to Address 0x017, Bits[1:0] and Address 0x018, 5/10—Rev. A to Rev. B Changes to Default Values of LVDS/CMOS Outputs Changes to Register 0x140, Bit 0; Register 0x142, Bit 0; 12/09—Rev. 0 to Rev. A Added Exposed Paddle Notation to Figure 6; Changes to Change to High Frequency Clock Distribution—CLK or Changes to Charge Pump (CP), On-Chip VCO, PLL Changes to Reference Switchover and VCXO/VCO Change to Clock Frequency Division Section; Changes to Channel Dividers—LVDS/CMOS Outputs 7/07—Revision 0: Initial Version

Rev. E | Page 4 of 80 SPECIFICATIONS Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments VS 3.135 3.3 3.465 V 3.3 V ± 5% VS_LVPECL 2.375 VS V Nominally 2.5 V to 3.3 V ± 5% VCP VS 5.25 V Nominally 3.3 V to 5.0 V ± 5% RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 2.7 5.1 10 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA); actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground PLL CHARACTERISTICS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments VCO (ON-CHIP) Frequency Range 2550 2950 MHz See Figure 15 VCO Gain (KVCO) 50 MHz/V See Figure 10 Tuning Voltage (VT) 0.5 VCP − 0.5 V VCP ≤ VS when using internal VCO; outside of this range, the CP spurs may increase due to CP up/down mismatch Frequency Pushing (Open Loop) 1 MHz/V Phase Noise at 100 kHz Offset −105 dBc/Hz f = 2800 MHz Phase Noise at 1 MHz Offset −123 dBc/Hz f = 2800 MHz REFERENCE INPUTS Differential Mode (REFIN, REFIN) Differential mode (can accommodate single-ended input by ac grounding undriven input) Input Frequency 0 250 MHz Frequencies below about 1 MHz should be dc-coupled; be careful to match VCM (self-bias voltage) Input Sensitivity 250 mV p-p PLL figure of merit (FOM) increases with increasing slew rate (see Figure 14); the input sensitivity is sufficient for ac-coupled LVDS and LVPECL signals Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN1 Self-Bias Voltage, REFIN 1.30 1.50 1.60 V Self-bias voltage of REFIN1 Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased1 Input Resistance, REFIN 4.4 5.3 6.4 kΩ Self-biased1 Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/µs Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/µs; CMOS levels Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed VS p-p Input Logic High 2.0 V Input Logic Low 0.8 V Input Current −100 +100 µA Pulse Width High/Low 1.8 ns This value determines the allowable input duty cycle and is the amount of time that a square wave is high/low Input Capacitance 2 pF Each pin, REFIN/REFIN (REF1/REF2) PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pulse width = 6.0 ns Antibacklash Pulse Width 1.3 ns Register 0x017[1:0] = 01b 2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b 6.0 ns Register 0x017[1:0] = 10b

Rev. E | Page 5 of 80 Parameter Min Typ Max Unit Test Conditions/Comments CHARGE PUMP (CP) CPV is CP pin voltage; VCP is charge pump power supply voltage ICP Sink/Source Programmable High Value 4.8 mA With CPRSET = 5.1 kΩ Low Value 0.60 mA Absolute Accuracy 2.5 % CPV = VCP/2 V CPRSET Range 2.7/10 kΩ ICP High Impedance Mode Leakage 1 nA Sink-and-Source Current Matching 2 % 0.5 < CPV < VCP − 0.5 V ICP vs. CPV 1.5 % 0.5 < CPV < VCP − 0.5 V ICP vs. Temperature 2 % CPV = VCP/2 V PRESCALER (PART OF N DIVIDER) See the VCXO/VCO Feedback Divider N—P , A, B, R section Prescaler Input Frequency P = 1 FD 300 MHz P = 2 FD 600 MHz P = 3 FD 900 MHz P = 2 DM (2/3) 200 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 2400 MHz P = 16 DM (16/17) 3000 MHz P = 32 DM (32/33) 3000 MHz Prescaler Output Frequency 300 MHz A, B counter input frequency (prescaler input frequency divided by P) PLL DIVIDER DELAYS Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 54

000 Off ps

In-Band Phase Noise of the Charge Pump/Phase Frequency Detector (In-Band Is Within the LBW of the PLL) The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider) At 500 kHz PFD Frequency −165 dBc/Hz At 1 MHz PFD Frequency −162 dBc/Hz At 10 MHz PFD Frequency −151 dBc/Hz At 50 MHz PFD Frequency −143 dBc/Hz PLL Figure of Merit (FOM) −220 dBc/Hz Reference slew rate > 0.25 V/ns; FOM + 10 log(fPFD) is an approxi- mation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed-loop, the phase noise, as observed at the VCO output, is increased by 20 log(N) PLL DIGITAL LOCK DETECT WINDOW2 Signal available at LD, STATUS, and REFMON pins when selected by appropriate register settings Required to Lock (Coincidence of Edges) Selected by Register 0x017[1:0] and Register 0x018[4] Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 3.5 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b To Unlock After Lock (Hysteresis)2 Low Range (ABP 1.3 ns, 2.9 ns) 7 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 15 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 11 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b 1 REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. 2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

Rev. E | Page 6 of 80 CLOCK INPUTS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments CLOCK INPUTS (CLK, CLK) Differential input Input Frequency 01 2.4 GHz High frequency distribution (VCO divider) 01 1.6 GHz Distribution only (VCO divider bypassed) Input Sensitivity, Differential 150 mV p-p Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns Input Level, Differential 2 V p-p Larger voltage swings may turn on the protection diodes and may degrade jitter performance Input Common-Mode Voltage, VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling Input Common-Mode Range, VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLK ac-bypassed to RF ground Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF 1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM. CLOCK OUTPUTS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V OUT0, OUT1, OUT2, OUT3 Differential (OUT, OUT) Output Frequency, Maximum 2950 MHz Using direct to output; see Figure 25 for peak-to-peak differential amplitude Output High Voltage (VOH) VS_LVPECL − 1.12 VS_LVPECL − 0.98 VS_LVPECL − 0.84 V Output Low Voltage (VOL) VS_LVPECL − 2.03 VS_LVPECL − 1.77 VS_LVPECL − 1.49 V Output Differential Voltage (VOD) 550 790 980 mV This is VOH − VOL for each leg of a differential pair for default amplitude setting with driver not toggling; the peak-to-peak amplitude measured using a differential probe across the differential pair with the driver toggling is roughly 2× these values (see Figure 25 for variation over frequency) LVDS CLOCK OUTPUTS Differential termination 100 Ω at 3.5 mA OUT4, OUT5, OUT6, OUT7 Differential (OUT, OUT) Output Frequency 800 MHz The AD9517 outputs toggle at higher frequencies, but the output amplitude may not meet the VOD specification; see Figure 26 Output Differential Voltage (VOD) 247 360 454 mV VOH − VOL measurement across a differential pair at the default amplitude setting with output driver not toggling; see Figure 26 for variation over frequency Delta VOD 25 mV This is the absolute value of the difference between V OD when the normal output is high vs. when the complementary output is high Output Offset Voltage (VOS) 1.125 1.24 1.375 V (VOH + VOL)/2 across a differential pair Delta VOS 25 mV This is the absolute value of the difference between V OS when the normal output is high vs. when the complementary output is high Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND

Rev. E | Page 7 of 80 Parameter Min Typ Max Unit Test Conditions/Comments CMOS CLOCK OUTPUTS OUT4A, OUT4B, OUT5A, OUT5B, OUT6A, OUT6B, OUT7A, OUT7B Single-ended; termination = 10 pF Output Frequency 250 MHz See Figure 27 Output Voltage High (VOH) VS − 0.1 V At 1 mA load Low (VOL) 0.1 V At 1 mA load Source Current Exceeding these values can result in damage to the part Static 20 mA Dynamic 16 mA Sink Current Exceeding these values can result in damage to the part Static 8 mA Dynamic 16 mA

Rev. E | Page 8 of 80 TIMING CHARACTERISTICS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL Termination = 50 Ω to VS − 2 V; level = 810 mV Output Rise Time, tRP 70 180 ps 20% to 80%, measured differentially Output Fall Time, tFP 70 180 ps 80% to 20%, measured differentially PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 43 Clock Distribution Configuration 773 933 1090 ps See Figure 45 Variation with Temperature 0.8 ps/°C OUTPUT SKEW, LVPECL OUTPUTS1 LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps LVDS Termination = 100 Ω differential; 3.5 mA Output Rise Time, tRL 170 350 ps 20% to 80%, measured differentially2 Output Fall Time, tFL 160 350 ps 20% to 80%, measured differentially2 PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT Delay off on all outputs For All Divide Values 1.4 1.8 2.1 ns Variation with Temperature 1.25 ps/°C OUTPUT SKEW, LVDS OUTPUTS1 Delay off on all outputs LVDS Outputs That Share the Same Divider 6 62 ps LVDS Outputs on Different Dividers 25 150 ps All LVDS Outputs Across Multiple Parts 430 ps CMOS Termination = open Output Rise Time, tRC 495 1000 ps 20% to 80%; CLOAD = 10 pF Output Fall Time, tFC 475 985 ps 80% to 20%; CLOAD = 10 pF PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT Fine delay off For All Divide Values 1.6 2.1 2.6 ns Variation with Temperature 2.6 ps/°C OUTPUT SKEW, CMOS OUTPUTS1 Fine delay off CMOS Outputs That Share the Same Divider 4 66 ps All CMOS Outputs on Different Dividers 28 180 ps All CMOS Outputs Across Multiple Parts 675 ps DELAY ADJUST3 LVDS and CMOS Shortest Delay Range4 Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 101111b Zero Scale 50 315 680 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b Full Scale 540 880 1180 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b Longest Delay Range4 Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 000000b Zero Scale 200 570 950 ps Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b Quarter Scale 1.72 2.31 2.89 ns Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 001100b Full Scale 5.7 8.0 10.1 ns Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b Delay Variation with Temperature Short Delay Range5 Zero Scale 0.23 ps/°C Full Scale −0.02 ps/°C Long Delay Range5 Zero Scale 0.3 ps/°C Full Scale 0.24 ps/°C 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Corresponding CMOS drivers set to A for noninverting and B for inverting. 3 The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output. 4 Incremental delay; does not include propagation delay. 5 All delays between zero scale and full scale can be estimated by linear interpolation.

Rev. E | Page 9 of 80 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter Min Typ Max Unit Test Conditions/Comments CLK-TO-LVPECL ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, Output = 1 GHz Input slew rate > 1 V/ns Divider = 1 At 10 Hz Offset −109 dBc/Hz At 100 Hz Offset −118 dBc/Hz At 1 kHz Offset −130 dBc/Hz At 10 kHz Offset −139 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −146 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz CLK = 1 GHz, Output = 200 MHz Input slew rate > 1 V/ns Divider = 5 At 10 Hz Offset −120 dBc/Hz At 100 Hz Offset −126 dBc/Hz At 1 kHz Offset −139 dBc/Hz At 10 kHz Offset −150 dBc/Hz At 100 kHz Offset −155 dBc/Hz At 1 MHz Offset −157 dBc/Hz >10 MHz Offset −157 dBc/Hz CLK-TO-LVDS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1.6 GHz, Output = 800 MHz Input slew rate > 1 V/ns Divider = 2 At 10 Hz Offset −103 dBc/Hz At 100 Hz Offset −110 dBc/Hz At 1 kHz Offset −120 dBc/Hz At 10 kHz Offset −127 dBc/Hz At 100 kHz Offset −133 dBc/Hz At 1 MHz Offset −138 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz CLK = 1.6 GHz, Output = 400 MHz Input slew rate > 1 V/ns Divider = 4 At 10 Hz Offset −114 dBc/Hz At 100 Hz Offset −122 dBc/Hz At 1 kHz Offset −132 dBc/Hz At 10 kHz Offset −140 dBc/Hz At 100 kHz Offset −146 dBc/Hz At 1 MHz Offset −150 dBc/Hz >10 MHz Offset −155 dBc/Hz CLK-TO-CMOS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, Output = 250 MHz Input slew rate > 1 V/ns Divider = 4 At 10 Hz Offset −110 dBc/Hz At 100 Hz Offset −120 dBc/Hz At 1 kHz Offset −127 dBc/Hz At 10 kHz Offset −136 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −147 dBc/Hz >10 MHz Offset −154 dBc/Hz

Rev. E | Page 10 of 80 Parameter Min Typ Max Unit Test Conditions/Comments CLK = 1 GHz, Output = 50 MHz Input slew rate > 1 V/ns Divider = 20 At 10 Hz Offset −124 dBc/Hz At 100 Hz Offset −134 dBc/Hz At 1 kHz Offset −142 dBc/Hz At 10 kHz Offset −151 dBc/Hz At 100 kHz Offset −157 dBc/Hz At 1 MHz Offset −160 dBc/Hz >10 MHz Offset −163 dBc/Hz CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL ABSOLUTE PHASE NOISE Internal VCO; direct to LVPECL output VCO = 2.95 GHz; Output = 2.95 GHz At 1 kHz Offset −47 dBc/Hz At 10 kHz Offset −78 dBc/Hz At 100 kHz Offset −104 dBc/Hz At 1 MHz Offset −122 dBc/Hz At 10 MHz Offset −140 dBc/Hz At 40 MHz Offset −146 dBc/Hz VCO = 2.75 GHz; Output = 2.75 GHz At 1 kHz Offset −49 dBc/Hz At 10 kHz Offset −79 dBc/Hz At 100 kHz Offset −105 dBc/Hz At 1 MHz Offset −123 dBc/Hz At 10 MHz Offset −141 dBc/Hz At 40 MHz Offset −146 dBc/Hz VCO = 2.55 GHz; Output = 2.55 GHz At 1 kHz Offset −51 dBc/Hz At 10 kHz Offset −80 dBc/Hz At 100 kHz Offset −106 dBc/Hz At 1 MHz Offset −125 dBc/Hz At 10 MHz Offset −142 dBc/Hz At 40 MHz Offset −146 dBc/Hz

Rev. E | Page 11 of 80 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter Min Typ Max Unit Test Conditions/Comments setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R = 1 VCO = 2.95 GHz; LVPECL = 491.52 MHz; PLL LBW = 75 kHz 148 fs rms Integration BW = 200 kHz to 10 MHz 342 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.95 GHz; LVPECL = 122.88 MHz; PLL LBW = 75 kHz 212 fs rms Integration BW = 200 kHz to 10 MHz 320 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.70 GHz; LVPECL = 122.88 MHz; PLL LBW = 187 kHz 184 fs rms Integration BW = 200 kHz to 10 MHz 304 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.70 GHz; LVPECL = 61.44 MHz; PLL LBW = 187 kHz 221 fs rms Integration BW = 200 kHz to 10 MHz 345 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.58 GHz; LVPECL = 61.44 MHz; PLL LBW = 75 kHz 210 fs rms Integration BW = 200 kHz to 10 MHz 334 fs rms Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9. Parameter Min Typ Max Unit Test Conditions/Comments setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 19.44 MHz; R = 1 VCO = 2.80 GHz; LVPECL = 155.52 MHz; PLL LBW = 12.8 kHz 513 fs rms Integration BW = 12 kHz to 20 MHz VCO = 2.95 GHz; LVPECL = 77.76 MHz; PLL LBW = 12.8 kHz 544 fs rms Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 10. Parameter Min Typ Max Unit Test Conditions/Comments setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R = 1 LVPECL = 245.76 MHz; PLL LBW = 125 Hz 54 fs rms Integration BW = 200 kHz to 5 MHz 77 fs rms Integration BW = 200 kHz to 10 MHz 109 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 122.88 MHz; PLL LBW = 125 Hz 79 fs rms Integration BW = 200 kHz to 5 MHz 114 fs rms Integration BW = 200 kHz to 10 MHz 163 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 61.44 MHz; PLL LBW = 125 Hz 124 fs rms Integration BW = 200 kHz to 5 MHz 176 fs rms Integration BW = 200 kHz to 10 MHz 259 fs rms Integration BW = 12 kHz to 20 MHz

Rev. E | Page 12 of 80 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1 40 fs rms BW = 12 kHz to 20 MHz CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4 80 fs rms BW = 12 kHz to 20 MHz CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16 215 fs rms Calculated from SNR of ADC method; DCC not used for even divides CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5 245 fs rms Calculated from SNR of ADC method; DCC on LVDS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2; VCO Divider Not Used 85 fs rms BW = 12 kHz to 20 MHz CLK = 1 GHz; LVDS = 200 MHz; Divider = 5 113 fs rms BW = 12 kHz to 20 MHz CLK = 1.6 GHz; LVDS= 100 MHz; Divider = 16 280 fs rms Calculated from SNR of ADC method; DCC not used for even divides CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16 365 fs rms Calculated from SNR of ADC method; DCC not used for even divides CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 12. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz; Divider = 12; Duty-Cycle Correction = Off 210 fs rms Calculated from SNR of ADC method LVDS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz; Divider = 12; Duty-Cycle Correction = Off 285 fs rms Calculated from SNR of ADC method CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz; Divider = 12; Duty-Cycle Correction = Off 350 fs rms Calculated from SNR of ADC method

Rev. E | Page 13 of 80 DELAY BLOCK ADDITIVE TIME JITTER Table 13. Parameter Min Typ Max Unit Test Conditions/Comments DELAY BLOCK ADDITIVE TIME JITTER1 Incremental additive jitter

100 MHz Output

Delay (1600 µA, 0x1C) Fine Adj. 000000b 0.54 ps rms Delay (1600 µA, 0x1C) Fine Adj. 101111b 0.60 ps rms Delay (800 µA, 0x1C) Fine Adj. 000000b 0.65 ps rms Delay (800 µA, 0x1C) Fine Adj. 101111b 0.85 ps rms Delay (800 µA, 0x4C) Fine Adj. 000000b 0.79 ps rms Delay (800 µA, 0x4C) Fine Adj. 101111b 1.2 ps rms Delay (400 µA, 0x4C) Fine Adj. 000000b 1.2 ps rms Delay (400 µA, 0x4C) Fine Adj. 101111b 2.0 ps rms Delay (200 µA, 0x1C) Fine Adj. 000000b 1.3 ps rms Delay (200 µA, 0x1C) Fine Adj. 101111b 2.5 ps rms Delay (200 µA, 0x4C) Fine Adj. 000000b 1.9 ps rms Delay (200 µA, 0x4C) Fine Adj. 101111b 3.8 ps rms 1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter should be added to this value using the root sum of the squares (RSS) method. SERIAL CONTROL PORT Table 14. Parameter Min Typ Max Unit Test Conditions/Comments CS (INPUT) CS has an internal 30 kΩ pull-up resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 µA Input Logic 0 Current 110 µA Input Capacitance 2 pF SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF SDIO (WHEN INPUT) Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V TIMING Clock Rate (SCLK, 1/tSCLK) 25 MHz Pulse Width High, tHIGH 16 ns Pulse Width Low, tLOW 16 ns SDIO to SCLK Setup, tDS 2 ns SCLK to SDIO Hold, tDH 1.1 ns SCLK to Valid SDIO and SDO, tDV 8 ns CS to SCLK Setup and Hold, tS, tH 2 ns CS Minimum Pulse Width High, tPWH 3 ns

Rev. E | Page 14 of 80 PD, SYNC, AND RESET PINS Table 15. Parameter Min Typ Max Unit Test Conditions/Comments INPUT CHARACTERISTICS These pins each have a 30 kΩ internal pull-up resistor Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 1 µA Logic 0 Current 110 µA Capacitance 2 pF RESET TIMING Pulse Width Low 50 ns SYNC TIMING Pulse Width Low 1.5 High speed clock cycles High speed clock is CLK input signal LD, STATUS, AND REFMON PINS Table 16. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT CHARACTERISTICS When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 54, Register 0x017, Register 0x01A, and Register 0x01B Output Voltage High (VOH) 2.7 V Output Voltage Low (VOL) 0.4 V MAXIMUM TOGGLE RATE 100 MHz Applies when mux is set to any divider or counter output, or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling ANALOG LOCK DETECT Capacitance 3 pF On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor REF1, REF2, AND VCO FREQUENCY STATUS MONITOR Normal Range 1.02 MHz Frequency above which the monitor always indicates the presence of the reference Extended Range (REF1 and REF2 Only) 8 kHz Frequency above which the monitor always indicates the presence of the reference LD PIN COMPARATOR Trip Point 1.6 V Hysteresis 260 mV

Rev. E | Page 15 of 80 POWER DISSIPATION Table 17. Parameter Min Typ Max Unit Test Conditions/Comments POWER DISSIPATION, CHIP Power-On Default 1.0 1.2 W No clock; no programming; default register values; does not include power dissipated in external resistors Full Operation; CMOS Outputs at 229 MHz 1.4 2.0 W PLL on; internal VCO = 2750 MHz; VCO divider = 2; all channel dividers on; four LVPECL outputs at 687.5 MHz; eight CMOS outputs (10 pF load) at 229 MHz; all fine delay on, maximum current; does not include power dissipated in external resistors Full Operation; LVDS Outputs at 200 MHz 1.4 2.1 W PLL on; internal VCO = 2800 MHz, VCO divider = 2; all channel dividers on; four LVPECL outputs at 700 MHz; four LVDS outputs at 200 MHz; all fine delay on, maximum current; does not include power dissipated in external resistors PD Power-Down 75 185 mW PD pin pulled low; does not include power dissipated in terminations PD Power-Down, Maximum Sleep 31 mW PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b; SYNC power-down, Register 0x230[2] = 1b; REF for distribution power-down, Register 0x230[1] = 1b VCP Supply 4 4.8 mW PLL operating; typical closed-loop configuration POWER DELTAS, INDIVIDUAL FUNCTIONS Power delta when a function is enabled/disabled VCO Divider 30 mW VCO divider bypassed REFIN (Differential) 20 mW All references off to differential reference enabled REF1, REF2 (Single-Ended) 4 mW All references off to REF1 or REF2 enabled; differential reference not enabled VCO 70 mW CLK input selected to VCO selected PLL 75 mW PLL off to PLL on, normal operation; no reference enabled Channel Divider 30 mW Divider bypassed to divide-by-2 to divide-by-32 LVPECL Channel (Divider Plus Output Driver) 160 mW No LVPECL output on to one LVPECL output on, independent of frequency LVPECL Driver 90 mW Second LVPECL output turned on, same channel LVDS Channel (Divider Plus Output Driver) 120 mW No LVDS output on to one LVDS output on; see Figure 8 for dependence on output frequency LVDS Driver 50 mW Second LVDS output turned on, same channel CMOS Channel (Divider Plus Output Driver) 100 mW Static; no CMOS output on to one CMOS output on; see Figure 9 for variation over output frequency CMOS Driver (Second in Pair) 0 mW Static; second CMOS output, same pair, turned on CMOS Driver (First in Second Pair) 30 mW Static; first output, second pair, turned on Fine Delay Block 50 mW Delay block off to delay block enabled; maximum current setting

Rev. E | Page 17 of 80 ABSOLUTE MAXIMUM RATINGS Table 18. Parameter Rating VS, VS_LVPECL to GND −0.3 V to +3.6 V VCP to GND −0.3 V to +5.8 V REFIN, REFIN to GND −0.3 V to VS + 0.3 V REFIN to REFIN −3.3 V to +3.3 V RSET to GND −0.3 V to VS + 0.3 V CPRSET to GND −0.3 V to VS + 0.3 V CLK, CLK to GND −0.3 V to VS + 0.3 V CLK to CLK −1.2 V to +1.2 V SCLK, SDIO, SDO, CS to GND −0.3 V to VS + 0.3 V OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3,OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7 to GND −0.3 V to VS + 0.3 V SYNC to GND −0.3 V to VS + 0.3 V REFMON, STATUS, LD to GND −0.3 V to VS + 0.3 V Junction Temperature1 150°C Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C 1 See Table 19 for θJA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Table 19. Package Type1 θJA Unit 48-Lead LFCSP 24.7 °C/W

1 Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-2. ESD CAUTION

1. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE

CONNECTED TO GROUND FOR PROPER OPERATION. Figure 6. Pin Configuration Table 20. Pin Function Descriptions most applications; but if a 5 V external VCXO is used, this pin should be 5 V. 4 O 3.3 V CMOS CP Charge Pump (Output). Connects to external loop filter. 5 O 3.3 V CMOS STATUS Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017. internal 30 kΩ pull-up resistor. 9 O Loop filter BYPASS This pin is for bypassing the LDO to ground with a capacitor. I Power VS 3.3 V Power Pins.

11 I Differential

section. This pin can be left floating if internal VCO is used.

12 I Differential

section. This pin can be left floating if internal VCO is used. 13 I 3.3 V CMOS SCLK Serial Control Port Data Clock Signal. 14 I 3.3 V CMOS CS Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor.

Rev. E | Page 19 of 80 Pin No. Input/ Output Pin Type Mnemonic Description 15 O 3.3 V CMOS SDO Serial Control Port. Unidirectional serial data output. 16 I/O 3.3 V CMOS SDIO Serial Control Port. Bidirectional serial data input/output and unidirectional serial data input. 17 I 3.3 V CMOS RESET Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor. 18 I 3.3 V CMOS PD Chip Power Down, Active Low. This pin has an internal 30 kΩ pull-up resistor. 21, 40 I Power VS_LVPECL Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins. 42 O LVPECL OUT0 LVPECL Output; One Side of a Differential LVPECL Output. 41 O LVPECL OUT0 LVPECL Output; One Side of a Differential LVPECL Output. 39 O LVPECL OUT1 LVPECL Output; One Side of a Differential LVPECL Output. 38 O LVPECL OUT1 LVPECL Output; One Side of a Differential LVPECL Output. 19 O LVPECL OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 20 O LVPECL OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 22 O LVPECL OUT3 LVPECL Output; One Side of a Differential LVPECL Output. 23 O LVPECL OUT3 LVPECL Output; One Side of a Differential LVPECL Output.

35 O LVDS or

OUT4 (OUT4A) LVDS/CMOS Output; One Side of a Differential LVDS Output or a Single-Ended CMOS Output.

34 O LVDS or

OUT4 (OUT4B) LVDS/CMOS Output; One Side of a Differential LVDS Output or a Single-Ended CMOS Output.

33 O LVDS or

OUT5 (OUT5A) LVDS/CMOS Output; One Side of a Differential LVDS Output or a Single-Ended CMOS Output.

32 O LVDS or

OUT5 (OUT5B) LVDS/CMOS Output; One Side of a Differential LVDS Output or a Single-Ended CMOS Output.

26 O LVDS or

OUT6 (OUT6A) LVDS/CMOS Output; One Side of a Differential LVDS Output or a Single-Ended CMOS Output.

27 O LVDS or

OUT6 (OUT6B) LVDS/CMOS Output; One Side of a Differential LVDS Output or a Single-Ended CMOS Output.

28 O LVDS or

OUT7 (OUT7A) LVDS/CMOS Output; One Side of a Differential LVDS Output or a Single-Ended CMOS Output.

29 O LVDS or

OUT7 (OUT7B) LVDS/CMOS Output; One Side of a Differential LVDS Output or a Single-Ended CMOS Output.

44 O Current set

RSET Resistor connected here sets internal bias currents. Nominal value = 4.12 kΩ.

46 O Current set

CPRSET Resistor connected here sets CP current range. Nominal value = 5.1 kΩ.

47 I Reference

REFIN (REF2) Along with REFIN, this is the self-biased differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF2.

48 I Reference

REFIN (REF1) Along with REFIN, this is the self-biased differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1. EPAD GND GND Ground. The external paddle on the bottom of the package must be connected to ground for proper operation.

2 CHANNELS—4 LVPECL

2 CHANNELS—2 LVPECL

1 CHANNEL—1 LVPECL

Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs

1 CHANNEL—1 LVDS

2 CHANNELS—2 LVDS

2 CHANNELS—4 LVDS

Figure 8. Current vs. Frequency—LVDS Outputs

1 CHANNEL—2 CMOS

1 CHANNEL—1 CMOS

2 CHANNELS—2 CMOS

2 CHANNELS—8 CMOS

Figure 9. Current vs. Frequency—CMOS Outputs Figure 10. VCO KVCO vs. Frequency Figure 11. Charge Pump Characteristics at VCP = 3.3 V Figure 12. Charge Pump Characteristics at VCP = 5.0 V

Rev. E | Page 26 of 80 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal-to-noise ratio (SNR) and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise Additive phase noise is the amount of phase noise that can be attributed to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. Additive Time Jitter Additive time jitter is the amount of time jitter that can be attributed to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.

1 TO 32

1 TO 32 LVDS/CMOSDIVIDE BY

Figure 42. Detailed Block Diagram

appropriate bits in the corresponding control register or registers. minimum divide is 2 before the channel dividers. Register 0x232 must be set to 0x01 for the values to take effect. Table 21. Default Settings of Some PLL Registers 0x010[1:0] = 01b PLL asynchronous power-down (PLL off) . 0x1E1[0] = 0b Use the VCO divider. 0x1E1[1] = 0b CLK selected as the source. Table 22. Settings When Using an External VCO 0x010[1:0] = 00b PLL normal operation (PLL on). according to the intended loop configuration. 0x1E1[1] = 0b CLK selected as the source. Table 23. Setting the PFD Polarity voltage produces lower frequency).

Figure 43. High Frequency Clock Distribution or External VCO > 1600 MHz

Figure 44. Internal VCO and Clock Distribution crucial to the loop stability. VCO (Register 0x018[0]) to ensure optimal performance. register settings that are shown in Table 24. Table 24. Settings When Using Internal VCO 0x010[1:0] = 00b PLL normal operation (PLL on). according to the intended loop configuration. divide-by-4, divide-by-5, and divide-by-6. 0x1E1[1] = 1b Select VCO as the source.

Figure 45. Clock Distribution or External VCO < 1600 MHz

divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is bypassed. to the maximum input frequency allowed at the channel dividers). <1600 MHz, use the register settings that are shown in Table 25. Table 25. Settings for Clock Distribution < 1600 MHz Table 26. Settings for Using Internal PLL with External VCO <

1600 MHz

polarity for the VCO/VCXO being used. Table 27. Setting the PFD Polarity Register 0x232 must be set to 0x01 for the values to take effect.

Figure 46. PLL Functional Blocks The AD9517 includes an on-chip PLL with an on-chip VCO. usually consists of a small number of capacitors and resistors. establish the loop bandwidth and stability of the operating PLL. external VCO/VCXO, and the loop bandwidth. Table 52 and Table 54) and by the design of the external loop filter. theory and design is helpful. available at www.analog.com/clocks. delay element that controls the width of the antibacklash pulse. antibacklash pulse width is set by Register 0x017[1:0]. specified in the phase/frequency detector parameter of Table 2.

Figure 49. REFIN Equivalent Circuit detection of the presence of a reference. condition is not met, and the PLL does not reacquire. Automatic nonrevertive switching is not supported. The reference inputs are routed to the reference divider, R. depends on the antibacklash pulse setting (see Table 2). where the value of P can be 2, 4, 8, 16, or 32. modes are available at all frequencies (see Table 2). in which case the previous equation also applies.

be locked to any integer multiple of N. divider value by using the other prescaler modes. must be less than the B counter. because the frequency going to the A/B counter is too high. VCO requires an overall feedback divider greater than 32. that these reset bits are not self-clearing. (see Table 54). The SYNC pin reset is disabled by default. Both the R and N dividers feature a programmable delay cell. range is about 1 ns. See Register 0x019 in Table 54. Table 28. Using a 10 MHz Reference Input to Generate Different VCO Frequencies 10 1 1 X 1 1 10 FD P = 1, B = 1 (A and B counters are bypassed). 10 1 2 X 1 2 20 FD P = 2, B = 1 (A and B counters are bypassed). 10 1 1 X 3 3 30 FD A counter is bypassed. 10 1 1 X 4 4 40 FD A counter is bypassed. 10 1 1 X 5 5 50 FD A counter is bypassed. 10 1 2 X 3 6 60 FD A counter is bypassed. 10 1 2 1 3 7 70 DM Maximum frequency into prescaler in P = 2/3 mode is 200 MHz. to 300 MHz, use P = 1, and N = 7 or 11, respectively. P = 32 is not allowed (A > B not allowed).

impedance. This is useful when the PLL reference clock is lost. constant frequency even though there is no reference clock. accuracy is sufficient for 3 sec to 5 sec. before issuing a VCO calibration. difference for the loop to settle out. off each time SYNC is taken low to put the part into holdover. of the automatic/internal holdover function operation. LOCK WAS PREVIOUSLY ACHIEVED.

5 TO 255 CYCLES (PROGRAMMING OF

INSIDE THE LOCK WINDOW AT THE PFD. FUNCTION CAN BE RETRIGGERED. Figure 53. Flowchart of Automatic/Internal Holdover Mode

Rev. E | Page 39 of 80 The holdover function senses the logic level of the LD pin as a condition to enter holdover. The signal at LD can be from the DLD, ALD, or current source LD mode. It is possible to disable the LD comparator (Register 0x01D[3]), which causes the holdover function to always sense LD as high. If DLD is used, it is possible for the DLD signal to chatter some while the PLL is reacquiring lock. The holdover function may retrigger, thereby preventing the holdover mode from ever terminating. Use of the current source lock detect mode is recommended to avoid this situation (see the Current Source Digital Lock Detect section). Once in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present. As in the external holdover mode, the B counter (in the N divider) is reset synchronously with the charge pump leaving the high impedance state on the reference path PFD event. This helps align the edges out of the R and N dividers for faster settling of the PLL and to reduce frequency errors during settling. Because the prescaler is not reset, this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out. After leaving holdover, the loop then reacquires lock and the LD pin must charge (if Register 0x01D[3] = 1) before it can re-enter holdover (CP high impedance). The holdover function always responds to the state of the currently selected reference (Register 0x01C). If the loop loses lock during a reference switchover (see the Reference Switchover section), holdover is triggered briefly until the next reference clock edge at the PFD. The following registers affect the internal/automatic holdover function:

• Register 0x018[6:5], lock detect counter. These bits change the number of consecutive PFD cycles with edges inside the lock detect window that are required for the DLD indicator to indicate lock. This impacts the time required before the LD pin can begin to charge as well as the delay from the end of a holdover event until the holdover function can be reengaged.
• Register 0x018[3], disable digital lock detect. This bit must be set to 0b to enable the DLD circuit. Internal/automatic holdover does not operate correctly without the DLD function enabled.
• Register 0x01A[5:0], lock detect pin output select. Set these bits to 000100b for the current source lock detect mode if using the LD pin comparator. Load the LD pin with a capacitor of an appropriate value.
• Register 0x01D[3], enable LD pin comparator. 1 = enable, 0 = disable. When disabled, the holdover function always senses the LD pin as high.
• Register 0x01D[1], enable external holdover control.
• Register 0x01D[0] and Register 0x01D[2], holdover function enable. If holdover is disabled, both external and internal/automatic holdover are disabled. For example, to use automatic holdover with the following:
• Automatic reference switchover, prefer REF1
• Digital lock detect: five PFD cycles, high range window
• Automatic holdover using the LD pin comparator Set the following registers (in addition to the normal PLL registers):
• Register 0x018[6:5] = 00b; lock detect counter = five cycles.
• Reg ister 0x018[4] = 0b; lock detect window = high range.
• Register 0x018[3] = 0b; DLD normal operation.
• Register 0x01A[5:0] = 000100b; current source lock detect mode.
• Register 0x01B[7:0] = 0xF7; set REFMON pin to status of REF1 (active low).
• Register 0x01C[2:1] = 11b; enable REF1 and REF2 input buffers.
• Register 0x01D[3] = 1b; enable LD pin comparator.
• Register 0x01D[2]=1b; enable the holdover function.
• Register 0x01D[1] = 0b; use internal/automatic holdover mode.
• Register 0x01D[0] = 1b; enable the holdover function. (VCO calibration must be complete before this bit is enabled.)
• Connect REFMON pin to REFSEL pin. Frequency Status Monitors The AD9517 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency. A diagram showing their location in the PLL is shown in Figure 54. The VCO status frequency monitor is also capable of monitoring the CLK input if the CLK input is selected as the input to the N divider. The PLL reference frequency monitors have two threshold frequencies: normal and extended (see Table 16). The reference frequency monitor thresholds are selected in Register 0x01A. The frequency monitor status can be found in Register 0x01F, Bits[3:1].

Figure 54. Reference and VCO Status Monitors by returning a logic true (that is, 1b).

1. Program the PLL registers to the proper values for the PLL
2. Ensure that the input reference signal is present.
3. For the initial setting of the registers after a power-up or reset,

initiate VCO calibration by setting Register 0x018[0] = 1b. Register 0x018[0] = 1b, update registers.

1. A sync operation is initiated internally, causing the outputs
2. The VCO calibrates to the desired setting for the requested

which prevents unwanted frequencies from being produced. resume clocking before the PLL loop is completely settled. fREFIN is the frequency of the REFIN signal. R is the value of the R divider. The VCO calibration takes 4400 calibration clock cycles. Table 29. Example Time to Complete a VCO Calibration

• After changing any of the PLL R, P , B, and A divider settings, or after a change in the PLL reference clock frequency. This, in effect, means any time a PLL register or reference clock is changed such that a different VCO frequency results.
• Whenever system calibration is desired. The VCO is designed to operate properly over extremes of temperatures even when it is first calibrated at the opposite extreme. However, a VCO calibration can be initiated at any time, if desired. CLOCK DISTRIBUTION A clock channel consists of a pair (or double pair, in the case of CMOS) of outputs that share a common divider. A clock output consists of the drivers that connect to the output pins. The clock outputs have either LVPECL or LVDS/CMOS signal levels at the pins. The AD9517 has four clock channels: two channels are LVPECL (four outputs); two channels are LVDS/CMOS (up to four LVDS outputs or up to eight CMOS outputs). Each channel has its own programmable divider that divides the clock frequency that is applied to its input. The LVPECL channel dividers can divide by any integer from 2 to 32, or the divider can be bypassed to achieve a divide by one. Each LVDS/CMOS channel divider contains two of these divider blocks in a cascaded configuration. The total division of the channel is the product of the divide value of the cascaded dividers. This allows divide values of (1 to 32) × (1 to 32), or up to 1024 (note that this is not all values from 1 to 1024 but only the set of numbers that are the product of the two dividers). If the user wishes to use the channel dividers, the VCO divider must be used after the on-chip VCO. This is because the internal VCO frequency is above the maximum channel divider input frequency (1600 MHz). The VCO divider can be set to divide by 2, 3, 4, 5, or 6. External clock signals connected to the CLK input also require the VCO divider if the frequency of the signal is greater than 1600 MHz. The channel dividers allow for a selection of various duty cycles, depending on the currently set division. That is, for any specific division, D, the output of the divider can be set to high for N + 1 input clock cycles and low for M + 1 input clock cycles (where D = N + M + 2). For example, a divide-by-5 can be high for one divider input cycle and low for four cycles, or a divide- by-5 can be high for three divider input cycles and low for two cycles. Other combinations are also possible. The channel dividers include a du ty-cycle correction function that can be disabled. In contrast to the selectable duty cycle just described, this function can correct a non-50% duty cycle caused by an odd division. However, this requires that the division be set by M = N + 1. In addition, the channel dividers allow a coarse phase offset or delay to be set. Depending on the division selected, the output can be delayed by up to 31 input clock cycles. The divider outputs can also be set to start high or start low. Internal VCO or External CLK as Clock Source The clock distribution of the AD9517 has two clock input sources: an internal VCO or an external clock connected to the CLK/CLK pins. Either the internal VCO or CLK must be chosen as the source of the clock signal to distribute. When the internal VCO is selected as the source, the VCO divider must be used. When CLK is selected as the source, it is not necessary to use the VCO divider if the CLK frequency is less than the maximum channel divider input frequency (1600 MHz); otherwise, the VCO divider must be used to reduce the frequency to one acceptable by the channel dividers. Table 30 shows how the VCO, CLK, and VCO divider are selected. Register 0x1E1[1:0] selects the channel divider source and determines whether the VCO divider is used. It is not possible to select the VCO without using the VCO divider.

Table 30. Selecting VCO or CLK as Source for Channel be able to provide a full voltage swing at the highest frequencies.

distribution section, even if no channel uses it. source for the direct-to-output routing. Table 31. Settings for Routing VCO Divider Input Directly Table 32. Frequency Division for Divider 0 and Divider 1 Table 33. Frequency Division for Divider 2 and Divider 3 and control registers (see Table 52 through Table 62). to divide by 2, 3, 4, 5, or 6 (see Table 60, Register 0x1E0[2:0]). Each pair of LVPECL outputs is driven by a channel divider. Table 34. Setting D 1 Note that the value stored in the register = # of cycles minus 1. input of the channel dividers (VCO divider out or CLK). When a divider is bypassed, DX = 1. each channel divider to divide by any integer from 2 to 32.

• What are the M and N values for the channel?
• Is the DCC enabled?
• Is the VCO divider used?
• What is the CLK input duty cycle? (The internal VCO has a 50% duty cycle.) The DCC function is enabled by default for each channel divider. However, the DCC function can be disabled individually for each channel divider by setting the DCCOFF bit for that channel. Certain M and N values for a channel divider result in a non-50% duty cycle. A non-50% duty cycle can also result with an even division, if M ≠ N. The duty-cycle correction function automatically corrects non-50% duty cycles at the channel divider output to 50% duty cycle. Duty-cycle correction requires the following channel divider conditions:
• An even division must be set as M = N.
• An odd division must be set as M = N + 1. When not bypassed or corrected by the DCC function, the duty cycle of each channel divider output is the numerical value of (N + 1)/(N + M + 2), expressed as a percentage (%). The duty cycle at the output of the channel divider for various configurations is shown in Table 35 to Table 37.

Table 35. Duty Cycle with VCO Divider; Input Duty Cycle Is 50% Table 36. Duty Cycle with VCO Divider; Input Duty Cycle Is X% Table 37. Channel Divider Output Duty Cycle When the VCO is connected directly to the output, the duty cycle is 50%. the output is the same as the CLK input.

delay, to be programmed by setting register bits (see Table 38). (see the Synchronizing the Outputs—Sync Function section). Table 38. Setting Phase Offset and Division for Divider 0 and Δc = delay (in cycles of clock signal at input to DX). The channel divide-by is set as N = high cycles and M = low cycles. Figure 55. Effect of Coarse Phase Offset (or Delay) single-ended outputs, providing for up to eight CMOS outputs. disabled, if desired, by setting the DCCOFF bit of the channel. Table 39. Setting Division (DX) for Divider 2, Divider 31 1 Note that the value stored in the register = # of cycles minus 1. When both X.1 and X.2 are bypassed, DX = 1 × 1 = 1. When only X.2 is bypassed, DX = (NX.1 + MX.1 + 2) × 1. X.1 × DX.2) can be realized.

• An even DX.Y must be set as MX.Y = NX.Y (low cycles = high cycles).
• An odd DX.Y must be set as MX.Y = NX.Y + 1 (the number of low cycles must be one greater than the number of high cycles).
• If only one divider is bypassed, it must be the second divider, X.2.
• If only one divider has an even divide-by, it must be the second divider, X.2. The possibilities for the duty cycle of the output clock from Divider 2 and Divider 3 are shown in Table 40 through Table 44.

Table 40. Divider 2 and Divider 3 Duty Cycle; VCO Divider Table 41. Divider 2 and Divider 3 Duty Cycle; VCO Divider Table 42. Divider 2 and Divider 3 Duty Cycle; VCO Divider Table 43. Divider 2 and Divider 3 Duty Cycle; VCO Divider

Table 44. Divider 2 and Divider 3 Duty Cycle; VCO Divider phase offset and start high registers (see Table 45). Table 45. Setting Phase Offset and Division for Divider 2 and TX.1 = period of the clock signal at the input to DX.1 (in seconds). TX.2 = period of the clock signal at the input to DX.2 (in seconds). variable time delays (Δt) in the clock signal at that output. Figure 56. Fine Delay (OUT4 to OUT7) by programming four registers per output (see Table 46). Table 46. Setting Analog Fine Delays

Rev. E | Page 47 of 80 Calculating the Fine Delay The following values and equations are used to calculate the delay of the delay block. IRAMP (µA) = 200 × (Ramp Current + 1) Number of Capacitors = Number of Bits = 0 in Ramp Capacitors + 1 Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1. Delay Range (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) × 1.3286 RAMP RAMP I Caps ofNo.IOffset Delay Full Scale (ns) = Delay Range + Offset Fine Delay (ns) = Delay Range × Delay Fraction × (1/63) + Offset Note that only delay fraction values up to 47 decimal (101111b; 0x2F) are supported. In no case can the fine delay exceed one-half of the output clock period. If a delay longer than half of the clock period is attempted, the output stops clocking. The delay function adds some jitter that is greater than that specified for the nondelayed output. This means that the delay function should be used primarily for clocking digital chips, such as FPGA, ASIC, DUC, and DDC. An output with this delay enabled may not be suitable for clocking data converters. The jitter is higher for long full scales because the delay block uses a ramp and trip points to create the variable delay. A slower ramp time produces more time jitter. Synchronizing the Outputs—Sync Function The AD9517 clock outputs can be synchronized to each other. Outputs can be individually excluded from synchronization. Synchronization consists of setting the nonexcluded outputs to a preset set of static conditions and subsequently releasing these outputs to continue clocking at the same instant with the preset conditions applied. This allows for the alignment of the edges of two or more outputs or for the spacing of edges according to the coarse phase offset settings for two or more outputs. Synchronization of the outputs is executed in several ways, as follows:

• By forcing the SYNC pin low and then releasing it (manual sync).
• By setting and then resetting any one of the following three bits: the soft sync bit (Register 0x230[0]), the soft reset bit (Register 0x000[2] [mirrored]), and the power-down distribution reference bit (Register 0x230[1]).
• By executing synchronization of the outputs as part of the chip power-up sequence.
• By forcing the RESET pin low and then releasing it (chip reset).
• By forcing the PD pin low and then releasing it (chip power- down).
• Following completion of a VCO calibration. An internal SYNC signal is automatically asserted at the beginning of a VCO calibration and then released upon its completion. The most common way to execute the sync function is to use the SYNC pin to do a manual synchronization of the outputs. This requires a low-going signal on the SYNC pin, which is held low and then released when synchronization is desired. The timing of the sync operation is shown in Figure 57 (using VCO divider) and Figure 58 (VCO divider not used). There is an uncertainty of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9517. The delay from the SYNC rising edge to the beginning of synchronized output clocking is between 14 and 15 cycles of clock at the channel divider input, plus either one cycle of the VCO divider input (see Figure 57), or one cycle of the channel divider input (see Figure 58), depending on whether the VCO divider is used. Cycles are counted from the rising edge of the signal. Another common way to execute the sync function is by setting and resetting the soft sync bit at Register 0x230[0] (see Table 53 through Table 62 for details). Both the setting and resetting of the soft sync bit require an update all registers operation (Register 0x232[0] = 1) to take effect.

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

Figure 57. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

Figure 58. SYNC Timing When VCO Divider Is Not Used—CLK Input Only synchronization conditions apply to both outputs of a pair. any sync operation by setting the nosync bit of the channel. differential or as pairs of single-ended CMOS outputs.

Rev. E | Page 50 of 80 POWER-DOWN MODES Chip Power-Down via PD The AD9517 can be put into a power-down condition by pulling the PD pin low. Power-down turns off most of the functions and currents inside the AD9517. The chip remains in this power-down state until PD is brought back to logic high. When the AD9517 wakes up, it returns to the settings programmed into its registers prior to the power-down, unless the registers are changed by new programming while the PD pin is held low. The PD power-down shuts down the currents on the chip, except the bias current that is necessary to maintain the LVPECL outputs in a safe shutdown mode. This is needed to protect the LVPECL output circuitry from damage that could be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode. When the AD9517 is in a PD power-down, the chip is in the following state:

• The PLL is off (asynchronous power-down).
• The VCO is off.
• The CLK input buffer is off.
• All dividers are off.
• All LVDS/CMOS outputs are off.
• All LVPECL outputs are in safe off mode.
• The serial control port is active, and the chip responds to commands. If the AD9517 clock outputs must be synchronized to each other, a SYNC is required upon exiting power-down (see the Synchronizing the Outputs—Sync Function section). A VCO calibration is not required when exiting power-down. PLL Power-Down The PLL section of the AD9517 can be selectively powered down. There are three PLL operating modes set by Register 0x010[1:0], as shown in Table 54. In asynchronous power-down mode, the device powers down as soon as the registers are updated. In synchronous power-down mode, the PLL power-down is gated by the charge pump to prevent unwanted frequency jumps. The device goes into power-down on the occurrence of the next charge pump event after the registers are updated. Distribution Power-Down The distribution section can be powered down by writing Register 0x230[1] = 1b. This turns off the bias to the distribution section. If the LVPECL power-down mode is normal operation (00b), it is possible for a low impedance load on that LVPECL output to draw significant current during this power-down. If the LVPECL power-down mode is set to 11b, the LVPECL output is not protected from reverse bias and may be damaged under certain termination conditions. Individual Clock Output Power-Down Any of the clock distribution outputs can be powered down individually by writing to the appropriate registers. The register map details the individual power-down settings for each output (see Table 52). The LVDS/CMOS outputs can be powered down, regardless of their output load configuration. The LVPECL outputs have multiple power-down modes (see Table 56), which give some flexibility in dealing with the various output termination conditions. When the mode is set to 10b, the LVPECL output is protected from reverse bias to 2 VBE + 1 V . If the mode is set to 11b, the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions. This setting also affects the operation when the distribution block is powered down with Register 0x230[1] = 1b (see the Distribution Power-Down section). Individual Circuit Block Power-Down Other AD9517 circuit blocks (such as CLK, REF1, and REF2) can be powered down individually. This gives flexibility in configuring the part for power savings whenever certain chip functions are not needed.

instruction is the only instruction mode supported). SCLK (serial clock) is the serial shift clock. This pin is an input. pin is internally pulled down by a 30 kΩ resistor to ground. bidirectional I/O mode (Register 0x000[0] = 0b). Figure 62. Serial Control Port of data (plus instruction data) are transferred (see Table 47). high during either part (instruction or data) of the transfer. terminates the serial transfer and flushes the buffer. byte to be transferred, thereby ending the stream mode. There are two parts to a communication cycle with the AD9517. the first byte of the data transfer. AD9517. Data bits are registered on the rising edge of SCLK. data is written to blank registers. been written to the buffer since any previous update.

Figure 69. Serial Control Port Timing—Write Table 50. Serial Control Port Timing

Table 51. Thermal Parameters for the 48-Lead LFCSP TJ is the junction temperature (°C). ΨJT is the value from Table 51. PD is the power dissipation of the device (see Table 17). where TA is the ambient temperature (°C). design considerations when an external heat sink is required.

Table 52. Control Register Map Overview

Rev. E | Page 57 of 80 Reg. Addr. (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Fine Delay Adjust—OUT4 to OUT7 0x0A0 OUT4 delay bypass Blank OUT4 delay bypass 0x01 0x0A1 OUT4 delay full-scale Blank OUT4 ramp capacitors OUT4 ramp current 0x00 0x0A2 OUT4 delay fraction Blank OUT4 delay fraction 0x00 0x0A3 OUT5 delay bypass Blank OUT5 delay bypass 0x01 0x0A4 OUT5 delay full-scale Blank OUT5 ramp capacitors OUT5 ramp current 0x00 0x0A5 OUT5 delay fraction Blank OUT5 delay fraction 0x00 0x0A6 OUT6 delay bypass Blank OUT6 delay bypass 0x01 0x0A7 OUT6 delay full-scale Blank OUT6 ramp capacitors OUT6 ramp current 0x00 0x0A8 OUT6 delay fraction Blank OUT6 delay fraction 0x00 0x0A9 OUT7 delay bypass Blank OUT7 delay bypass 0x01 0x0AA OUT7 delay full-scale Blank OUT7 ramp capacitors OUT7 ramp current 0x00 0x0AB OUT7 delay fraction Blank OUT7 delay fraction 0x00 0x0AC to 0x0EF Blank LVPECL Outputs 0x0F0 OUT0 Blank OUT0 invert OUT0 LVPECL differential voltage OUT0 power-down 0x08 0x0F1 OUT1 Blank OUT1 invert OUT1 LVPECL differential voltage OUT1 power-down 0x0A 0x0F2, 0x0F3 Reserved 0x0F4 OUT2 Blank OUT2 invert OUT2 LVPECL differential voltage OUT2 power-down 0x08 0x0F5 OUT3 Blank OUT3 invert OUT3 LVPECL differential voltage OUT3 power-down 0x0A 0x0F6 to 0x13F Blank LVDS/CMOS Outputs 0x140 OUT4 OUT4 CMOS output polarity OUT4 LVDS/ CMOS output polarity OUT4 CMOS B OUT4 select LVDS/CMOS OUT4 LVDS output current OUT4 power-down 0x42 0x141 OUT5 OUT5 CMOS output polarity OUT5 LVDS/ CMOS output polarity OUT5 CMOS B OUT5 select LVDS/CMOS OUT5 LVDS output current OUT5 power-down 0x43 0x142 OUT6 OUT6 CMOS output polarity OUT6 LVDS/ CMOS output polarity OUT6 CMOS B OUT6 select LVDS/CMOS OUT6 LVDS output current OUT6 power-down 0x42 0x143 OUT7 OUT7 CMOS output polarity OUT7 LVDS/ CMOS output polarity OUT7 CMOS B OUT7 select LVDS/CMOS OUT7 LVDS output current OUT7 power-down 0x43 0x144 to 0x18F Blank

Rev. E | Page 58 of 80 Reg. Addr. (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) LVPECL Channel Dividers 0x190 Divider 0 (PECL) Divider 0 low cycles Divider 0 high cycles 0x00 0x191 Divider 0 bypass Divider 0 nosync Divider 0 force high Divider 0 start high Divider 0 phase offset 0x80 0x192 Blank Reserved Divider 0 direct to output Divider 0 DCCOFF 0x00 0x193 to 0x195 Reserved 0x196 Divider1 (PECL) Divider 1 low cycles Divider 1 high cycles 0x00 0x197 Divider 1 bypass Divider 1 nosync Divider 1 force high Divider 1 start high Divider 1 phase offset 0x00 0x198 Blank Reserved Divider 1 direct to output Divider 1 DCCOFF 0x00 LVDS/CMOS Channel Dividers 0x199 Divider 2 (LVDS/CMOS) Low Cycles Divider 2.1 High Cycles Divider 2.1 0x22 0x19A Phase Offset Divider 2.2 Phase Offset Divider 2.1 0x00 0x19B Low Cycles Divider 2.2 High Cycles Divider 2.2 0x11 0x19C Reserved Bypass Divider 2.2 Bypass Divider 2.1 Divider 2 nosync Divider 2 force high Start High Divider 2.2 Start High Divider 2.1 0x00 0x19D Blank Reserved Divider 2 DCCOFF 0x00 0x19E Divider 3 (LVDS/CMOS) Low Cycles Divider 3.1 High Cycles Divider 3.1 0x22 0x19F Phase Offset Divider 3.2 Phase Offset Divider 3.1 0x00 0x1A0 Low Cycles Divider 3.2 High Cycles Divider 3.2 0x11 0x1A1 Reserved Bypass Divider 3.2 Bypass Divider 3.1 Divider 3 nosync Divider 3 force high Start High Divider 3.2 Start High Divider 3.1 0x00 0x1A2 Blank Reserved Divider 3 DCCOFF 0x00 0x1A3 Reserved 0x1A4 to 0x1DF Blank VCO Divider and CLK Input 0x1E0 VCO divider Blank Reserved VCO Divider 0x02 0x1E1 Input CLKs Reserved Power down clock input section Power down VCO clock interface Power down VCO and CLK Select VCO or CLK Bypass VCO divider 0x00 0x1E2 to 0x22A Blank System 0x230 Power down and sync Reserved Power down sync Power down distribution reference Soft sync 0x00 0x231 Blank Reserved 0x00 Update All Registers 0x232 Update all registers Blank Update all registers (self- clearing bit) 0x00

address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2]. Table 53. Serial Port Configuration and Part ID 0: 8-bit instruction (short). 1: 16-bit instruction (long) (default). 0b to complete reset operation. 1 LSB first MSB or LSB data orientation. 0: data-oriented MSB first; addressing decrements (default). 1: data-oriented LSB first; addressing increments. 0 SDO active Selects unidirectional or bidirectional data transfer mode. 0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default). 1: SDO used for read, SDIO used for write; unidirectional mode. 0x004 0 Read back active registers Selects register bank used for a readback. 0: reads back buffer registers (default). 1: reads back active registers.

Table 54. PLL positive polarity; Bit 7 = 0b. 0: positive; higher control voltage produces higher frequency (default). 1: negative; higher control voltage produces lower frequency. [6:4] CP current Charge pump current (with CPRSET = 5.1 kΩ). [3:2] CP mode Charge pump operating mode. 0 1 Force source current (pump up). 1 0 Force sink current (pump down). 1 1 Normal operation (default). [1:0] PLL power-down PLL operating mode. 0 1 Asynchronous power-down (default). R divider LSBs—lower eight bits (default = 0x01). R divider MSBs—upper six bits (default = 0x00). 0x013 [5:0] 6-bit A counter A counter (part of N divider) (default = 0x00). B counter (part of N divider)—lower eight bits (default = 0x03). B counter (part of N divider)—upper five bits (default = 0x00). 0x016 7 Set CP pin to VCP/2 Sets the CP pin to one-half of the VCP supply voltage. 0: CP normal operation (default). 6 Reset R counter Resets R counter (R divider). 1: holds the R counter in reset. 5 Reset A, B counters Resets A and B counters (part of N divider). 1: holds the A and B counters in reset. 4 Reset all counters Resets R, A, and B counters. 1: holds the R, A, and B counters in reset. 3 B counter B counter bypass. This is valid only when operating the prescaler in FD mode. 1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.

Rev. E | Page 61 of 80 Reg. Addr. (Hex) Bits Name Description 0x016 [2:0] Prescaler P Prescaler: DM = dual modulus and FD = fixed divide. 2 1 0 Mode Prescaler 0 0 0 FD Divide-by-1. 0 0 1 FD Divide-by-2. 0 1 0 DM Divide-by-2 (2/3 mode). 0 1 1 DM Divide-by-4 (4/5 mode). 1 0 0 DM Divide-by-8 (8/9 mode). 1 0 1 DM Divide-by-16 (16/17 mode). 1 1 0 DM Divide-by-32 (32/33 mode) (default). 1 1 1 FD Divide-by-3. 0x017 [7:2] STATUS pin Selects the signal that is connected to the STATUS pin. control 7 6 5 4 3 2 Level or Dynamic Signal Signal at STATUS Pin 0 0 0 0 0 0 LVL Ground (dc) (default). 0 0 0 0 0 1 DYN N divider output (after the delay). 0 0 0 0 1 0 DYN R divider output (after the delay). 0 0 0 0 1 1 DYN A divider output. 0 0 0 1 0 0 DYN Prescaler output. 0 0 0 1 0 1 DYN PFD up pulse. 0 0 0 1 1 0 DYN PFD down pulse. 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXXb not specified above. The selections that follow are the same as REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status REF1 frequency (active high). 1 0 1 0 0 0 LVL Status REF2 frequency (active high). 1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of VCO frequency (active high). 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL Digital lock detect (DLD); active high. 1 0 1 1 1 0 LVL Holdover active (active high). 1 0 1 1 1 1 LVL LD pin comparator output (active high). 1 1 0 0 0 0 LVL VS (PLL supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 1 0 1 LVL Digital lock detect (DLD) (active low). 1 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 1 LVL LD pin comparator output (active low).

Rev. E | Page 62 of 80 Reg. Addr. (Hex) Bits Name Description 0x017 [1:0] Antibacklash 1 0 Antibacklash Pulse Width (ns) pulse width 0 0 2.9 (default). This is the recommended setting; it does not normally need to be changed. 0 1 1.3. This setting may be necessary if the PFD frequency > 50 MHz. 1 0 6.0. 1 1 2.9. 0x018 [6:5] Lock detect counter Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked condition. 6 5 PFD Cycles to Determine Lock 0 0 5 (default). 0 1 16. 1 0 64. 1 1 255.

4 Digital lock detect

If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold. 0: high range (default). 1: low range. 3 Disable digital Digital lock detect operation. lock detect 0: normal lock detect operation (default). 1: disables lock detect. [2:1] VCO cal divider VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock. 2 1 VCO Calibration Clock Divider 0 0 2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R. 0 1 4. This setting is fine for PFD frequencies < 25 MHz. 1 0 8. This setting is fine for PFD frequencies < 50 MHz. 1 1 16 (default). This setting is fine for any PFD frequency but also results in the longest VCO calibration time. 0 VCO cal now Bit used to initiate the VCO calibration. This bit must be toggled from 0b to 1b in the active registers. To initiate calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0b (if not zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1b, followed by another update bit (Register 0x232, Bit 0). Clearing this bit discards the VCO calibration and usually results in the PLL losing lock. The user must ensure that the holdover enable bits in Register 0x01D = 00b during VCO calibration. 0x019 [7:6] R, A, B counters 7 6 Action SYNC pin reset 0 0 Does nothing on SYNC (default). 0 1 Asynchronous reset. 1 0 Synchronous reset. 1 1 Does nothing on SYNC. [5:3] R path delay R path delay (default = 0x00) (see Table 2). [2:0] N path delay N path delay (default = 0x00) (see Table 2).

Rev. E | Page 63 of 80 Reg. Addr. (Hex) Bits Name Description 0x01A 6 Reference frequency monitor Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO frequency monitor’s detection threshold (see Table 16: REF1, REF2, and VCO frequency status monitor parameter). threshold 0: frequency valid if frequency is above the higher frequency threshold (default). 1: frequency valid if frequency is above the lower frequency threshold. [5:0] LD pin control Selects the signal that is connected to the LD pin. 5 4 3 2 1 0 Level or Dynamic Signal Signal at LD Pin 0 0 0 0 0 0 LVL Digital lock detect (high = lock, low = unlock) (default). 0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 1 HIZ High-Z LD pin. 0 0 0 1 0 0 CUR Current source lock detect (110 µA when DLD is true). 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXXb not specified above. The selections that follow are the same as REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when indifferential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status REF1 frequency (active high). 1 0 1 0 0 0 LVL Status REF2 frequency (active high). 1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of VCO frequency (active high). 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL Digital lock detect (DLD); active high. 1 0 1 1 1 0 LVL Holdover active (active high). 1 0 1 1 1 1 LVL Not available. Do not use. 1 1 0 0 0 0 LVL VS (PLL supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 1 0 1 LVL Digital lock detect (DLD); active low. 1 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 1 LVL Not available. Do not use.

Rev. E | Page 64 of 80 Reg. Addr. (Hex) Bits Name Description 0x01B 7 VCO Enables or disables VCO frequency monitor. frequency monitor 0: disables VCO frequency monitor (default). 1: enables VCO frequency monitor. 6 REF2 (REFIN) Enables or disables REF2 frequency monitor. frequency monitor 0: disables REF2 frequency monitor (default). 1: enables REF2 frequency monitor.

5 REF1 (REFIN)

REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs (as selected by differential reference mode). 0: disables REF1 (REFIN) frequency monitor (default). 1: enables REF1 (REFIN) frequency monitor. [4:0] REFMON Selects the signal that is connected to the REFMON pin. pin control 4 3 2 1 0 Level or Dynamic Signal Signal at REFMON Pin 0 0 0 0 0 LVL Ground (dc) (default). 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 0 0 0 1 0 DYN REF2 clock (not available in differential mode). 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 0 0 1 1 1 LVL Status REF1 frequency (active high). 0 1 0 0 0 LVL Status REF2 frequency (active high). 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 0 1 0 1 1 LVL Status of VCO frequency (active high). 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 0 1 1 0 1 LVL Digital lock detect (DLD); active low. 0 1 1 1 0 LVL Holdover active (active high). 0 1 1 1 1 LVL LD pin comparator output (active high). 1 0 0 0 0 LVL VS (PLL supply). 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 0 0 1 LVL (Status of REF1 frequency) AND (Status of REF2 frequency). 1 1 0 1 0 LVL (DLD) AND (Status of selected reference) AND (Status of VCO). 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 0 1 LVL Digital lock detect (DLD); active low. 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 LVL LD pin comparator output (active low). 0x01C 7 Disable Disables or enables the switchover deglitch circuit. switchover 0: enables switchover deglitch circuit (default). deglitch 1: disables switchover deglitch circuit. 6 Select REF2 If Register 0x01C, Bit 5 = 0b, selects reference for PLL. 0: selects REF1 (default). 1: selects REF2. 5 Use REF_SEL pin Sets method of PLL reference selection. 0: uses Register 0x01C, Bit 6 (default). 1: uses REF_SEL pin. [4:3] Reserved Reserved (default: 00b).

Rev. E | Page 65 of 80 Reg. Addr. (Hex) Bits Name Description 0x01C 2 REF2 power-on This bit turns the REF2 power on. 0: REF2 power off (default). 1: REF2 power on. 1 REF1 power-on This bit turns the REF1 power on. 0: REF1 power off (default). 1: REF1 power on.

0 Differential

Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic switchover between REF1 and REF2 to work. 0: single-ended reference mode (default). 1: differential reference mode. 0x01D 4 PLL status Disables the PLL status register readback. register disable 0: PLL status register enable (default). 1: PLL status register disable.

3 LD pin comparator

Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When in the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if the PLL was previously in a locked state (see Figure 53). Otherwise, this function can be used with the REFMON and STATUS pins to monitor the voltage on this pin. 0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true (high) (default). 1: enables LD pin comparator. 2 Holdover enable Along with Bit 0, enables the holdover function. Automatic holdover must be disabled during VCO calibration. 0: holdover disabled (default). 1: holdover enabled. 1 External Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.) holdover control 0: automatic holdover mode—holdover controlled by automatic holdover circuit. (default) 1: external holdover mode—holdover controlled by SYNC pin. 0 Holdover enable Along with Bit 2, enables the holdover function. Automatic holdover must be disabled during VCO calibration. 0: holdover disabled (default). 1: holdover enabled. 0x01F 6 VCO cal finished Read-only register: indicates status of the VCO calibration. 0: VCO calibration not finished. 1: VCO calibration finished. 5 Holdover active Read-only register: indicates if the part is in the holdover state (see Figure 53). This is not the same as holdover enabled. 0: not in holdover. 1: holdover state active. 4 REF2 selected Read-only register: indicates which PLL reference is selected as the input to the PLL. 0: REF1 selected (or differential reference if in differential mode). 1: REF2 selected.

3 VCO frequency >

Read-only register: indicates if the VCO frequency is greater than the threshold (see Table 16: REF1, REF2, and VCO frequency status monitor). 0: VCO frequency is less than the threshold. 1: VCO frequency is greater than the threshold.

2 REF2 frequency >

Read-only register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by Register 0x1A, Bit 6. 0: REF2 frequency is less than threshold frequency. 1: REF2 frequency is greater than threshold frequency.

1 REF1 frequency >

Read-only register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by Register 0x01A, Bit 6. 0: REF1 frequency is less than threshold frequency. 1: REF1 frequency is greater than threshold frequency. 0 Digital lock detect Read-only register: digital lock detect. 0: PLL is not locked. 1: PLL is locked.

Table 55. Fine Delay Adjust—OUT4 to OUT7 0x0A0 0 OUT4 delay bypass Bypasses or uses the delay function. 1: bypasses delay function (default). number of the capacitors and the ramp current sets the delay full scale. current sets the delay full scale. 0x0A2 [5:0] OUT4 delay fraction Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00). 0x0A3 0 OUT5 delay bypass Bypasses or uses the delay function. 1: bypasses delay function (default). number of the capacitors and the ramp current sets the delay full scale.

Rev. E | Page 67 of 80 Reg. Addr. (Hex) Bits Name Description 0x0A4 [2:0] OUT5 ramp current Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. 2 1 0 Current (µA) 0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0A5 [5:0] OUT5 delay fraction Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00). 0x0A6 0 OUT6 delay bypass Bypasses or uses the delay function. 0: uses delay function. 1: bypasses delay function (default). 0x0A7 [5:3] OUT6 ramp capacitors Selects the number of ramp capacitors used by the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. 5 4 3 Number of Capacitors 0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 [2:0] OUT6 ramp current Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. 2 1 0 Current (µA) 0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0A8 [5:0] OUT6 delay fraction Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00). 0x0A9 0 OUT7 delay bypass Bypasses or uses the delay function. 0: uses delay function. 1: bypasses delay function (default).

number of capacitors and the ramp current sets the delay full scale. current sets the delay full scale. 0x0AB [5:0] OUT7 delay fraction Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00). Table 56. LVPECL Outputs 0x0F0 4 OUT0 invert Sets the output polarity. [3:2] OUT0 LVPECL Sets the LVPECL output differential voltage (VOD). [1:0] OUT0 power-down LVPECL power-down modes. use only if there are no external load resistors. use only if there are no external load resistors.

Rev. E | Page 69 of 80 Reg. Addr. (Hex) Bits Name Description 0x0F1 4 OUT1 invert Sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] OUT1 LVPECL Sets the LVPECL output differential voltage (VOD). differential voltage 3 2 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 [1:0] OUT1 power-down LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation. On 0 1 Partial power-down, reference on; use only if there are no external load resistors. Off 1 0 Partial power-down, reference on, safe LVPECL power-down (default). Off 1 1 Total power-down, reference off; use only if there are no external load resistors. Off 0x0F4 4 OUT2 invert Sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] OUT2 LVPECL Sets the LVPECL output differential voltage (VOD). differential voltage 3 2 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 [1:0] OUT2 power-down LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation (default). On 0 1 Partial power-down, reference on; use only if there are no external load resistors. Off 1 0 Partial power-down, reference on, safe LVPECL power-down. Off 1 1 Total power-down, reference off; use only if there are no external load resistors. Off 0x0F5 4 OUT3 invert Sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] OUT3 LVPECL Sets the LVPECL output differential voltage (VOD). differential voltage 3 2 VOD (mV) 0 0 400 0 1 600 1 0 780 (default) 1 1 960 [1:0] OUT3 power-down LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation. On 0 1 Partial power-down, reference on; use only if there are no external load resistors. Off 1 0 Partial power-down, reference on, safe LVPECL power-down (default). Off 1 1 Total power-down, reference off; use only if there are no external load resistors. Off

Table 57. LVDS/CMOS Outputs 0x140 [7:5] OUT4 output polarity In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity. 4 OUT4 CMOS B In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode. 0: turns off the CMOS B output (default). 1: turns on the CMOS B output. 3 OUT4 select LVDS/CMOS Selects LVDS or CMOS logic levels. [2:1] OUT4 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode. 0 OUT4 power-down Powers down output (LVDS/CMOS). 0x141 [7:5] OUT5 output polarity In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity. 4 OUT5 CMOS B In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode. 0: turns off the CMOS B output (default). 1: turns on the CMOS B output. 3 OUT5 select LVDS/CMOS Selects LVDS or CMOS logic levels. [2:1] OUT5 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode.

Rev. E | Page 71 of 80 Reg. Addr. (Hex) Bits Name Description 0x141 0 OUT5 power-down Powers down output (LVDS/CMOS). 0: power on. 1: power off (default). 0x142 [7:5] OUT6 output polarity In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity. 7 6 5 OUT6A (CMOS) OUT6B (CMOS) OUT6 (LVDS) 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting (default) 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT6 CMOS B In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode. 0: turns off the CMOS B output (default). 1: turns on the CMOS B output. 3 OUT6 select LVDS/CMOS Selects LVDS or CMOS logic levels. 0: LVDS (default). 1: CMOS. [2:1] OUT6 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode. 2 1 Current (mA) Recommended Termination (Ω) 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 0 OUT6 power-down Powers down output (LVDS/CMOS). 0: power on (default). 1: power off. 0x143 [7:5] OUT7 output polarity In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity. 7 6 5 OUT7A (CMOS) OUT7B (CMOS) OUT7 (LVDS) 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting (default) 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT7 CMOS B In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode. 0: turns off the CMOS B output (default). 1: turns on the CMOS B output. 3 OUT7 select LVDS/CMOS Selects LVDS or CMOS logic levels. 0: LVDS (default). 1: CMOS.

0x143 [2:1] OUT7 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode. 0 OUT7 power-down Powers down output (LVDS/CMOS). Table 58. LVPECL Channel Dividers low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x191 7 Divider 0 bypass Bypasses and powers down the divider; routes input to divider output. 1: bypasses divider (default). 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 5 Divider 0 force high Forces divider output to high. This requires that nosync (Bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. 4 Divider 0 start high Selects clock output to start high or start low. [3:0] Divider 0 phase offset Phase offset (default = 0x0). 0x192 1 Divider 0 direct to output Connects OUT0 and OUT1 to Divider 0 or directly to VCO or CLK. 0: OUT0 and OUT1 are connected to Divider 0 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1. If Register 0x1E1[1:0] = 01b, there is no effect. 0 Divider 0 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x196 [7:4] Divider 1 low cycles Number of clock cycles of the divider input during which divider output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x197 7 Divider 1 bypass Bypasses and powers down the divider; routes input to divider output. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 5 Divider 1 force high Forces divider output to high. This requires that nosync (Bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high.

0x197 4 Divider 1 start high Selects clock output to start high or start low. [3:0] Divider 1 phase offset Phase offset (default = 0x0). 0x198 1 Divider 1 direct to output Connects OUT2 and OUT3 to Divider 2 or directly to VCO or CLK. 0: OUT2 and OUT3 are connected to Divider 1 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3. If Register 0x1E1[1:0] = 01b, there is no effect. 0 Divider 1 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Table 59. LVDS/CMOS Channel Dividers 0x199 [7:4] Low Cycles Divider 2.1 Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] High Cycles Divider 2.1 Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x19A [7:4] Phase Offset Divider 2.2 Refer to LVDS/CMOS channel divider function description (default = 0x0). [3:0] Phase Offset Divider 2.1 Refer to LVDS/CMOS channel divider function description (default = 0x0). 0x19B [7:4] Low Cycles Divider 2.2 Number of clock cycles (minus 1) of 2.2 divider input during which 2.2 output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] High Cycles Divider 2.2 Number of clock cycles (minus 1)of 2.2 divider input during which 2.2 output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x19C 5 Bypass Divider 2.2 Bypasses (and powers down) 2.2 divider logic, routes clock to 2.2 output. 0: does not bypass (default). 4 Bypass Divider 2.1 Bypasses (and powers down) 2.1 divider logic, routes clock to 2.1 output. 0: does not bypass (default). 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 2 Divider 2 force high Forces Divider 2 output high. Requires that nosync also be set. 1 Start High Divider 2.2 Divider 2.2 start high/low. 0 Start High Divider 2.1 Divider 2.1 start high/low. 0x19D 0 Divider 2 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x19E [7:4] Low Cycles Divider 3.1 Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] High Cycles Divider 3.1 Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

Rev. E | Page 74 of 80 Reg. Addr. (Hex) Bits Name Description 0x19F [7:4] Phase Offset Divider 3.2 Refer to LVDS/CMOS channel divider function description (default = 0x0). [3:0] Phase Offset Divider 3.1 Refer to LVDS/CMOS channel divider function description (default = 0x0). 0x1A0 [7:4] Low Cycles Divider 3.2 Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] High Cycles Divider 3.2 Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x1A1 5 Bypass Divider 3.2 Bypasses (and powers down) 3.2 divider logic; routes clock to 3.2 output. 0: does not bypass (default). 1: bypasses. 4 Bypass Divider 3.1 Bypasses (and powers down) 3.1 divider logic; routes clock to 3.1 output. 0: does not bypass (default). 1: bypasses. 3 Divider 3 nosync Nosync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 2 Divider 3 force high Forces Divider 3 output high. Requires that nosync also be set. 0: forces low (default). 1: forces high. 1 Start High Divider 3.2 Divider 3.2 start high/low. 0: starts low (default). 1: starts high. 0 Start High Divider 3.1 Divider 3.1 start high/low. 0: starts low (default). 1: starts high. 0x1A2 0 Divider 3 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction.

Table 60. VCO Divider and CLK Input 0x1E1 4 Power down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree). 0: normal operation (default). 3 Power down VCO clock interface Powers down the interface block between VCO and clock distribution. 0: normal operation (default). 2 Power down VCO and CLK Powers down both VCO and CLK input. 0; normal operation (default). 1 Select VCO or CLK Selects either the VCO or the CLK as the input to VCO divider. 0: selects external CLK as input to VCO divider (default). 1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected. 0 Bypass VCO divider Bypasses or uses the VCO divider. 0: uses VCO divider (default). 1: bypasses VCO divider; cannot select VCO as input when this is selected. Table 61. System 0x230 2 Power down sync Powers down the sync function. 0: normal operation of the sync function (default). 1: powers down sync circuitry. 1 Power down distribution reference Powers down the reference for distribution section. 0: normal operation of the reference for the distribution section (default). 1: powers down the reference for the distribution section.

0 Soft sync The soft sync bit works the same as the SYNC pin, except that the polarity of the bit

state, and a 1-to-0 transition triggers a sync. 0: same as SYNC high (default). Table 62. Update All Registers registers. This bit is self-clearing; that is, it does not have to be set back to 0b. 1 (self-clearing): updates all active registers to the contents of the buffer registers.

WITH EXCEPTION TO EXPOSED PAD DIMENSION.

0.80 MAX

0.65 TYP

5.50 REF

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.22 MIN

Figure 77. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. E | Page 80 of 80 NOTES ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06424-0-3/13(E)