AD9514BCPZ

AD9514 AD | Alldatasheet

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Technical content

1.6 GHz Clock Distribution IC,

Dividers, Delay Adjust, Three Outputs AD9514 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

FEATURES

1.6 GHz differential clock input

Divide-by in range from1 to 32 Phase select for coarse delay adjust 2 independent 1.6 GHz LVPECL clock outputs Additive broadband output jitter 225 fs rms 1 independent 800 MHz/250 MHz LVDS/CMOS clock output Additive broadband output jitter 300 fs rms/290 fs rms Time delays up to 10 ns Device configured with 4-level logic pins Space-saving, 32-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure ATE FUNCTIONAL BLOCK DIAGRAM VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 SETUP LOGIC OUT0 CLK CLKB SYNCB RSET VS GND OUT0B OUT1 OUT1B OUT2 OUT2B AD9514 /1. . . /32 /1. . . /32 /1. . . /32 Δt LVPECL LVPECL LVDS/CMOS 05596-001 Figure 1. GENERAL DESCRIPTION The AD9514 features a multi-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are three independent clock outputs. Two of the outputs are LVPECL, and the third output can be set to either LVDS or CMOS levels. The LVPECL outputs operate to 1.6 GHz, and the third output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode. Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to another clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment. The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment. The AD9514 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ V S. The VREF pin provides a level of ⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels. The AD9514 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9514 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C.

Rev. 0 | Page 2 of 28 TABLE OF CONTENTS Using the AD9514 Outputs for ADC Clock Applications.... 25 Power and Grounding Considerations and Power Supply

REVISION HISTORY

7/05—Revision 0: Initial Version

Rev. 0 | Page 3 of 28 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%, TA = 25°C, RSET = 4.12 kΩ, LVPECL VOD = 790 mV , unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. CLOCK INPUT Table 1. Parameter Min Typ Max Unit Test Conditions/Comments CLOCK INPUT (CLK) Input Frequency1 0 1.6 GHz Input Sensitivity1 150 mV p-p Input Common-Mode Voltage, VCM 1.5 1.6 1.7 V Self-biased; enables ac coupling Input Common-Mode Range, VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLKB ac-bypassed to RF ground Input Resistance 4.0 4.8 5.6 kΩ Self-biased Input Capacitance 2 pF 1 A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications. CLOCK OUTPUTS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V (OUT0, OUT1) Differential Output Frequency 0 1.6 GHz Output High Voltage (VOH) VS − 1.1 VS − 0.96 VS − 0.82 V Output Low Voltage (VOL) VS − 1.90 VS − 1.76 VS − 1.52 V Output Differential Voltage (VOD) 640 790 960 mV LVDS CLOCK OUTPUT Termination = 100 Ω differential (OUT2) Differential Output Frequency 0 800 MHz Differential Output Voltage (VOD) 250 350 450 mV Delta VOD 30 mV Output Offset Voltage (VOS) 1.125 1.23 1.375 V Delta VOS 25 mV Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND CMOS CLOCK OUTPUT Single-ended measurements; termination open (OUT2) Single-Ended Complementary output on (OUT2B) Output Frequency 0 250 MHz With 5 pF load Output Voltage High (VOH) VS − 0.1 V @ 1 mA load Output Voltage Low (VOL) 0.1 V @ 1 mA load

Rev. 0 | Page 4 of 28 TIMING CHARACTERISTICS CLK input slew rate = 1 V/ns or greater. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL Termination = 50 Ω to VS − 2 V Output Rise Time, tRP 60 100 ps 20% to 80%, measured differentially Output Fall Time, tFP 60 100 ps 80% to 20%, measured differentially PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT Divide = 1 355 480 635 ps Divide = 2 − 32 395 530 710 ps Variation with Temperature 0.5 ps/°C OUTPUT SKEW, LVPECL OUT0 to OUT1 on Same Part, tSKP1 −50 0 +55 ps Both LVPECL Outputs Across Multiple Parts, tSKP_AB2 125 ps Same LVPECL Output Across Multiple Parts, tSKP_AB2 125 ps LVDS Termination = 100 Ω differential, 3.5 mA Output Rise Time, tRL 200 350 ps 20% to 80%, measured differentially Output Fall Time, tFL 210 350 ps 80% to 20%, measured differentially PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT Optional delay off Divide = 1 1.00 1.25 1.55 ns Divide = 2 − 32 1.05 1.30 1.60 ns Variation with Temperature 0.9 ps/°C OUTPUT SKEW, LVDS Optional delay off LVDS Output Across Multiple Parts, tSKV_AB2 230 ps CMOS B outputs are inverted; termination = open Output Rise Time, tRC 650 865 ps 20% to 80%; CLOAD = 3 pF single-ended Output Fall Time, tFC 650 990 ps 80% to 20%; CLOAD = 3 pF single-ended PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT Optional delay off Divide = 1 1.10 1.45 1.75 ns Divide = 2 − 32 1.15 1.50 1.80 ns Variation with Temperature 1 ps/°C OUTPUT SKEW, CMOS Optional delay off CMOS Output Across Multiple Parts, tSKC_AB2 300 ps LVPECL-TO-LVDS OUT Output Delay, tSKV_C 560 790 950 ps LVPECL-TO-CMOS OUT Output Delay, tSKV_C 700 970 1150 ps DELAY ADJUST (OUT2; LVDS and CMOS) S0 = 1/3 Zero Scale Delay Time3 0.34 ns Zero Scale Variation with Temperature 0.20 ps/°C Full Scale Time Delay3 1.7 ns Full Scale Variation with Temperature −0.38 ps/°C S0 = 2/3 Zero Scale Delay Time3 0.45 ns Zero Scale Variation with Temperature 0.31 ps/°C Full Scale Time Delay3 5.9 ns Full Scale Variation with Temperature −1.3 ps/°C

Rev. 0 | Page 5 of 28 Parameter Min Typ Max Unit Test Conditions/Comments S0 = 1 Zero Scale Delay Time3 0.56 ns Zero Scale Variation with Temperature 0.47 ps/°C Full Scale Time Delay3 11.4 ns Full Scale Variation with Temperature −5 ps/°C Linearity, DNL 0.2 LSB Linearity, INL 0.2 LSB 1 This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature. 2 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature. 3 Incremental delay; does not include propagation delay. CLOCK OUTPUT PHASE NOISE CLK input slew rate = 1 V/ns or greater. Table 4. Parameter Min Typ Max Unit Test Conditions/Comments CLK-TO-LVPECL ADDITIVE PHASE NOISE CLK = 622.08 MHz, OUT = 622.08 MHz Divide = 1 @ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −148 dBc/Hz @ 100 kHz Offset −153 dBc/Hz >1 MHz Offset −154 dBc/Hz CLK = 622.08 MHz, OUT = 155.52 MHz Divide = 4 @ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −140 dBc/Hz @ 1 kHz Offset −148 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −161 dBc/Hz CLK = 622.08 MHz, OUT = 38.88 MHz Divide = 16 @ 10 Hz Offset −135 dBc/Hz @ 100 Hz Offset −145 dBc/Hz @ 1 kHz Offset −158 dBc/Hz @ 10 kHz Offset −165 dBc/Hz @ 100 kHz Offset −165 dBc/Hz >1 MHz Offset −166 dBc/Hz CLK = 491.52 MHz, OUT = 61.44 MHz Divide = 8 @ 10 Hz Offset −131 dBc/Hz @ 100 Hz Offset −142 dBc/Hz @ 1 kHz Offset −153 dBc/Hz @ 10 kHz Offset −160 dBc/Hz @ 100 kHz Offset −165 dBc/Hz >1 MHz Offset −165 dBc/Hz

Rev. 0 | Page 6 of 28 Parameter Min Typ Max Unit Test Conditions/Comments CLK = 491.52 MHz, OUT = 245.76 MHz Divide = 2 @ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −151 dBc/Hz @ 100 kHz Offset −157 dBc/Hz >1 MHz Offset −158 dBc/Hz CLK = 245.76 MHz, OUT = 61.44 MHz Divide = 4 @ 10 Hz Offset −138 dBc/Hz @ 100 Hz Offset −144 dBc/Hz @ 1 kHz Offset −154 dBc/Hz @ 10 kHz Offset −163 dBc/Hz @ 100 kHz Offset −164 dBc/Hz >1 MHz Offset −165 dBc/Hz CLK-TO-LVDS ADDITIVE PHASE NOISE CLK = 622.08 MHz, OUT= 622.08 MHz Divide = 1 @ 10 Hz Offset −100 dBc/Hz @ 100 Hz Offset −110 dBc/Hz @ 1 kHz Offset −118 dBc/Hz @ 10 kHz Offset −129 dBc/Hz @ 100 kHz Offset −135 dBc/Hz @ 1 MHz Offset −140 dBc/Hz >10 MHz Offset −148 dBc/Hz CLK = 622.08 MHz, OUT = 155.52 MHz Divide = 4 @ 10 Hz Offset −112 dBc/Hz @ 100 Hz Offset −122 dBc/Hz @ 1 kHz Offset −132 dBc/Hz @ 10 kHz Offset −142 dBc/Hz @ 100 kHz Offset −148 dBc/Hz @ 1 MHz Offset −152 dBc/Hz >10 MHz Offset −155 dBc/Hz CLK = 491.52 MHz, OUT = 245.76 MHz Divide = 2 @ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −154 dBc/Hz

Rev. 0 | Page 7 of 28 Parameter Min Typ Max Unit Test Conditions/Comments CLK = 491.52 MHz, OUT = 122.88 MHz Divide = 4 @ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −129 dBc/Hz @ 1 kHz Offset −136 dBc/Hz @ 10 kHz Offset −147 dBc/Hz @ 100 kHz Offset −153 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz CLK = 245.76 MHz, OUT = 245.76 MHz Divide = 1 @ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −155 dBc/Hz CLK = 245.76 MHz, OUT = 122.88 MHz Divide = 2 @ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −127 dBc/Hz @ 1 kHz Offset −137 dBc/Hz @ 10 kHz Offset −147 dBc/Hz @ 100 kHz Offset −154 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz CLK-TO-CMOS ADDITIVE PHASE NOISE CLK = 245.76 MHz, OUT = 245.76 MHz Divide = 1 @ 10 Hz Offset −110 dBc/Hz @ 100 Hz Offset −121 dBc/Hz @ 1 kHz Offset −130 dBc/Hz @ 10 kHz Offset −140 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −149 dBc/Hz >10 MHz Offset −156 dBc/Hz CLK = 245.76 MHz, OUT = 61.44 MHz Divide = 4 @ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −143 dBc/Hz @ 10 kHz Offset −152 dBc/Hz @ 100 kHz Offset −158 dBc/Hz @ 1 MHz Offset −160 dBc/Hz >10 MHz Offset −162 dBc/Hz

Rev. 0 | Page 8 of 28 Parameter Min Typ Max Unit Test Conditions/Comments CLK = 78.6432 MHz, OUT = 78.6432 MHz Divide = 1 @ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −155 dBc/Hz @ 1 MHz Offset −158 dBc/Hz >10 MHz Offset −160 dBc/Hz CLK = 78.6432 MHz, OUT = 39.3216 MHz Divide = 2 @ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −136 dBc/Hz @ 1 kHz Offset −146 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −162 dBc/Hz CLOCK OUTPUT ADDITIVE TIME JITTER Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER CLK = 622.08 MHz 40 fs rms BW = 12 kHz − 20 MHz LVPECL (OUT0 and OUT1) = 622.08 MHz OUT2 off Divide = 1 CLK = 622.08 MHz 55 fs rms BW = 12 kHz − 20 MHz LVPECL (OUT0 and OUT1) = 155.52 MHz OUT2 off Divide = 4 CLK = 400 MHz 215 fs rms Calculated from SNR of ADC method; LVPECL (OUT0 and OUT1) = 100 MHz OUT2 off Divide = 4 CLK = 400 MHz 215 fs rms Calculated from SNR of ADC method; LVPECL (OUT0, OUT1) = 100 MHz Other LVPECL and OUT2 LVDS at same frequency Divide = 4 CLK = 400 MHz 225 fs rms Calculated from SNR of ADC method; LVPECL (OUT0 or OUT1) = 100 MHz Divide = 4 Other LVPECL = 50 MHz Interferer LVDS (OUT2) = 50 MHz Interferer CLK = 400 MHz 230 fs rms Calculated from SNR of ADC method; LVPECL (OUT0 or OUT1) = 100 MHz Divide = 4 Other LVPECL = 50 MHz Interferer CMOS (OUT2) = 50 MHz Interferer LVDS OUTPUT ADDITIVE TIME JITTER Delay off CLK = 400 MHz 300 fs rms Calculated from SNR of ADC method; LVDS (OUT2) = 100 MHz OUT0 at same frequency; OUT1 off Divide = 4

Rev. 0 | Page 9 of 28 Parameter Min Typ Max Unit Test Conditions/Comments CLK = 400 MHz 350 fs rms Calculated from SNR of ADC method LVDS (OUT2) = 100 MHz Divide = 4 Both LVPECL = 50 MHz Interferer(s) CMOS OUTPUT ADDITIVE TIME JITTER Delay off CLK = 400 MHz 290 fs rms Calculated from SNR of ADC method CMOS (OUT2) = 100 MHz OUT0 at same frequency; OUT1 off Divide = 4 CLK = 400 MHz 315 fs rms Calculated from SNR of ADC method CMOS (OUT2) = 100 MHz Divide = 4 Both LVPECL = 50 MHz Interferer(s) DELAY BLOCK ADDITIVE TIME JITTER1 100 MHz output; incremental additive jitter Delay FS = 1.5 ns Fine Adj. 00000 0.71 ps rms Delay FS = 1.5 ns Fine Adj. 11111 1.2 ps rms Delay FS = 5 ns Fine Adj. 00000 1.3 ps rms Delay FS = 5 ns Fine Adj. 11111 2.7 ps rms Delay FS = 10 ns Fine Adj. 00000 2.0 ps rms Delay FS = 10 ns Fine Adj. 11111 2.8 ps rms 1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter should be added to this value using the root sum of the squares (RSS) method.

Rev. 0 | Page 10 of 28 SYNCB, VREF, AND SETUP PINS Table 6. Parameter Min Typ Max Unit Test Conditions/Comments SYNCB Logic High 2.7 V Logic Low 0.40 V Capacitance 2 pF VREF Output Voltage 0.62 VS 0.76 VS V Minimum − maximum from 0 mA to 1 mA load S0 TO S10 Levels 0 0.1 VS V 1/3 0.2 VS 0.45 VS V 2/3 0.55 VS 0.8 VS V 1 0.9 VS V POWER Table 7. Parameter Min Typ Max Unit Test Conditions/Comments POWER-ON SYNCHRONIZATION1 35 ms See Figure 24. VS Transit Time from 2.2 V to 3.1 V POWER DISSIP A TION 295 405 550 mW All outputs on. 2 LVPECL (divide = 2), 1 LVDS (divide = 2). No clock. Does not include power dissipated in external resistors. 380 490 635 mW All outputs on. 2 LVPECL (divide = 2), 1 CMOS (divide = 2); at 62.5 MHz out (5 pF load). 410 525 680 mW All outputs on. 2 LVPECL, 1 CMOS (divide = 2); At 125 MHz out (5 pF load). POWER DELTA Divider (Divide = 2 to Divide = 1) 15 30 45 mW For each divider. No clock. LVPECL Output 65 90 125 mW For each output. No clock. LVDS Output 20 50 85 mW No clock. CMOS Output (Static) 30 40 50 mW No clock. CMOS Output (@ 62.5 MHz) 80 110 140 mW Single-ended. At 62.5 MHz out with 5 pF load. CMOS Output (@ 125 MHz) 110 150 190 mW Single-ended. At 125 MHz out with 5 pF load. Delay Block 30 45 65 mW Off to 1.5 ns fs, delay word = 60; output clocking at 62.5 MHz. 1 This is the rise time of the VS supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs will not be synchronized.

Rev. 0 | Page 12 of 28 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter or Pin With Respect to Min Max Unit VS GND −0.3 +3.6 V RSET GND −0.3 VS + 0.3 V CLK GND −0.3 VS + 0.3 V CLK CLKB −1.2 +1.2 V OUT0, OUT1, OUT2 GND −0.3 VS + 0.3 V FUNCTION GND −0.3 VS + 0.3 V STATUS GND −0.3 VS + 0.3 V Junction Temperature1 150 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS2 Thermal Resistance 32-Lead LFCSP3 θJA = 36.6°C/W 1 See Thermal Characteristics for θ . JA

2 Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-7.

3 The external pad of this package must be soldered to adequate copper land

on board. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD pr ecautions are recommended to avoid performance degradation or loss of functionality.

2 CLK

3 CLKB

5 SYNCB

6 VREF

7 S10

18 OUT2B

19 OUT2

22 OUT1B

23 OUT1

Figure 6. 32-Lead LFCSP Pin Configuration Figure 7. Exposed Paddle Table 9. Pin Function Descriptions 3 CLKB Complementary Clock Input. 5 SYNCB Used to Synchronize Outputs; Do Not Let Float. 6 VREF Provides 2/3 VS for Use as One of the Four Logic Levels on S0 to S10. 7 to 16, 25 S10 to S0 Setup Select Pins. These are 4-state logic. The logic levels are VS, GND, 1/3 VS, and 2/3 VS. that logic level should be left no connection (NC). 18 OUT2B Complementary LVDS/Inverted CMOS Output. 22 OUT1B Complementary LVPECL Output. 27 OUT0B Complementary LVPECL Output. 31, Exposed Paddle GND Ground. The exposed paddle on the back of the chip is also GND. 32 RSET Current Sets Resistor to Ground. Nominal value = 4.12 kΩ.

Rev. 0 | Page 14 of 28 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although there are many causes that can contribute to phase jitter, one major component is due to random noise that is characterized statistically as being Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. It is also meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. For a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Since these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the SNR and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise It is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device affects the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contribute their own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. Additive Time Jitter It is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device will affect the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute their own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.

2 LVPECL (DIV ON)

2 LVPECL (DIV = 1)

Figure 8. Power vs. Frequency—LVPECL, LVDS Figure 9. CLK Smith Chart (Evaluation Board)

2 LVPECL (DIV ON) + 1 CMOS (DIV ON)

2 LVPECL (DIV OFF) + 1 CMOS (DIV OFF)

Figure 10. Power vs. Frequency—LVPECL, CMOS

16 levels of fine adjustment. The CLK and CLKB pins are differential clock input pins. between approximately 150 mV p-p to no more than 2 V p-p. turned on to ensure that the outputs start in synchronization. not divide = 1 are synchronized. Figure 24. Power-On Sync Timing outputs can be re-synchronized to each other at any time. in synchronicity (except where divide = 1).

3 CLK CYCLES 4 CLK CYCLES

Figure 25. SYNCB Timing with Clock Present

4 CLK CYCLES

Figure 26. SYNCB Timing with No Clock Present particular output’s divider. Figure 27. SYNCB Equivalent Input Circuit

after four input clock cycles.

• that are not turned OFF
• where the divider is not divide = 1 (divider bypassed) An output with its divider set to divide = 1 (divider bypassed) is always synchronized with the input clock, with a propagation delay. The SYNCB pin must be pulled up for normal operation. Do not let the SYNCB pin float. RSET RESISTOR The internal bias currents of the AD9514 are set by the RSET resistor. This resistor should be as close as possible to the value given as a condition in the Specifications section (RSET = 4.12 kΩ). This is a standard 1% resistor value and should be readily obtainable. The bias currents set by this resistor determine the logic levels and operating conditions of the internal blocks of the AD9514. The performance figures given in the Specifications section assume that this resistor value is used for RSET. VREF The VREF pin provides a voltage level of ⅔ VS. This voltage is one of the four logic levels used by the setup pins (S0 to S10). These pins set the operation of the AD9514. The VREF pin provides sufficient drive capability to drive as many of the setup pins as necessary, up to all on a single part. The VREF pin should be used for no other purpose. SETUP CONFIGURATION The specific operation of the AD9514 is set by the logic levels applied to the setup pins (S0 to S10). These pins use four-state logic. The logic levels used are VS and GND, plus ⅓ VS and ⅔ VS. The ⅓ VS level is provided by the internal self-biasing on each of the setup pins (S0 to S10). This is the level seen by a setup pin that is left not connected (NC). The ⅔ V S level is provided by the VREF pin. All setup pins requiring the ⅔ VS level must be tied to the VREF pin. SETUP PIN S0 TO S10 60kΩ 30kΩ VS 05596-023

Figure 28. Setup Pin (S0 to S10) Equivalent Circuit levels. See the setup pins thresholds in Table 6. to S4 sets the delay block fine adjust (fraction of full scale). powered down, including the divider. and 960 mV (limited to the available combinations, see Table 11). OUT2 can be set to either LVDS or CMOS levels. S7 and S8 set the phase word for OUT2.

Table 10. S0—OUT2 Delay

0 Off (Bypassed)

Table 11. S1, S2—Output Select Table 12. S3, S4—OUT2 Delay Fine Adjust or Phase

Table 13. S5, S6—OUT2 Divide or OUT1 Phase 1 Duty cycle is the clock signal high time divided by the total period. Table 14. S7, S8—OUT1 Divide or OUT2 Phase 1 Duty cycle is the clock signal high time divided by the total period. Table 15. S9, S10—OUT0 Divide or OUT2 Divide 1 Duty cycle is the clock signal high time divided by the total period.

LVDS CLOCK DISTRIBUTION Termination at the far end of the PCB trace is a second option. Figure 40. The trace lengths on less critical nets. Figure 40. CMOS Output with Far-End Termination provides superior performance for clocking converters. Figure 38. LVDS Output Termination following general guidelines should be used.

1.0 INCH

Figure 39. Series Termination of CMOS Output

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.80 SEATING

3.50 REF

0.60 MAX

0.25 MIN

Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the property of their respective owners.