AD9512

AD9511 1.2 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 48

Technical content

1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs AD9512 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2020 Analog Devices, Inc. All rights reserved.

FEATURES

Two 1.6 GHz, differential clock inputs 5 programmable dividers, 1 to 32, all integers Phase select for output-to-output coarse delay adjust 3 independent 1.2 GHz LVPECL outputs Additive output jitter 225 fs rms 2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 275 fs rms Fine delay adjust on 1 LVDS/CMOS output Serial control port Space-saving 48-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure FUNCTIONAL BLOCK DIAGRAM 05287-001 SYNC STATUS SYNC STATUS SCLK SDIO SDO CSB SERIAL CONTROL PORT FUNCTION SYNCB, RESETB PDB DSYNC DSYNCB DETECT SYNC VREF RSET AD9512 GNDVS CLK1 CLK1B CLK2 CLK2B PROGRAMMABLE DIVIDERS AND PHASE ADJUST OUT0 OUT0B LVPECL OUT1 OUT1B LVPECL OUT2 OUT2B LVPECL OUT3 OUT3B LVDS/CMOS OUT4 OUT4B LVDS/CMOS DELAY ADJUST Figure 1. GENERAL DESCRIPTION The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this part. There are five independent clock outputs. Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels. Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs features a programmable delay element with a range of up to 10 ns of delay. This fine tuning delay block has 5-bit resolution, giving 32 possible delays from which to choose. The AD9512 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9512 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. The temperature range is −40°C to +85°C.

Rev. B | Page 2 of 48 TABLE OF CONTENTS Power-On Reset—Start-Up Conditions when VS is Using the AD9512 Outputs for ADC Clock Applications ... 44

Rev. B | Page 3 of 48 Power and Grounding Considerations and Power Supply

REVISION HISTORY

9/2020—Rev. A to Rev. B 6/2005—Rev. 0 to Rev. A Changes to Chip Power-Down or Sleep Mode—PDB Section. 31 Changes to General Operation of Serial Added Framing a Communication Cycle with CSB Section .... 33 Added Communication Cycle—Instruction Plus 4/2005—Revision 0: Initial Version

Rev. B | Page 4 of 48 SPECIFICATIONS Typical (Typ) is given for VS = 3.3 V ± 5%; TA = 25°C, RSET = 4.12 kΩ, unless otherwise noted. Minimum (Min) and Maximum (Max) values are given over full VS and TA (−40°C to +85°C) variation. CLOCK INPUTS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments CLOCK INPUTS (CLK1, CLK2)1 Input Frequency 0 1.6 GHz Input Sensitivity 150 2 mV p-p Jitter performance can be improved with higher slew rates (greater swing). Input Level 2 3 V p-p Larger swings turn on the protection diodes and can degrade jitter performance. Input Common-Mode Voltage, VCM 1.5 1.6 1.7 V Self-biased; enables ac coupling. Input Common-Mode Range, VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled. Input Sensitivity, Single-Ended 150 mV p-p CL K2 ac-coupled; CLK2B ac bypassed to RF ground. Input Resistance 4.0 4.8 5.6 kΩ Self-biased. Input Capacitance 2 pF 1 CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input. 2 With a 50 Ω termination, this is −12.5 dBm. 3 With a 50 Ω termination, this is +10 dBm. CLOCK OUTPUTS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL CLOCK OUTPUTS Termination = 50 Ω to V S − 2 V OUT0, OUT1, OUT2; Differential O utput level 3Dh (3Eh) (3Fh)<3:2> = 10b Output Frequency 1200 MHz See Figure 14 Output High Voltage (VOH) V S − 1.22 V S − 0.98 V S − 0.93 V Output Low Voltage (VOL) V S − 2.10 V S − 1.80 V S − 1.67 V Output Differential Voltage (VOD) 660 810 965 mV LVDS CLOCK OUTPUTS Termination = 100 Ω differential; default OUT3, OUT4; Differential Output level 40h (41h)<2:1> = 01b 3.5 mA termination current Output Frequency 800 MHz See Figure 15 Differential Output Voltage (VOD) 250 360 450 mV Delta VOD 25 mV Output Offset Voltage (VOS) 1.125 1.23 1.375 V Delta VOS 25 mV Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND CMOS CLOCK OUTPUTS OUT3, OUT4 Single-ended measurements; B outputs: inverted, termination open Output Frequency 250 MHz With 5 pF load each output; see Figure 16 Output Voltage High (VOH) V S − 0.1 V @ 1 mA load Output Voltage Low (VOL) 0.1 V @ 1 mA load

Rev. B | Page 5 of 48 TIMING CHARACTERISTICS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL Termination = 50 Ω to VS − 2 V Output level 3Dh (3Eh) (3Fh)<3:2> = 10b Output Rise Time, tRP 130 180 ps 20% to 80%, measured differentially Output Fall Time, tFP 130 180 ps 80% to 20%, measured differentially PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT1 Divide = Bypass 335 490 635 ps Divide = 2 − 32 375 545 695 ps Variation with Temperature 0.5 ps/°C OUTPUT SKEW, LVPECL OUTPUTS OUT1 to OUT0 on Same Part, tSKP2 70 100 140 ps OUT1 to OUT2 on Same Part, tSKP2 15 45 80 ps OUT0 to OUT2 on Same Part, tSKP2 45 65 90 Ps All LVPECL OUT Across Multiple Parts, tSKP_AB3 275 ps Same LVPECL OUT Across Multiple Parts, tSKP_AB3 130 ps LVDS Termination = 100 Ω differential Output level 40h (41h) <2:1> = 01b 3.5 mA termination current Output Rise Time, tRL 200 350 ps 20% to 80%, measured differentially Output Fall Time, tFL 210 350 ps 80% to 20%, measured differentially PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT1 Delay off on OUT4 OUT3 to OUT4 Divide = Bypass 0.99 1.33 1.59 ns Divide = 2 − 32 1.04 1.38 1.64 ns Variation with Temperature 0.9 ps/°C OUTPUT SKEW, LVDS OUTPUTS Delay off on OUT4 OUT3 to OUT4 on Same Part, tSKV2 −85 +270 ps All LVDS OUTs Across Multiple Parts, tSKV_AB3 450 ps Same LVDS OUT Across Multiple Parts, tSKV_AB3 325 ps CMOS B outputs are inverted; termination = open Output Rise Time, tRC 681 865 ps 20% to 80%; C LOAD = 3 pF Output Fall Time, tFC 646 992 ps 80% to 20%; C LOAD = 3 pF PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT1 Delay off on OUT4 Divide = Bypass 1.02 1.39 1.71 ns Divide = 2 − 32 1.07 1.44 1.76 ns Variation with Temperature 1 ps/°C OUTPUT SKEW, CMOS OUTPUTS Delay off on OUT4 OUT3 to OUT4 on Same Part, tSKC2 −140 +145 +300 All CMOS OUT Across Multiple Parts, tSKC_AB3 650 ps Same CMOS OUT Across Multiple Parts, tSKC_AB3 500 ps LVPECL-TO-LVDS OUT Everythin g the same; different logic type Output Skew, tSKP_V 0.74 0.92 1.14 ns LVPECL to LVDS on same part LVPECL-TO-CMOS OUT Everythin g the same; different logic type Output Skew, tSKP_C 0.88 1.14 1.43 ns LVPECL to CMOS on same part LVDS-TO-CMOS OUT Everything the same; different logic type Output Skew, tSKV_C 158 353 506 ps LVDS to CMOS on same part

Rev. B | Page 6 of 48 Parameter Min Typ Max Unit Test Conditions/Comments DELAY ADJUST OUT4; LVDS and CMOS Shortest Delay Range4 35h <5:1> 11111b Zero Scale 0.05 0.36 0.68 ns 36h <5:1> 00000b Full Scale 0.72 1.12 1.51 ns 36h <5:1> 11111b Linearity, DNL 0.5 LSB Linearity, INL 0.8 LSB Longest Delay Range4 35h <5:1> 00000b Zero Scale 0.20 0.57 0.95 ns 36h <5:1> 00000b Full Scale 9.0 10.2 11.6 ns 36h <5:1> 11111b Linearity, DNL 0.3 LSB Linearity, INL 0.6 LSB Delay Variation with Temperature Long Delay Range, 10 ns5 Zero Scale 0.35 ps/°C Full Scale −0.14 ps/°C Short Delay Range, 1 ns5 Zero Scale 0.51 ps/°C Full Scale 0.67 ps/°C 1 The measurements are for CLK1. For CLK2, add approximately 25 ps. 2 This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature. 3 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature. 4 Incremental delay; does not include propagation delay. 5 All delays between the zero scale and full scale can be estimated by linear interpolation.

Rev. B | Page 7 of 48 CLOCK OUTPUT PHASE NOISE Table 4. Parameter Min Typ Max Unit Test Conditions/Comments CLK1-TO-LVPECL ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Input slew rate > 1 V/ns Divide Ratio = 1 @ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −148 dBc/Hz @ 100 kHz Offset −153 dBc/Hz >1 MHz Offset −154 dBc/Hz CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −140 dBc/Hz @ 1 kHz Offset −148 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −161 dBc/Hz CLK1 = 622.08 MHz, OUT = 38.88 MHz Divide Ratio = 16 @ 10 Hz Offset −135 dBc/Hz @ 100 Hz Offset −145 dBc/Hz @ 1 kHz Offset −158 dBc/Hz @ 10 kHz Offset −165 dBc/Hz @ 100 kHz Offset −165 dBc/Hz >1 MHz Offset −166 dBc/Hz CLK1 = 491.52 MHz, OUT = 61.44 MHz Divide Ratio = 8 @ 10 Hz Offset −131 dBc/Hz @ 100 Hz Offset −142 dBc/Hz @ 1 kHz Offset −153 dBc/Hz @ 10 kHz Offset −160 dBc/Hz @ 100 kHz Offset −165 dBc/Hz >1 MHz Offset −165 dBc/Hz CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −151 dBc/Hz @ 100 kHz Offset −157 dBc/Hz >1 MHz Offset −158 dBc/Hz CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset −138 dBc/Hz @ 100 Hz Offset −144 dBc/Hz @ 1 kHz Offset −154 dBc/Hz @ 10 kHz Offset −163 dBc/Hz @ 100 kHz Offset −164 dBc/Hz >1 MHz Offset −165 dBc/Hz

Rev. B | Page 8 of 48 Parameter Min Typ Max Unit Test Conditions/Comments CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset −100 dBc/Hz @ 100 Hz Offset −110 dBc/Hz @ 1 kHz Offset −118 dBc/Hz @ 10 kHz Offset −129 dBc/Hz @ 100 kHz Offset −135 dBc/Hz @ 1 MHz Offset −140 dBc/Hz >10 MHz Offset −148 dBc/Hz CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset −112 dBc/Hz @ 100 Hz Offset −122 dBc/Hz @ 1 kHz Offset −132 dBc/Hz @ 10 kHz Offset −142 dBc/Hz @ 100 kHz Offset −148 dBc/Hz @ 1 MHz Offset −152 dBc/Hz >10 MHz Offset −155 dBc/Hz CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −154 dBc/Hz CLK1 = 491.52 MHz, OUT = 122.88 MHz Divide Ratio = 4 @ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −129 dBc/Hz @ 1 kHz Offset −136 dBc/Hz @ 10 kHz Offset −147 dBc/Hz @ 100 kHz Offset −153 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −155 dBc/Hz

Rev. B | Page 9 of 48 Parameter Min Typ Max Unit Test Conditions/Comments CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 @ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −127 dBc/Hz @ 1 kHz Offset −137 dBc/Hz @ 10 kHz Offset −147 dBc/Hz @ 100 kHz Offset −154 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz CLK1-TO-CMOS ADDITIVE PHASE NOISE CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset −110 dBc/Hz @ 100 Hz Offset −121 dBc/Hz @ 1 kHz Offset −130 dBc/Hz @ 10 kHz Offset −140 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −149 dBc/Hz > 10 MHz Offset −156 dBc/Hz CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −143 dBc/Hz @ 10 kHz Offset −152 dBc/Hz @ 100 kHz Offset −158 dBc/Hz @ 1 MHz Offset −160 dBc/Hz >10 MHz Offset −162 dBc/Hz CLK1 = 78.6432 MHz, OUT = 78.6432 MHz Divide Ratio = 1 @ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −155 dBc/Hz @ 1 MHz Offset −158 dBc/Hz >10 MHz Offset −160 dBc/Hz CLK1 = 78.6432 MHz, OUT = 39.3216 MHz Divide Ratio = 2 @ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −136 dBc/Hz @ 1 kHz Offset −146 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −162 dBc/Hz

Rev. B | Page 10 of 48 CLOCK OUTPUT ADDITIVE TIME JITTER Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz 40 fs rms BW = 12 kHz − 20 MHz (OC-12) Any LVPECL (OUT0 to OUT2) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz 55 fs rms BW = 12 kHz − 20 MHz (OC-3) Any LVPECL (OUT0 to OUT2) = 155.52 MHz Divide Ratio = 4 CLK1 = 400 MHz 215 fs rms Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz 215 fs rms Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 100 MHz Interferer(s) Both LVDS (OUT3, OUT4) = 100 MHz Interferer(s) CLK1 = 400 MHz 222 fs rms Calculated from SNR of ADC method; F C = 100 MHz with AIN = 170 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both LVDS (OUT3, OUT4) = 50 MHz Interferer(s) CLK1 = 400 MHz 225 fs rms Calculated from SNR of ADC method; F C = 100 MHz with AIN = 170 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off) Interferer(s) CLK1 = 400 MHz 225 fs rms Calculated from SNR of ADC method; F C = 100 MHz with AIN = 170 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On) Interferer(s) LVDS OUTPUT ADDITIVE TIME JITTER CLK1 = 400 MHz 264 fs rms Calculated from SNR of ADC method; F C = 100 MHz with AIN = 170 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz 319 fs rms Calculated from SNR of ADC method; F C = 100 MHz with AIN = 170 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz 395 fs rms Calculated from SNR of ADC method; F C = 100 MHz with AIN = 170 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 LVDS (OUT4) = 50 MHz Interferer(s) All LVPECL = 50 MHz Interferer(s)

Rev. B | Page 11 of 48 Parameter Min Typ Max Unit Test Conditions/Comments CLK1 = 400 MHz 395 fs rms Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 LVDS (OUT3) = 50 MHz Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 367 fs rms Calculated from SNR of ADC method; F C = 100 MHz with AIN = 170 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs Off) Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 367 fs rms Calculated from SNR of ADC method; F C = 100 MHz with AIN = 170 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs Off) Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 548 fs rms Calculated from SNR of ADC method; F C = 100 MHz with AIN = 170 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs On) Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 548 fs rms Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs On) Interferer(s) All LVPECL = 50 MHz Interferer(s) CMOS OUTPUT ADDITIVE TIME JITTER CLK1 = 400 MHz 275 fs rms Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Both CMOS (OUT3, OUT4) = 100 MHz (B Output On) Divide Ratio = 4 CLK1 = 400 MHz 400 fs rms Calculated from SNR of ADC method; F C = 100 MHz with AIN = 170 MHz CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) LVDS (OUT4) = 50 MHz Interferer(s) CLK1 = 400 MHz 374 fs rms Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) CMOS (OUT4) = 50 MHz (B Output Off) Interferer(s) CLK1 = 400 MHz 555 fs rms Calculated from SNR of ADC method; F C = 100 MHz with AIN = 170 MHz CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) CMOS (OUT4) = 50 MHz (B Output On) Interferer(s)

Rev. B | Page 12 of 48 Parameter Min Typ Max Unit Test Conditions/Comments DELAY BLOCK ADDITIVE TIME JITTER1 Incremental additive jitter 1

100 MHz Output

Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 00000 0.61 ps Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 11111 0.73 ps Delay FS = 2 ns (800 μA, 1C) Fine Adj. 00000 0.71 ps Delay FS = 2 ns (800 μA, 1C) Fine Adj. 11111 1.2 ps Delay FS = 3 ns (800 μA, 4C) Fine Adj. 00000 0.86 ps Delay FS = 3 ns (800 μA, 4C) Fine Adj. 11111 1.8 ps Delay FS = 4 ns (400 μA, 4C) Fine Adj. 00000 1.2 ps Delay FS = 4 ns (400 μA, 4C) Fine Adj. 11111 2.1 ps Delay FS = 5 ns (200 μA, 1C) Fine Adj. 00000 1.3 ps Delay FS = 5 ns (200 μA, 1C) Fine Adj. 11111 2.7 ps Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00000 2.0 ps Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00100 2.8 ps 1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter should be added to this value using the root sum of the squares (RSS) method. SERIAL CONTROL PORT Table 6. Parameter Min Typ Max Unit Test Conditions/Comments CSB, SCLK (INPUTS) CSB and SCLK have 30 kΩ internal pull-down resistors Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF SDIO (WHEN INPUT) Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 10 nA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V TIMING Clock Rate (SCLK, 1/tSCLK) 25 MHz Pulse Width High, tPWH 16 ns Pulse Width Low, tPWL 16 ns SDIO to SCLK Setup, tDS 2 ns SCLK to SDIO Hold, tDH 1 ns SCLK to Valid SDIO and SDO, tDV 6 ns CSB to SCLK Setup and Hold, tS, tH 2 ns CSB Minimum Pulse Width High, tPWH 3 ns

Rev. B | Page 13 of 48 FUNCTION PIN Table 7. Parameter Min Typ Max Unit Test Conditions/Comments INPUT CHARACTERISTICS The FUNCTION pin has a 30 kΩ internal pull-down resistor. This pin should normally be held high. Do not leave NC. Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 110 μA Logic 0 Current 1 μA Capacitance 2 pF RESET TIMING Pulse Width Low 50 ns SYNC TIMING Pulse Width Low 1.5 High speed clock cycles High speed clock is CLK1 or CLK2, whichever is being used for distribution. SYNC STATUS PIN Table 8. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT CHARACTERISTICS Output Voltage High (VOH) 2.7 V Output Voltage Low (VOL) 0.4 V

Rev. B | Page 14 of 48 POWER Table 9. Parameter Min Typ Max Unit Test Conditions/Comments POWER-UP DEFAULT MODE POWER DISSIPATION 550 600 mW Power-up default state; does not include power dissipated in output load resistors. No clock. POWER DISSIPATION 800 mW All outputs on. Three LVPECL outputs @ 800 MHz, two CMOS out @ 62 MHz (5 pF load). Does not include power dissipated in external resistors. 850 mW All outputs on. Three LVPECL outputs @ 800 MHz, two CMOS out @ 125 MHz (5 pF load). Does not include power dissipated in external resistors. Full Sleep Power-Down 35 60 mW Maximum sleep is entered by setting 0Ah<1:0> = 01b and 58h<4> = 1b. This powers off all band gap references. Does not include power dissipated in terminations. Power-Down (PDB) 60 80 mW Set FUNCTION pin for PDB operation by setting 58h<6:5> = 11b. Pull PDB low. Does not include power dissipated in terminations. POWER DELTA CLK1, CLK2 Power-Down 10 15 25 mW Divider, DIV 2 − 32 to Bypass 23 27 33 mW For each divider. LVPECL Output Power-Down (PD2, PD3) 50 65 75 mW For each output. Does not include dissipation in termination (PD2 only). LVDS Output Power-Down 80 92 110 mW For each output. CMOS Output Power-Down (Static) 56 70 85 mW For each output. Static (no clock). CMOS Output Power-Down (Dynamic) 115 150 190 mW For each CMOS output, single-ended. Clocking at 62 MHz with 5 pF load. CMOS Output Power-Down (Dynamic) 125 165 210 mW For each CMOS output, single-ended. Clocking at 125 MHz with 5 pF load. Delay Block Bypass 20 24 60 mW Vs. delay block operation at 1 ns fs with maximum delay; output clocking at 25 MHz.

Rev. B | Page 16 of 48 ABSOLUTE MAXIMUM RATINGS Table 10. Parameter or Pin With Respect to Min Max Unit VS GND −0.3 +3.6 V DSYNC/DSYNCB GND −0.3 V S + 0.3 V RSET GND −0.3 VS + 0.3 V CLK1, CLK1B, CLK2, CLK2B GND −0.3 V S + 0.3 V CLK1 CLK1B −1.2 +1.2 V CLK2 CLK2B −1.2 +1.2 V SCLK, SDIO, SDO, CSB GND −0.3 V S + 0.3 V OUT0, OUT1, OUT2, OUT3, OUT4 GND −0.3 V S + 0.3 V FUNCTION GND −0.3 VS + 0.3 V SYNC STATUS GND −0.3 V S + 0.3 V Junction Temperature 150 °C Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance1 48-Lead LFCSP θJA = 28.5°C/W

1 Thermal impedance measurements were taken on a 4-layer board in still air,

in accordance with EIA/JESD51-7. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

1. THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION

PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND, GND. Figure 6. 48-Lead LFCSP Pin Configuration function properly, the paddle must be attached to ground, GND.

Table 11. Pin Function Descriptions 1 DSYNC Detect Sync. Used for multichip synchronization. 2 DSYNCB Detect Sync Complement. Us ed for multichip synchronization. 8 CLK2B Complementary Clock Input. Used in conjunction with CLK2. 11 CLK1B Complementary Clock Input. Used in conjunction with CLK1. 12 FUNCTION Multipurpose Input. Can be programmed as a re set (RESETB), sync (SYNCB), or power-down (PDB) pin. 13 STATUS Output Used to Monitor the Status of Multichip Synchronization. 17 CSB Serial Port Chip Select. 20 OUT2B Complementary LVPECL Output. 26 OUT1B Complementary LVPECL Output. 30 OUT4B Complementary LVDS/Inverted CMOS Output. OUT4 includes a delay block. 31 OUT4 LVDS/CMOS Output. OUT4 includes a delay block. 34 OUT3B Complementary LVDS/Inverted CMOS Output. 41 OUT0B Complementary LVPECL Output. 45 RSET Current Set Resistor to Ground. Nominal value = 4.12 kΩ. function properly, the paddle must be attached to ground, GND.

Rev. B | Page 19 of 48 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 degrees to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. In a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Since these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the SNR and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise It is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contribute their own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. Additive Time Jitter It is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device will impact the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute their own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.

3 LVPECL (DIV ON) 2 LVDS (DIV ON)

3 LVPECL + 2 LVDS (DIV BYPASSED)

Figure 7. Power vs. Frequency—LVPECL, LVDS Figure 8. CLK1 Smith Chart (Evaluation Board)

3 LVPECL + 2 CMOS (DIV ON)

Figure 9. Power vs. Frequency—LVPECL, CMOS Figure 10. CLK2 Smith Chart (Evaluation Board)

Figure 23. Functional Block Diagram Showing Maximum Frequencies

it is powered down to save power. ratio of 1 is selected by bypassing the divider. depend on the divide ratio that is chosen. value is 4 bits and has the range of 0 to 15. ratio, the resulting duty cycle is not the same. Ratio = 4, the duty cycle can be 25%, 50%, or 75%. Table 12. Duty Cycle and Divide Ratio

Rev. B | Page 26 of 48 Divide Ratio Duty Cycle (%) 4Ah to 52h LO<7:4> HI<3:0> 9 67 2 5 9 33 5 2 9 78 1 6 9 22 6 1 9 89 0 7 9 11 7 0 10 50 4 4 10 60 3 5 10 40 5 3 10 70 2 6 10 30 6 2 10 80 1 7 10 20 7 1 10 90 0 8 10 10 8 0 11 55 4 5 11 45 5 4 11 64 3 6 11 36 6 3 11 73 2 7 11 27 7 2 11 82 1 8 11 18 8 1 11 91 0 9 11 9 9 0 12 50 5 5 12 58 4 6 12 42 6 4 12 67 3 7 12 33 7 3 12 75 2 8 12 25 8 2 12 83 1 9 12 17 9 1 12 92 0 A 12 8 A 0 13 54 5 6 13 46 6 5 13 62 4 7 13 38 7 4 13 69 3 8 13 31 8 3 13 77 2 9 13 23 9 2 13 85 1 A 13 15 A 1 13 92 0 B 13 8 B 0 14 50 6 6 14 57 5 7 14 43 7 5 Divide Ratio Duty Cycle (%) 4Ah to 52h LO<7:4> HI<3:0> 14 64 4 8 14 36 8 4 14 71 3 9 14 29 9 3 14 79 2 A 14 21 A 2 14 86 1 B 14 14 B 1 14 93 0 C 14 7 C 0 15 53 6 7 15 47 7 6 15 60 5 8 15 40 8 5 15 67 4 9 15 33 9 4 15 73 3 A 15 27 A 3 15 80 2 B 15 20 B 2 15 87 1 C 15 13 C 1 15 93 0 D 15 7 D 0 16 50 7 7 16 56 6 8 16 44 8 6 16 63 5 9 16 38 9 5 16 69 4 A 16 31 A 4 16 75 3 B 16 25 B 3 16 81 2 C 16 19 C 2 16 88 1 D 16 13 D 1 16 94 0 E 16 6 E 0 17 53 7 8 17 47 8 7 17 59 6 9 17 41 9 6 17 65 5 A 17 35 A 5 17 71 4 B 17 29 B 4 17 76 3 C 17 24 C 3 17 82 2 D 17 18 D 2

Rev. B | Page 27 of 48 Divide Ratio Duty Cycle (%) 4Ah to 52h LO<7:4> HI<3:0> 17 88 1 E 17 12 E 1 17 94 0 F 17 6 F 0 18 50 8 8 18 56 7 9 18 44 9 7 18 61 6 A 18 39 A 6 18 67 5 B 18 33 B 5 18 72 4 C 18 28 C 4 18 78 3 D 18 22 D 3 18 83 2 E 18 17 E 2 18 89 1 F 18 11 F 1 19 53 8 9 19 47 9 8 19 58 7 A 19 42 A 7 19 63 6 B 19 37 B 6 19 68 5 C 19 32 C 5 19 74 4 D 19 26 D 4 19 79 3 E 19 21 E 3 19 84 2 F 19 16 F 2 20 50 9 9 20 55 8 A 20 45 A 8 20 60 7 B 20 40 B 7 20 65 6 C 20 35 C 6 20 70 5 D 20 30 D 5 20 75 4 E 20 25 E 4 20 80 3 F 20 20 F 3 21 52 9 A 21 48 A 9 21 57 8 B 21 43 B 8 21 62 7 C Divide Ratio Duty Cycle (%) 4Ah to 52h LO<7:4> HI<3:0> 21 38 C 7 21 67 6 D 21 33 D 6 21 71 5 E 21 29 E 5 21 76 4 F 21 24 F 4 22 50 A A 22 55 9 B 22 45 B 9 22 59 8 C 22 41 C 8 22 64 7 D 22 36 D 7 22 68 6 E 22 32 E 6 22 73 5 F 22 27 F 5 23 52 A B 23 48 B A 23 57 9 C 23 43 C 9 23 61 8 D 23 39 D 8 23 65 7 E 23 35 E 7 23 70 6 F 23 30 F 6 24 50 B B 24 54 A C 24 46 C A 24 58 9 D 24 42 D 9 24 63 8 E 24 38 E 8 24 67 7 F 24 33 F 7 25 52 B C 25 48 C B 25 56 A D 25 44 D A 25 60 9 E 25 40 E 9 25 64 8 F 25 36 F 8 26 50 C C 26 54 B D 26 46 D B 26 58 A E 26 42 E A 26 62 9 F

Rev. B | Page 28 of 48 Divide Ratio Duty Cycle (%) 4Ah to 52h LO<7:4> HI<3:0> 26 38 F 9 27 52 C D 27 48 D C 27 56 B E 27 44 E B 27 59 A F 27 41 F A 28 50 D D 28 54 C E 28 46 E C 28 57 B F 28 43 F B Divide Ratio Duty Cycle (%) 4Ah to 52h LO<7:4> HI<3:0> 29 52 D E 29 48 E D 29 55 C F 29 45 F C 30 50 E E 30 53 D F 30 47 F D 31 52 E F 31 48 F E 32 50 F F

Figure 26. Analog Delay (OUT4)

10 MHz clock, the delay can extend to the full 10 ns maximum

5 ns (or half of the period). settings for each full scale, set by Register 36h. longer ramp means more noise might be introduced. Figure 27. LVPECL Output Simplified Equivalent Circuit

Figure 28. LVDS Output Simplified Equivalent Circuit new programming while the PDB mode is active. certain termination and load configurations when tri-stated.  All clocks and sync circuits are off.  All LVDS/CMOS outputs are off.  All LVPECL outputs are in safe off mode. required when exiting power-down mode. under certain termination conditions. powered down, regardless of their output load configuration. (see Register 3Dh, Register 3Eh, and Register 3Fh in Table 18). 58h<3> = 1b (see the Distribution Power-Down section). functionality is not needed. indicated in the default value column of Table 17. registers, except for Register 00h itself. 00h<5> = 0b for the operation of the part to continue.

synchronized is shown in Figure 29. a high indicates an out-of-sync condition. Figure 29. Multichip Synchronization

read/write access to all registers that configure the AD9512. only) or for two unidirectional I/O pins (SDIO/SDO). SCLK (serial clock) is the serial shift clock. This pin is an input. pin is internally pulled down by a 30 kΩ resistor to ground. reading back data. The AD9512 defaults to this I/O mode. 30 kΩ resistor to ground. It should not be left NC or tied low. the use of the CSB in a communication cycle. Figure 30. Serial Control Port boundary terminates the serial transfer and flushes the buffer. address for the first byte of the data transfer.

register changes since any previous update. bidirectional mode, the readback data appears on the SDIO pin. Figure 31. Relationship Between Serial Control Port Register Buffers and Table 14. Byte Transfer Count bytes increment the address. control port operations are changed to LSB first order. toward 1FFFh for multibyte I/O operations. operations that would include these addresses.

Figure 37. Serial Control Port Timing—Write Table 16. Serial Control Port Timing

16 INSTRUCTION BITS + 8 DATA BITS 16 INSTRUCTION BITS + 8 DATA B ITS

BE TOGGLED HIGH AND THEN LOW AT THE COMPLETION OF A COMMUNICATION CYCLE. Figure 38. Use of CSB to Define Communication Cycles

Table 17. AD9512 Register Map

00 Serial

34 Delay Bypass 4 Not Used Bypass 01 Bypass

35 Delay

36 Delay Fine

40 LVDS_CMOS

02 LVDS, ON

41 LVDS_CMOS

45 Clocks Select,

01 All Clocks

Rev. B | Page 38 of 48 Addr (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Def. Value (Hex) Notes 4F Divider 2 Bypass No Sync Force Start H/L Phase Offset <3:0> 00 Phase = 0

50 Divider 3 Low Cycles <7:4> High Cycles <3:0> 00 Divide by 2

51 Divider 3 Bypass No

Force Start H/L Phase Offset <3:0> 00 Phase = 0

52 Divider 4 Low Cycles <7:4> High Cycles <3:0> 11 Divide by 4

53 Divider 4 Bypass No

Force Start H/L Phase Offset <3:0> 00 Phase = 0 54, 55, 56, 57 Not Used FUNCTION

58 FUNCTION

00 FUNCTION

Pin = RESETB

59 Not Used

00 Self-

functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 17. Table 18. AD9512 Register Descriptions does not have to be written. is 8 bits. The default, and only, mode for this part is long instruction (Default = 1b). the SDO is active (unidirectional mode). (Default = 0b). Bypasses Delay Block and Powers It Down (Default = 1b). The slowest ramp (200 μs) sets the longest full scale of approximately 10 ns. Selects the Number of Capacitors in Ramp Generation Circuit. More Capacitors => Slower Ramp.

Rev. B | Page 40 of 48 Reg. Addr. (Hex) Bit(s) Name Description 36 <5:1> Delay Fine Adjust OUT4 Sets Delay Within Full Scale of the Ramp; There Are 32 Steps. 00000b => Zero Delay (Default). 11111b => Maximum Delay. 36 <7:6> Not Used. 37 (38) (39) (3A) (3B) (3C) <7:0> Not Used. OUTPUTS 3D (3E) (3F) <1:0> Power-Down LVPECL OUT0 (OUT1) (OUT2) Mode <1> <0> Description Output ON 0 0 Normal Operation. ON PD1 0 1 Test Only—Do Not Use. OFF PD2 1 0 Safe Power-Down. Partial Power-Down; Use If Output Has Load Resistors. OFF PD3 1 1 Total Power-Down. Use Only If Output Has No Load Resistors. OFF 3D (3E) (3F) <3:2> Output Level LVPECL OUT0 (OUT1) (OUT2) Output Single-Ended Voltage Levels for LVPECL Outputs. <3> <2> Output Voltage (mV) 0 0 490 0 1 330 1 0 805 (Default) 1 1 650 3D (3E) (3F) <7:4> Not Used. 40 (41) <0> Power-Down LVDS/CMOS OUT3 (OUT4) Power-Down Bit for Both Output and LVDS Driver. 0 = LVDS/CMOS on (Default). 1 = LVDS/CMOS Power-Down. 40 (41) <2:1> Output Current Level LVDS OUT3 (OUT4) <2> <1> Current (mA) Termination (Ω) 0 0 1.75 100 0 1 3.5 (Default) 100 1 0 5.25 50 1 1 7 50 40 (41) <3> LVDS/CMOS Select OUT3 (OUT4) 0 = LVDS (Default). 1 = CMOS. 40 (41) <4> Inverted CMOS Driver OUT3 (OUT4) Affects Output Only when in CMOS Mode. 0 = Disable Inverted CMOS Driver (Default). 1 = Enable Inverted CMOS Driver. 40 (41) <7:5> Not Used.

Rev. B | Page 41 of 48 Reg. Addr. (Hex) Bit(s) Name Description CLK1 AND CLK2 45 <0> Clock Select 0: CLK2 Drives Distribution Section. 1: CLK1 Drives Distribution Section (Default). 45 <1> CLK1 Power-Down 1 = CLK1 Input Is Powered Down (Default = 0b). 45 <2> CLK2 Power-Down 1 = CLK2 Input Is Powered Down (Default = 0b). 45 <4:3> Not Used. 45 <5> All Clock Inputs Power- Down 1 = Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree; (Default = 0b). 45 <7:6> Not Used. 46 (47) (48) (49) <7:0> Not Used. DIVIDERS <3:0> Divider High Number of Cloc k Cycles Divider Output Stays High. 4A OUT0 (4C) (OUT1) (4E) (OUT2) (50) (OUT3) (52) (OUT4) <7:4> Divider Low Number of Clock Cycles Divider Output Stays Low. 4A OUT0 (4C) (OUT1) (4E) (OUT2) (50) (OUT3) (52) (OUT4) <3:0> Phase Offset Phase Offset (Default = 0000b). 4B OUT0 (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) <4> Start Selects Start High or Start Low. 4B OUT0 (Default = 0b). (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) <5> Force Forces Individual Outputs to the State Specified in Start (Above). This Function Requires That Nosync (Below) Also Be Set (Default = 0b). 4B OUT0 (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) <6> Nosync Ignore Chip-Level Sync Signal (Default = 0b). 4B OUT0 (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4)

Rev. B | Page 42 of 48 Reg. Addr. (Hex) Bit(s) Name Description <7> Bypass Divider Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b). 4B OUT0 (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) 54 (55) (56) (57) <7:0> Not Used. FUNCTION 58 <0> SYNC Detect Enable 1 = Enable SYNC Detect (Default = 0b). 58 <1> SYNC Select 1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles. 0 (Default) = Raise Flag if Slow Clocks Are Out-of-Sync by 1 to 1.5 High Speed Clock Cycles. 58 <2> Soft SYNC Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit’s polarity is reversed. That is, a high level forces selected outputs into a known state, and a high > low transition triggers a sync (Default = 0b). 58 <3> Dist Ref Power-Down 1 = Power-Down the Referenc es for the Distribution Section (Default = 0b). 58 <4> SYNC Power-Down 1 = Power-Down the SYNC (Default = 0b). 58 <6:5> FUNCTION Pin Select <6> <5> Function 0 0 RESETB (Default) 0 1 SYNCB 1 0 Test Only; Do Not Use 1 1 PDB 58 <7> Not Used. 59 <7:0> Not Used. 5A <0> Update Registers 1 written to this bit updates all registers and transfers all serial control port register buffer contents to the control registers on the next rising SCLK edge. This is a self-clearing bit. 0 does not have to be written to clear it. 5A <7:1> Not Used. END

Rev. B | Page 43 of 48 POWER SUPPLY The AD9512 requires a 3.3 V ± 5% power supply for VS. The tables in the Specifications section give the performance expected from the AD9512 with the power supply voltage within this range. The absolute maximum range of −0.3 V to +3.6 V, with respect to GND, must never be exceeded on the VS pin. Good engineering practice should be followed in the layout of power supply traces and ground plane of the PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 μF). The AD9512 should be bypassed with adequate capacitors (0.1 μF) at all power pins, as close as possible to the part. The layout of the AD9512 evaluation board (AD9512/PCB) is a good example. The AD9512 is a complex part that is programmed for its desired operating configuration by on-chip registers. These registers are not maintained over a shutdown of external power. This means that the registers can lose their programmed values if V S is lost long enough for the internal voltages to collapse. Careful bypassing should protect the part from memory loss under normal conditions. Nonetheless, it is important that the V S power supply not become intermittent, or the AD9512 risks losing its programming. The internal bias currents of the AD9512 are set by the RSET resistors. This resistor should be as close as possible to the value given as conditions in the Specifications section (RSET = 4.12 kΩ). This is a standard 1% resistor value and should be readily obtainable. The bias currents set by this resistor determine the logic levels and operating conditions of the internal blocks of the AD9512. The performance figures given in the Specifications section assume that this specific resistor value is used. The exposed metal paddle on the AD9512 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The PCB acts as a heat sink for the AD9512; therefore, this GND connection should provide a good thermal path to a larger dissipation area, such as a ground plane on the PCB. See the layout of the AD9512 evaluation board (AD9512/PCB or AD9512-VCO/PCB) for a good example. POWER MANAGEMENT The power usage of the AD9512 can be managed to use only the power required for the functions that are being used. Unused features and circuitry can be powered down to save power. The following circuit blocks can be powered down, or are powered down when not selected (see the Register Map and Description section):  Any of the dividers are powered down when bypassed— equivalent to divide-by-one.  The adjustable delay block on OUT4 is powered down when not selected.  Any output can be powered down. However, LVPECL outputs have both a safe and an off condition. When the LVPECL output is terminated, only the safe shutdown should be used to protect the LVPECL output devices. This still consumes some power.  The entire distribution section can be powered down when not needed. Powering down a functional block does not cause the programming information for that block (in the registers) to be lost. This means that blocks can be powered on and off without otherwise having to reprogram the AD9512. However, synchronization is lost. A SYNC must be issued to resynchronize (see the Single-Chip Synchronization section).

Rev. B | Page 44 of 48 USING THE AD9512 OUTPUTS FOR ADC CLOCK Any high speed analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer; any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at ≥14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed approximately by   jftSNR 2π 1log 20 where f is the highest analog frequency being digitized, and tj is the rms jitter on the sampling clock. Figure 39 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB). 120 100 1 3 10 30 100 05287-024 FULL-SCALE SINE WAVE ANALOG INPUT FREQUENCY (MHz) SNR (dB) ENOB tj = 50fs tj = 0.1ps tj = 1ps tj = 10ps tj = 100ps tj = 1ns SNR = 20log10 2ftj Figure 39. ENOB and SNR vs. Analog Input Frequency best clocking/converter solution. requiring CMOS level logic at their clock inputs. following general guidelines should be followed.

1.0 INCH

Figure 40. Series Termination of CMOS Output Termination at the far end of the PCB trace is a second option. trace lengths on less critical nets. Figure 41. CMOS Output with Far-End Termination

0.20 MIN

0.05 MAX

0.02 NOM

0.203 REF

5.50 REF

Figure 45. 48-Lead Lead Frame Chip Scale Package [LFCSP]

Rev. B | Page 47 of 48 NOTES

Rev. B | Page 48 of 48 NOTES © 2005–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D05287–9/20(B)