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1.65 GHz Clock Fanout Buffer with
Output Dividers and Delay Adjust Data Sheet AD9508 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
1.65 GHz differential clock inputs/outputs
10-bit programmable dividers, 1 to 1024, all integers Up to 4 differential outputs or 8 CMOS outputs Pin strapping capability for hardwired programming at power-up <115 fs rms broadband random jitter (see Figure 25) Additive output jitter: 41 fs rms typical (12 kHz to 20 MHz) Excellent output-to-output isolation Automatic synchronization of all outputs Single 2.5 V/3.3 V power supply Internal LDO (low drop-out) voltage regulator for enhanced power supply immunity Phase offset select for output-to-output coarse delay adjust 3 programmable output logic levels, LVDS, HSTL, and CMOS Serial control port (SPI/I 2C) or pin-programmable mode Space-saving 24-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential clock outputs, each with various types of logic levels available. Available logic types include LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8 V CMOS (250 MHz). In 1.8 V CMOS output mode, the differential output becomes two CMOS single-ended signals. The CMOS outputs are 1.8 V logic levels, regardless of the operating supply voltage. Each output has a programmable divider that can be bypassed or be set to divide by any integer up to 1024. In addition, the AD9508 supports a coarse output phase adjustment between the outputs. The device can also be pin programmed for various fixed configurations at power-up without the need for SPI or I2C programming. The AD9508 is available in a 24-lead LFCSP and operates from a either a single 2.5 V or 3.3 V supply. The temperature range is −40°C to +85°C. DIV/Φ OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3CONTROL INTERFACE SPI/I2C/PINS AD9508 CLK SCLK/SCL/SC0 SDIO/SDA/S1 SDO/S3 CS/C2 SYNC CLK PIN CONTROL DIV/Φ DIV/Φ DIV/Φ RESET 11161-001
Rev. A | Page 2 of 40 TABLE OF CONTENTS
REVISION HISTORY
4/13—Rev. 0 to Rev. A 1/13—Revision 0: Initial Version
Rev. A | Page 3 of 40 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical values are given for VS = 3.3 V and 2.5 V and TA = 25°C; minimum and maximum values are given over the full VDD = 3.3 V + 5% down to 2.5 V − 5% and TA = −40°C to +85°C variation; and input slew rate > 1 V/ns, unless otherwise noted. POWER SUPPLY CURRENT AND TEMPERATURE CONDITIONS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments appropriate current consumption configura- tion (see Current Consumption parameters in Table 1) to calculate total power dissipation CURRENT CONSUMPTION LVDS Configuration 152 168 mA Input clock: 1500 MHz in differential mode, all LVDS output drivers at 1500 MHz 122 134 mA Input clock: 800 MHz in differential mode, all LVDS output drivers at 200 MHz HSTL Configuration 182 200 mA Input clock: 1500 MHz in differential mode, all HSTL output drivers at 1500 MHz 118 131 mA Input clock: 491.52 MHz in differential mode, all output drivers at 491.52 MHz 92 101 mA Input clock: 122.88 MHz in differential mode, all output drivers at 122.88 MHz CMOS Configuration 141 185 mA Input clock: 1500 MHz in differential mode, all CMOS output drivers at 250 MHz, 10 pF load 122 134 mA Input clock: 800 MHz in differential mode, all CMOS outputs drivers at 200 MHz, 10 pF load 85 94 mA Input clock: 100 MHz in differential mode, all CMOS outputs drivers at 100 MHz, 10 pF load Full Power-Down 6 10 mA TEMPERATURE Ambient Temperature Range, TA −40 +25 +85 °C Junction Temperature, TJ 115 °C Junction temperatures above 115°C can degrade performance but no damage should occur, unless the absolute temperature is exceeded
Rev. A | Page 4 of 40 CLOCK INPUTS AND OUTPUT DC SPECIFICATIONS Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments CLOCK INPUTS Differential Mode Input Frequency 0 1650 MHz Differential input Input Sensitivity 360 2200 mV p-p As measured with a differential probe; jitter performance improves with higher slew rates (greater voltage swing) Input Common-Mode Voltage VICM 0.95 1.05 1.15 V Input pins are internally self biased, which enables ac coupling Input Voltage Offset 30 mV DC-Coupled Input Common- Mode Range VCMR 0.58 1.67 V This is the allowable common-mode voltage range when dc-coupled Pulse Width Low 303 ps High 303 ps Input Resistance (Differential) 5.0 7 9 kΩ Input Capacitance CIN 2 pF Input Bias Current (Each Pin) 100 400 µA Full input swing CMOS CLOCK MODE (SINGLE-ENDED) Input Frequency 250 MHz Input Voltage High VIH VDD/2 − 0.15 V Low VIL VDD/2 + 0.15 V Input Current High IINH 1 µA Low IINL −142 µA Input Capacitance CIN 2 pF LVDS CLOCK OUTPUTS Termination = 100 Ω differential (OUTx, OUTx) Output Frequency 1650 MHz Output Voltage Differential VOD 247 375 454 mV VOH − VOL measurement across a differential pair at the default amplitude setting with output driver not toggling; see Figure 6 for variation over frequency Delta VOD ΔVOD 50 mV This is the absolute value of the difference between VOD when the normal output is high vs. when the complementary output is high Offset Voltage VOS 1.125 1.18 1.375 V (VOH + VOL)/2 across a differential pair Delta VOS ΔVOS 50 mV This is the absolute value of the difference between VOS when the normal output is high vs. when the complementary output is high Short-Circuit Current ISA, ISB 13.6 24 mA Each pin (output shorted to GND) LVDS Duty Cycle 45 55 % Up to 750 MHz input 39 61 % 750 MHz to1500 MHz input 50.1 % 1650 MHz input HSTL CLOCK OUTPUTS 100 Ω across differential pair; default amplitude setting Output Frequency 1650 MHz Differential Output Voltage VO 859 925 978 mV VOH − VOL with output driver static Common-Mode Output Voltage VOCM 905 940 971 mV (VOH + VOL)/2 with output driver static HSTL Duty Cycle 45 55 % Up to 750 MHz input 40 60 % 750 MHz to 1500 MHz input 50.9 % 1650 MHz input
Rev. A | Page 5 of 40 Parameter Symbol Min Typ Max Unit Test Conditions/Comments CMOS CLOCK OUTPUTS Single-ended; termination = open; OUTx and OUTx in phase Output Frequency 250 MHz With 10 pF load per output, see Figure 14 for swing vs. frequency Output Voltage @ 1 mA Load High VOH 1.7 V Low VOL 0.1 V @ 10 mA load High VOH 1.2 V Low VOL 0.6 V @ 10 mA Load (2 × CMOS Mode) High VOH 1.45 V Low VOL 0.35 V CMOS Duty Cycle 45 55 % Up to 250 MHz OUTPUT DRIVER TIMING CHARACTERISTICS Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments LVDS OUTPUTS Termination = 100 Ω differential, 1 × LVDS Output Rise/Fall Time tR, tF 152 177 ps 20% to 80% measured differentially Propagation Delay, Clock-to-LVDS Output tPD 1.56 2.01 2.43 ns Temperature Coefficient 2.8 ps/°C Output Skew1 All LVDS Outputs On the Same Part 48 ps Across Multiple Parts 781 ps Assumes same temperature and supply; takes into account worst-case propaga- tion delay delta due to worst-case process variation HSTL OUTPUTS Termination = 100 Ω differential, 1 × HSTL Output Rise/Fall Time tR, tF 118 143 ps 20% to 80% measured differentially Propagation Delay, Clock-to-HSTL Output tPD 1.59 2.05 2.5 ns Temperature Coefficient 2.9 ps/°C Output Skew1 All HSTL Outputs On the Same Part 59 ps Across Multiple Parts 825 ps Assumes same temperature and supply; takes into account worst-case propaga- tion delay delta due to worst-case process variation CMOS OUTPUTS Output Rise/Fall Time tR, tF 1.18 1.45 ns 20% to 80%; CLOAD = 10 pF Propagation Delay, Clock-to-CMOS Output tPD 2.04 2.56 3.07 ns 10 pF load Temperature Coefficient 3.3 ps/°C Output Skew1 All CMOS Outputs On the Same Part 112 ps Across Multiple Parts 965 ps Assumes same temperature and supply; takes into account worst-case propagation delay delta due to worst- case process variation
Rev. A | Page 6 of 40 Parameter Symbol Min Typ Max Unit Test Conditions/Comments OUTPUT LOGIC SKEW1 CMOS load = 10 pF and LVDS load = 100 Ω LVDS Output(s) and HSTL Output(s) 77 119 ps Outputs on the same device; assumes worst-case output combination LVDS Output(s) and CMOS Output(s) 497 700 ps Outputs on the same device; assumes worst-case output combination HSTL Output(s) and CMOS Output(s) 424 622 ps Outputs on the same device; assumes worst-case output combination 1 Output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. LOGIC INPUTS Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS RESET, SYNC, IN_SEL Input Voltage High VIH 1.7 V 2.5 V supply voltage operation 2.0 V 3.3 V supply voltage operation Low VIL 0.7 V 2.5 V supply voltage operation 0.8 V 3.3 V supply voltage operation Input Current IINH, IINL −300 +100 µA Input Capacitance CIN 2 pF SERIAL PORT SPECIFICATIONS—SPI MODE Table 5. Parameter Min Typ Max Unit Test Conditions/Comments CS SCLK has a 200 kΩ internal pull-down resistor Input Voltage Logic 1 VDD − 0.4 V Logic 0 0.4 V Input Current Logic 1 −4 µA Logic 0 −85 µA Input Capacitance 2 µA SCLK Input Voltage Logic 1 VDD − 0.4 V Logic 0 0.4 V Input Current Logic 1 70 µA Logic 0 13 µA Input Capacitance 2 pF SDIO As Input Input Voltage Logic 1 VDD − 0.4 V Logic 0 0.4 V Input Current Logic 1 −1 µA Logic 0 −1 µA Input Capacitance 2 pF
Rev. A | Page 7 of 40 Parameter Min Typ Max Unit Test Conditions/Comments As Output Output Voltage Logic 1 VDD − 0.4 V 1 mA load current Logic 0 0.4 V 1 mA load current SDO Output Voltage Logic 1 VDD − 0.4 V 1 mA load current Logic 0 0.4 V 1 mA load current TIMING SCLK Clock Rate, 1/tCLK 30 MHz Pulse Width High, tHIGH 4.6 ns Pulse Width Low, tLOW 3.5 ns SDIO to SCLK Setup, tDS 2.9 ns SCLK to SDIO Hold, tDH 0 ns SCLK to Valid SDIO and SDO, tDV 15 ns EE AA to SCLK Setup (tS) CS 3.4 ns AACS EE AA to SCLK Hold (tC) 0 ns AACS EE AA Minimum Pulse Width High 3.4 ns SERIAL PORT SPECIFICATIONS—I2C MODE Table 6. Parameter Min Typ Max Unit Test Conditions/Comments SDA, SCL (AS INPUT) Input Voltage Logic 1 VDD − 0.4 V Logic 0 0.4 V Input Current −40 0 µA For VIN = 10% to 90% DVDD3 Hysteresis of Schmitt Trigger Inputs 150 mV SDA (AS OUTPUT) Output Logic 0 Voltage 0.4 V IO = 3 mA Output Fall Time from VIH (MIN) to VIL (MAX) 250 ns 10 pF ≤ Cb ≤ 400 pF TIMING SCL Clock Rate 400 kHz Bus-Free Time Between a Stop and Start Condition, tBUF 1.3 µs Repeated Start Condition Setup Time, tSU; STA 0.6 µs Repeated Hold Time Start Condition, tHD; STA 0.6 µs After this period, the first clock pulse is generated Stop Condition Setup Time, tSU; STO 0.6 µs Low Period of the SCL Clock, tLOW 1.3 µs High Period of the SCL Clock, tHIGH 0.6 µs Data Setup Time, tSU; DAT 100 ns Data Hold Time, tHD; DAT 0 0.9 µs
Rev. A | Page 8 of 40 EXTERNAL RESISTOR VALUES FOR PIN STRAPPING MODE Table 7. Parameter Resistor Polarity Min Typ Max Unit Test Conditions/Comments EXTERNAL RESISTORS Using 10% tolerance resistor Voltage Level 0 Pull down to ground 820 Ω Voltage Level 1 Pull down to ground 1.8 kΩ Voltage Level 2 Pull down to ground 3.9 kΩ Voltage Level 3 Pull down to ground 8.2 kΩ Voltage Level 4 Pull up to VDD 820 Ω Voltage Level 5 Pull up to VDD 1.8 kΩ Voltage Level 6 Pull up to VDD 3.9 kΩ Voltage Level 7 Pull up to VDD 8.2 kΩ CLOCK OUTPUT ADDITIVE PHASE NOISE Table 8. Parameter Min Typ Max Unit Test Conditions/Comments CLK-TO-HSTL OR LVDS ADDITIVE PHASE NOISE CLK = 1474.56 MHz, OUTx = 1474.56 MHz Input slew rate > 1 V/ns Divide Ratio = 1 @ 10 Hz Offset −88 dBc/Hz @ 100 Hz Offset −100 dBc/Hz @ 1 kHz Offset −109 dBc/Hz @ 10 kHz Offset −116 dBc/Hz @ 100 kHz Offset −135 dBc/Hz @ 1 MHz Offset −144 dBc/Hz @ 10 MHz Offset −148 dBc/Hz @ 100 MHz Offset −149 dBc/Hz CLK-TO-HSTL OR LVDS or CMOS ADDITIVE PHASE NOISE CLK = 625 MHz, OUTx = 125 MHz Input slew rate > 1 V/ns Divide Ratio = 5 @ 10 Hz Offset −114 dBc/Hz @ 100 Hz Offset −125 dBc/Hz @ 1 kHz Offset −133 dBc/Hz @ 10 kHz Offset −141 dBc/Hz @ 100 kHz Offset −159 dBc/Hz @ 1 MHz Offset −162 dBc/Hz @ 10 MHz Offset −163 dBc/Hz @ 20 MHz Offset −163 dBc/Hz CLK-TO-HSTL OR LVDS ADDITIVE PHASE NOISE CLK = 491.52 MHz, OUTx = 491.52 MHz Input slew rate > 1 V/ns Divide Ratio = 1 @ 10 Hz Offset −100 dBc/Hz @ 100 Hz Offset −111 dBc/Hz @ 1 kHz Offset −120 dBc/Hz @ 10 kHz Offset −127 dBc/Hz @ 100 kHz Offset −146 dBc/Hz @ 1 MHz Offset −153 dBc/Hz @ 10 MHz Offset −153 dBc/Hz @ 20 MHz Offset −153 dBc/Hz
Rev. A | Page 9 of 40 CLOCK OUTPUT ADDITIVE TIME JITTER Table 9. Parameter Min Typ Max Unit Test Conditions/Comments LVDS OUTPUT ADDITIVE TIME JITTER CLK = 622.08 MHz, Outputs = 622.08 MHz 41 fs rms BW = 12 kHz to 20 MHz 70 fs rms BW = 20 kHz to 80 MHz 69 fs rms BW = 50 kHz to 80 MHz CLK = 622.08 MHz, Outputs = 155.52 MHz 93 fs rms BW = 12 kHz to 20 MHz 144 fs rms BW = 20 kHz to 80 MHz 142 fs rms BW = 50 kHz to 80 MHz CLK = 125 MHz, Outputs = 125 MHz 105 fs rms BW = 12 kHz to 20 MHz 209 fs rms BW = 20 kHz to 80 MHz 206 fs rms BW = 50 kHz to 80 MHz CLK = 400 MHz, Outputs = 50 MHz 184 fs rms BW = 12 kHz to 20 MHz HSTL OUTPUT ADDITIVE TIME JITTER CLK = 622.08 MHz, Outputs = 622.08 MHz 41 fs rms BW = 12 kHz to 20 MHz 56 fs rms BW = 100 Hz to 20 MHz 72 fs rms BW = 20 kHz to 80 MHz 70 fs rms BW = 50 kHz to 80 MHz CLK = 622.08 MHz, Outputs = 155.52 MHz 76 fs rms BW = 12 kHz to 20 MHz 87 fs rms BW = 100 Hz to 20 MHz 158 fs rms BW = 20 kHz to 80 MHz 156 fs rms BW = 50 kHz to 80 MHz CMOS OUTPUT ADDITIVE TIME JITTER CLK = 100 MHz, Outputs = 100 MHz 91 fs rms BW = 12 kHz to 20 MHz
TJ is the junction temperature (°C). the top center of the package. JT is the value as indicated in Table 11. PD is the power dissipation. where TA is the ambient temperature (°C). design considerations when an external heat sink is required. Table 11. Thermal Characteristics, 24-Lead LFCSP
1 The exposed pad on the bottom of the package must be soldered to ground
(VSS) to achieve the specified thermal performance. assumed in these calculations.
Figure 2. Pin Configuration Table 12. Pin Function Descriptions to Program on Power-Up section for more details. 2 OUT0 LVDS/HSTL Differential Output or Single-Ended CMOS Output. 3 OUT0 Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output. 4 SDO/S3 Serial Data Output/Pin Programming. Multipurpose pin. This pin is controlled by the PROG_SEL pin. programming mode, this pin becomes S3, which is hard wired with a resistor to either VDD or ground. and Pin 17. See the Pin Strapping to Program on Power-Up section for more details. 5 EXT_CAP0 Node for External Decoupling Capacitor for LDO. Tie this pin to a 0.47 μF capacitor to ground. 6 VDD Power Supply (2.5 V or 3.3 V Operation). 7 OUT1 LVDS/HSTL Differential Output or Single-Ended CMOS Output. 8 OUT1 Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output. on Pin 2, Pin 3, Pin 7, and Pin 8. See the Pin Strapping to Program on Power-Up section for more details. 11 OUT2 LVDS/HSTL Differential Output or Single-Ended CMOS Output. 12 OUT2 Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output. 13 VDD Power Supply (2.5 V or 3.3 V Operation). 14 EXT_CAP1 Node for External Decoupling Capacitor fo r LDO. Tie this pin to a 0.47 μF capacitor to ground. 16 OUT3 LVDS/HSTL Differential Output or Single-Ended CMOS Output. 17 OUT3 Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output.
- THE EXPOSED DIE PAD MUST BE CONNECTED
Rev. A | Page 12 of 40 Pin No. Mnemonic Description
18 ARESET
E CMOS Input. Device Reset. When this active low pin is asserted, the internal register settings enter their default state after the ARESET E A is released. Note that ARESET E A also serves as a power-down of the device while an active low signal is applied to the pin. The ARESET E A pin has an internal 24 kΩ pull-up resistor. 19 SCLK/SCL/S0 Serial Programming Clock/Data Clock/Programming Pin. Multipurpose pin controlled by the PROG_SEL pin used for serial programming clock (SCLK) in SPI mode or data clock (SCL) for serial programming in I2C Mode. The PROG_SEL pin determines which programming mode is used. In pin programming mode, this pin becomes S0. In this mode, S0 is hardwired with a resistor to either VDD or ground. The resistor value and resistor biasing determine the channel divider values for the outputs on Pin 2 and Pin 3. See the Pin Strapping to Program on Power-Up section for more details.
20 ASYNC
E Clock Synchronization. When this pin is active low, the output drivers are held static and then synchronized on a low-to-high transition of this pin. The ASYNC E A pin has an internal 24 kΩ pull-up resistor. 21 CLK Differential Clock Input or Single-Ended CMOS Input. Whether this pin serves as the differential clock input or the single-ended CMOS input depends on the logic state of the IN_SEL pin.
22 ACLK
E Complementary Differential Clock Input. 23 IN_SEL CMOS Input. A logic high configures the CLK and ACLK E A inputs for a differential input signal. A logic low configures the input for single-ended CMOS applied to the CLK pin. AC-couple the unused ACLK E A to ground with a 0.1 μF capacitor. 24 SDIO/SDA/S1 Serial Data Input and Output (SPI)/Serial Data (I2C)/Pin Programming. Pin 24 is a multipurpose input controlled by the PROG_SEL pin used for SPI (SDIO), I2C (SDA), and pin strapping modes (S1). When the device is in 4-wire SPI mode, data is written via SDIO. In 3-wire mode, both data reads and writes occur on this pin. There is no internal pull-up/pull-down resistor on this pin. In I2C mode, SDA serves as the serial data pin. The PROG_SEL pin determines which programming mode is used. In pin programming mode, this pin becomes S1. In this mode, S1 is hardwired with a resistor to either VDD or ground. The resistor value and resistor biasing determine the channel divider values for the outputs on Pin 7 and Pin 8. See the Pin Strapping to Program on Power-Up section for more details. EP Exposed Pad. The exposed die pad must be connected to ground (VSS).
Figure 33. Additive Phase Noise with Clock Input = 100 MHz with CMOS
Rev. A | Page 20 of 40 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and an even progression phase with time from 0 degrees to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, characterized statistically as being Gaussian (normal) in distribution. Phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spec- trum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise contained within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as with time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or one sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the SNR and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable only to the device or subsystem being measured. The residual phase noise system makes use of two devices operating in perfect quadrature. The correlated noise of any external components common to both devices (such as clock sources) is not present. This makes it possible to predict the degree to which the device is going to affect the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contribute their own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. Additive Time Jitter Additive time jitter refers to the amount of time jitter that is attributable to the device or subsystem being measured. It is calculated by integrating the additive phase noise over a specific range. This makes it possible to predict the degree to which the device is going to impact the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute their own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
Figure 41. Detailed Block Diagram at speeds of up to 1650 MHz. no phase offset adjustment available. outputs is adjustable for output drive strength. Table 13. SPI/I2C/Pin Serial Port Setup The IN_SEL pin controls the desired input clock configuration. ground with a 0.1 μF capacitor.
operation with its logic level set to 11 or toggle mode. with adequate capacitance (0.1 µF) as close to the part as possible. its exposed paddle. The PCB acts as a heat sink for the AD9508. ground plane. See Figure 47 for an example. Figure 47. PCB Land Example for Attaching Exposed Paddle
output or to set the output to a high-Z state. relationship and share the same channel divider value. listed in Table 15 must have 10% or better tolerance. configuration instead of using the 820 Ω resistor. Table 15. Selection Table for Pin Strapping Control
many industry-standard microcontrollers and microprocessors. In SPI mode, single- or multiple-byte transfers are supported. The SPI port configuration is programmable via Register 0x00. Table 16. Serial Port Mode Selection supports a maximum clock rate of 40 MHz. default SPI mode is bidirectional. I/O mode. It serves as the data output pin for read operations. to switch to unidirectional mode. the instruction and data portions of the transfer. terminates the serial transfer and flushes the buffer. Table 17. Byte Transfer Count The SPI protocol consists of a two part communication cycle.
data is written to blank registers, but it is customary to write 0s. buffer register contents to their active register counterparts. are not skipped during readback. port buffer registers or the active registers. starting register address of the read/write operation (see Table 19). bit is set, subsequent serial control port operations are LSB first. data bytes must follow, in order, from high address to low address. tor decrements for each data byte of the multibyte transfer cycle. consecutive reserved (or unmapped) registers. Table 18. Streaming Mode (No Addresses Skipped) Table 19. Serial Control Port, 16-Bit Instruction Word, MSB First Bit Map Figure 48. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data
Table 20. Serial Control Port Timing pins and is a de facto standard throughout the I2C industry. receivers ignore pulses of less than 50 ns duration. as a slave device; that is, no clock is generated by the AD9508. traditional 8-bit memory addressing. Table 21. I2C Bus Abbreviation Definitions clock signal on the SCL line is low. Figure 54. Valid Bit Transfer by a low-to-high transition on the SDA line while SCL is high. a data transfer. Every byte on the SDA line must be eight bits long. each 8-bit data byte (see Figure 56).
value to sections of registers marked reserved. reset. Note that the default column is represented by Def. Table 23. Register Map
Table 24. Serial Configuration 0x00 7 SDO enable Enables SPI port SDO pin. This bit does nothing in I²C mode. 1 = 4-wire (SDO pin enabled). 6 LSB first/increment address Bit order for the SPI port. This bit is nonfunctional in I²C mode. 2 Soft reset Same function as Bit 5 of this register, set Bit 2 and Bit 5 to the same value. 1 LSB first/increment address Same function as Bit 6 of this register, set Bit 1 and Bit 6 to the same value. 0 SDO enable Same function as Bit 7 of this register, set Bit 7 and Bit 0 to the same value. Table 25. Silicon Revision 0x0A [7:0] Silicon Revision[7:0] A read-only register. Identifies the revision level of the AD9508. 0x0B [7:0] Reserved 0x00 = default. 0x0D [7:0] Clock Part Family ID[15:8] This register is a continuation of Register 0x000C. Table 26. Sleep and Synchronization
4 Sleep 0 = disables sleep mode (default)
0 SYNC_BAR 0 = enables a software output synchronization routine
Table 27. Divide Ratio and Phase Table 28. Output Driver, Power Down, and Sync
6 SYNCMASK0 Setting this bit masks Channel 0 from the output sync function
0 Reserved 0b = default
4 EN_CMOS_0N Setting this bit enables the OUT0N CMOS driver
Table 29. Divide Ratio and Phase Table 30. Output Driver, Power Down, and Sync
6 SYNCMASK1 Setting this bit masks Channel 1 from the output sync function
Table 31. Divide Ratio and Phase Table 32. Output Driver, Power Down, and Sync
6 SYNCMASK2 Setting this bit masks OUT2 from the output sync function
4 EN_CMOS_2N Setting this bit enables the OUT2N CMOS driver
Table 33. Divide Ratio and Phase Table 34. Output Driver, Power Down, and Sync
6 SYNCMASK3 Setting this bit masks OUT3 from the output sync function
4 EN_CMOS_3N Setting this bit enables the OUT3N CMOS driver
Figure 60. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] COMPLIANT TOJEDEC STANDARDS MO-220-WGGD.
0.20 REF
0.25 MIN
0.05 MAX
0.02 NOM
Rev. A | Page 39 of 40 NOTES
Rev. A | Page 40 of 40 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11161-0-4/13(A) www.analog.com/AD9508