AD9500

AD9500 Digitally Programmable Delay Generator (Rev D)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 11

Technical content

REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Digitally Programmable Delay Generator AD9500 FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The AD9500 is a digitally programmable delay generator, which provides programmed delays, selected through an 8-bit digital code, in resolutions as small as 10 ps. The AD9500 is con- structed in a high performance bipolar process, designed to provide high speed operation for both digital and analog circuits. The AD9500 employs differential TRIGGER and RESET inputs which are designed primarily for ECL signal levels but function with analog and TTL input levels. An onboard ECL reference midpoint allows both of the inputs to be driven by either single ended or differential ECL circuits. The AD9500 output is a complementary ECL stage, which also provides a QR parallel output circuit to facilitate reset timing implementations. The digital control data is passed to the AD9500 through a transparent latch controlled by the LATCH ENABLE signal. In the transparent mode, the internal DAC of the AD9500 will attempt to follow changes at the inputs. The LATCH ENABLE is otherwise used to strobe the digital data into the AD9500 latches. The AD9500 is available as an industrial temperature range device, –25°C to +85°C, and as an extended temperature range device, –55°C to +125°C. Both grades are packaged in a 24-lead cerdip (0.3" package width), as well as 28-leaded and leadless surface mount packages. The AD9500 is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9500/883B data sheet for detailed specifications.

FEATURES

2.5 ns to 10 ms Full-Scale Range Fully Differential Inputs Separate Trigger and Reset Inputs Low Power Dissipation—310 mW MIL-STD-883 Compliant Versions Available

APPLICATIONS

Arbitrary Waveform Generators High Stability Timing Source Multiple Phase Clock Generators DIFFERENTIAL ANALOG INPUT STAGE ECL VOLTAGE REFERENCE REFERENCE CURRENT TIMING CONTROL CIRCUIT OFFSET ADJUST LATCH ENABLE GROUND ECL COMMON Q TRIGGER RESET ECL REF D 0 (LSB) C S+VS TRIGGER RESET Q R Q INTERNAL DAC TTL LATCHES D 7 (MSB) D 1 AD9500 C EXT R SET R S –VS –VS D 2 D 3 D 4 D 5 D 6 PIN CONFIGURATIONS TOP VIEW (Not to Scale) D 4 D 7 (MSB) ECL REF OFFSET ADJUST C S +V S D 3 D 2 D 1 D 0 (LSB) LATCH ENABLE GROUND R S –VS ECL COMMON Q TRIGGER RESET TRIGGER RESET Q R Q AD9500 D 5 D 6 TOP VIEW (Not to Scale) 4 3 2 1 2 82 72 6 12 13 14 15 16 17 18 LATCH ENABLE GROUND ECL COMMON OFFSET ADJUST TRIGGER D 7 (MSB) ECL REF C S +V S Q Q R RESET TRIGGER RESET Q NC D 6 NC NCNC AD9500 D 5 D 4 D 3 D 2 D 1 D 0 (LSB) R S –VS NC = NO CONNECT Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999

ELECTRICAL CHARACTERISTICS2 (Supply Voltages +VS = +5.0 V, VS = –5.2 V; CEXT = 0 pF; RSET = 500 V unless otherwise noted) –258C to +858C –55 8C to +1258C Test AD9500BP/BQ AD9500TE/TQ Parameter Level Temp Min Typ Max Min Typ Max Units RESOLUTION 8 8 Bits ACCURACY3 Differential Linearity I +25 °C 0.5 0.5 LSB Integral Linearity I +25 °C 1.0 1.0 LSB Monotonicity I +25 °C Guaranteed Guaranteed DIGITAL INPUT Logic “1” Voltage VI Full 2.0 2.0 V Logic “0” Voltage VI Full 0.8 0.8 V Logic “1” Current VI Full 5 5 mA Logic “0” Current VI Full 5 5 mA Digital Input Capacitance VI +25 °C 5.5 5.5 pF Data Setup Time 4 V +25 °C 0.4 0.75 0.4 0.75 ns Data Hold Time5 V +25 °C 0.4 0.75 0.4 0.75 ns Latch Pulsewidth (t LPW) V +25 °C 3.0 3.0 ns RESET/TRIGGER INPUTS6 TRIGGER Input Voltage Range IV Full –2.5; 4.5 –2.5; 4.5 V RESET Input Voltage Range IV Full –2.5; 2.0 –2.5; 2.0 V Differential Switching Voltage IV Full 40 300 40 300 mV Input Bias Current I +25 °C 4 05 0 4 05 0 mA VI Full 75 75 mA Input Resistance IV +25 °C4 4 k W Input Capacitance IV +25 °C 6.5 7.25 6.5 7.25 pF Minimum Input Pulsewidth tTPW, tRPW V +25 °C 2.0 2.0 ns DYNAMIC PERFORMANCE7 Maximum Trigger Rate IV +25 °C 60 60 MHz Minimum Propagation Delay TC V Full 7.5 7.5 ps/ °C Full-Scale Range TC9 V Full 0.5 0.5 ps/ °C Delay Uncertainty (Jitter) V +25 °C1 0 1 0 p s Reset-to-Trigger Holdoff (t THO)11 IV +25 °C 0.2 0 0.2 0 ns Trigger-to-Reset Holdoff (t RHO)12 IV +25 °C 2.0 1.5 2.0 1.5 ns Minimum Output Pulsewidth V +25 °C 3.3 3.3 ns Output Rise Time7 I +25 °C 2.0 2.0 ns Output Fall Time7 I +25 °C 2.0 2.0 ns Delay Coefficient Settling Time (t DAC)13 V +25 °C2 9 2 9 n s Linear Ramp Settling Time (t LRS) V +25 °C2 2 2 2 n s REV. D–2– ABSOLUTE MAXIMUM RATINGS 1 Minimum R Operating Temperature Range AD9500–SPECIFICATIONS

–258C to +858C –55 8C to +1258C Test AD9500BP/BQ AD9500TE/TQ Parameter Level Temp Min Typ Max Min Typ Max Units SUPPORT FUNCTIONS ECLREF Voltage Drift14 V Full 1.1 1.1 mV/ °C Offset Adjust Range V Full –2 –2 mA DIGITAL OUTPUTS7 Logic “1” Voltage VI Full –1.1 –1.1 V Logic “0” Voltage VI Full –1.5 –1.5 V POWER SUPPLY15 Positive Supply Current (+5.0 V) I +25 °C 2 42 8 2 42 8 m A VI Full 30 30 mA Negative Supply Current (–5.2 V) I +25 °C 3 74 2 3 74 2 m A VI Full 44 44 mA Nominal Power Dissipation V +25 °C 312 312 mW Power Supply Rejection Ratio 16 Full-Scale Range Sensitivity I +25 °C 70 300 70 300 ps/V Minimum Propagation Delay Sensitivity I +25 °C 150 500 150 500 ps/V NOTES 1Absolute maximum ratings are limiting values, to be applied individually, and beyond which serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may aff ect device reliability. 2Typical thermal impedance 24-Lead Cerdip qJA = 56°C/W; qJC = 16°C/W 28-Leadless PLCC (Plastic) qJA = 60°C/W; qJC = 22°C/W 28-Leaded Ceramic LCC qJA = 69°C/W; qJC = 25°C/W 3RSET = 10 kW (Full-scale delay = 100 ns). 4The digital data inputs must remain stable for the specified time prior to the LATCH ENABLE signal. 5The digital data inputs must remain stable for the specified time after the LATCH ENABLE signal. 6The TRIGGER and RESET inputs are differential and must be driven relative to one another. Both of these inputs are ECL compatib le, but can also be used with TTL logic families in a limited fashion. 7Outputs terminated through 50 W resistors to –2.0 V. 8Program Delay = 0.0 ps (Digital Data = 00 H). In Operation, any programmed delays are in addition to the Minimum Propagation Delay. 9Change in total delay through AD9500, exclusive of changes in minimum propagation delay t PD. 10Measured from the 50% transition point of the reset signal input, to the 50% transition point of the resetting output. 11Minimum time from falling edge of RESET to triggering input, to ensure a valid output event. 12Minimum time from triggering event to rising edge of RESET, to ensure a valid output event. 13Measured from the LATCH ENABLE input to the point when the AD9500 becomes 8-bit accurate again, after a full-scale change in th e programmed delay. 14Standard 10K and 10KH ECL families operate with a 1.1 mV/ °C drift by design. 15Supply voltages should remain stable within – 5% for normal operation. 16Measured at – 5% of –VS and +VS. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. II – 100% production tested at +25 °C, and sample tested at specified temperatures. III – Periodically sample tested. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% production tested at +25 °C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature ex- tremes for commercial/industrial devices. ORDERING GUIDE Temperature Package Package Model Ranges Descriptions Options AD9500BP –25 °C to +85°C 28-Leadless PLCC (Plastic), Industrial Temperature P-28A AD9500BQ –25 °C to +85°C 24-Lead Cerdip, Industrial Temperature Q-24 AD9500TE –55 °C to +125°C 28-Leaded LCC, Extended Temperature E-28A AD9500TQ –55 °C to +125°C 24-Lead Cerdip, Extended Temperature Q-24 AD9500 –3–REV. D

–4– REV. D PIN FUNCTION DESCRIPTIONS Pin Name Description D4–D6 One of eight digital inputs used to set the programmed delay. D7 (MSB) One of eight digital inputs used to set the programmed delay. D 7 (MSB) is the most significant bit of the digital input word. ECLREF ECL midpoint reference, nominally –1.3 V. Use of the ECL REF allows either of the TRIGGER or RESET inputs to be configured for single-ended ECL inputs. OFFSET ADJUST The OFFSET ADJUST is used to adjust the minimum propagation delay (t PD), by pulling or pushing a small current out of or into the pin. CS CS allows the full-scale range to be extended by using an external timing capacitor. The value of C EXT, connected between CS and +VS, may range from no external capacitance to 0.1 mF+. See RS (CINTERNAL = 10 pF). +VS Positive supply terminal, nominally +5.0 V. TRIGGER Noninverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by the programmed delay, after the triggering event. The programmed delay is set by the digital input word. The TRIGGER input must be driven in conjunction with the TRIGGER input. TRIGGER Inverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by the programmed delay, after the triggering event. The programmed delay is set by the digital input word. The TRIGGER input must be driven in conjunction with the TRIGGER input. RESET Inverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a signal is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will be equal to the “reset propagation delay,” t RD. The RESET input must be driven in conjunction with the RESET input. RESET Noninverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a signal is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will be equal to the “reset propagation delay,” t RD. The RESET input must be driven in conjunction with the RESET input. Q One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic HIGH on the Q output. A “resetting” event at the inputs will produce a logic LOW on the Q output. Q One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic LOW on the Q output. A “resetting” event at the inputs will produce a logic HIGH on the Q output. QR QR output is parallel to the Q output. The QR output is typically used to drive delaying circuits for extend- ing output pulsewidths. A “triggering” event at the inputs will produce a logic LOW on the QR output. A “resetting” event at the inputs will produce a logic HIGH on the QR output. ECL COMMON The collector common for the ECL output stage. The collector common may be tied to +5.0 V, but nor- mally it is tied to the circuit ground for standard ECL outputs. –VS Negative supply terminal, nominally –5.2 V. RS RS is the reference current setting terminal. An external setting resistor, R SET, connected between RS and –VS determines the internal reference current. See C S (250 W £ RSET £ 50 kW ). GROUND The ground return for the TTL and analog inputs. LATCH ENABLE Transparent TTL latch control line. A logic HIGH on the LATCH ENABLE freezes the digital code at the logic inputs. A logic LOW on the LATCH ENABLE allows the internal current levels to be continuously updated through the logic inputs D 0 thru D7. D0 (LSB) One of eight digital inputs used to set the programmed delay. D 0 (LSB) is the least significant bit of the digital input word. D3–D1 One of eight digital inputs used to set the programmed delay.

Figure 1. System Timing Diagram

Figure 2. Input/Output Circuits

–11–REV. D OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Cerdip (Q-24) 1 12 0.310 (7.87) 0.220 (5.59) PIN 1 0.005 (0.13) MIN 0.098 (2.49) MAX SEATING PLANE 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) MAX 1.280 (32.51) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.070 (1.78) 0.030 (0.76) 15° 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20)28-Leaded LCC (E-28A) 28 5 BOTTOM VIEW 25 0.028 (0.71) 0.022 (0.56) 45° TYP 0.015 (0.38) MIN 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) BSC 0.075 (1.91) REF 0.011 (0.28) 0.007 (0.18) R TYP 0.095 (2.41) 0.075 (1.90) 0.150 (3.51) BSC 0.300 (7.62) BSC 0.200 (5.08) BSC 0.075 (1.91) REF 0.458 (11.63) 0.442 (11.23) SQ 0.458 (11.63) MAX SQ 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 28-Leadless PLCC (P-28A) PIN 1 IDENTIFIER TOP VIEW (PINS DOWN) 0.495 (12.57) 0.485 (12.32)SQ 0.456 (11.58) 0.450 (11.43) SQ 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) R 0.050 (1.27) BSC 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16) C1137d–0–4/99PRINTED IN U.S.A.