AD9480

AD9480 8-Bit, 250 MSPS, 3.3 V A/D Converter Data Sheet (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 28

Technical content

8-Bit, 250 MSPS

3.3 V A/D Converter

Rev. A Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.

FEATURES

DNL = ± 0.25 LSB INL = ± 0.26 LSB Single 3.3 V supply operation (3.0 V to 3.6 V) Power dissipation of 590 mW at 250 MSPS

1 V p-p analog input range

Internal 1.0 V reference Single-ended or differential analog inputs LVDS outputs (ANSI 644 levels) Power-down mode Clock duty-cycle stabilizer

APPLICATIONS

Instrumentation and measurement Communications Point-to-point radios Predistortion loops FUNCTIONAL BLOCK DIAGRAM D7–D0 (LVDS) (LVDS) VIN+ VIN– CLK+ CLK– VREF SENSE DCO+ DCO- AGND DrGND DRVDD AVDD AD9480 LVDSBIASPDWN S1 LVDS CLOCK MGMT T&H 8-BIT ADC PIPELINE CORE LOGIC REFERENCE 168 04619-001 Figure 1. GENERAL DESCRIPTION The AD9480 is an 8-bit, monolithic analog-to-digital converter (ADC) optimized for high speed and low power consumption. Small in size and easy to use, the product operates at a

250 MSPS conversion rate, with excellent linearity and dynamic

performance over its full operating range. To minimize system cost and power dissipation, the AD9480 includes an internal reference and track-and-hold circuit. The user only provides a 3.3 V power supply and a differential encode clock. No external reference or driver components are required for many applications. The digital outputs are LVDS (ANSI 644) compatible with an option of twos complement or binary output format. The output data bits are provided in parallel fashion along with an LVDS output clock, which simplifies data capture. Fabricated on an advanced BiCMOS process, the AD9480 is available in a 44-lead surface-mount package (TQFP) specified over the industrial temperature range −40°C to +85°C. PRODUCT HIGHLIGHTS 1. Superior linearity. A DNL of ±0.25 makes the AD9480 suitable for instrumentation and measurement applications. 2. Power-down mode. A power-down function may be exercised to bring total consumption down to 15 mW. 3. LVDS outputs (ANSI-644). LVDS outputs simplify timing and improve noise performance

Rev. A | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

4/05—Rev. 0 to Rev. A 7/04—Revision 0: Initial Version

Rev. A | Page 3 of 28 DC SPECIFICATIONS AVDD = 3.3 V , DRVDD = 3.3 V , TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V , internal reference, differential analog and clock inputs, unless otherwise noted. Table 1. AD9480-250 Parameter Temp Test Level Min Typ Max Unit RESOLUTION 8 Bits ACCURACY No Missing Codes Full VI Guaranteed Offset Error 25°C I −40 +40 mV Gain Error1 25°C I −6.0 +6.0 % FS Differential Nonlinearity (DNL) AD9480BSUZ-250 Full VI −0.5 ±0.28 +0.5 LSB AD9480ASUZ-250 Full VI −0.85 ±0.35 +0.85 LSB Integral Nonlinearity (INL) Full VI −0.9 ±0.26 +0.9 LSB TEMPERATURE DRIFT Offset Error Full V 30 µV/°C Gain Error Full V 0.03 %FS/°C Reference Full V ±0.025 mV/°C REFERENCE Internal Reference Voltage Full VI 0.97 1.0 1.03 V Output Current2 25°C IV 1.5 mA IVREF Input Current3 25°C I 100 µA ISENSE Input Current2 25°C I 10 µA ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range (FS = 1) 4 Full V 1 V p-p Common-Mode Voltage Full VI 1.7 1.9 2.1 V Input Resistance 25°C I 8.6 10 10.7 kΩ Full VI 8.4 10 11.2 kΩ Input Capacitance 25°C V 4 pF Analog Bandwidth, Full Power 25°C V 750 MHz POWER SUPPLY AVDD Full IV 3.0 3.3 3.6 V DRVDD Full IV 3.0 3.3 3.6 V Power Dissipation5 25°C V 590 mW Power-Down Dissipation 25°C V 15 mW IAVDD5 Full VI 145 156 mA IDRVDD5 Full VI 34 38 mA Power Supply Rejection Ratio (PSRR) 25°C V −4.2 mV/V 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and a 1 V p-p differential analog input). 2 Internal reference mode; SENSE = AGND. 3 External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD. 4 In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other. 5 Power dissipation and current measured with rated encode and a dc analog input (outputs static). See for active oper ation. Figure 13

Rev. A | Page 4 of 28 DIGITAL SPECIFICATIONS AVDD = 3.3 V , DRVDD = 3.3 V , TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V , internal reference, differential analog and clock inputs, unless otherwise noted. Table 2. AD9480-250 Parameter Temp Test Level Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Differential Input Full IV 200 mV p-p Common-Mode Voltage1 Full VI 1.4 1.5 1.68 V Input Resistance Full VI 4.2 5.5 6.0 kΩ Input Capacitance 25°C V 4 pF LOGIC INPUTS (PDWN, S1) 2 PDWN Logic 1 Voltage Full IV 2.0 V PDWN Logic 0 Voltage Full IV 0.8 V PDWN Logic 1 Input Current Full VI ±160 µA PDWN Logic 0 input Current Full VI 10 µA PDWN, S1 Input Resistance 25°C V 30 kΩ PDWN, S1 Input Capacitance 25°C V 4 pF DIGITAL OUTPUTS Differential Output Voltage (VOD)3 Full VI 247 454 mV Output Offset Voltage (VOS) Full VI 1.125 1.375 V Output Coding Full IV Twos complement or binary 1 The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V. 2 S1 is a multilevel logic input, see Ta . ble 8 3 LVDSBIAS resistor = 3.74 kΩ.

Rev. A | Page 5 of 28 AC SPECIFICATIONS AVDD = 3.3 V , DRVDD = 3.3 V , TMIN = –40°C, TMAX = +85°C, AIN = –1 dBFS, full scale = 1.0 V , internal reference, differential analog and clock inputs, unless otherwise noted. Table 3. AD9480-250 Parameter Temp Test Level Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 19.7 MHz 25°C V 47 dB fIN = 70.1 MHz 25°C I 45 47 dB fIN = 170 MHz 25°C I 45 46 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 19.7 MHz 25°C V 46.5 dB fIN = 70.1 MHz 25°C I 44.8 46.5 dB fIN = 170 MHz 25°C I 44.8 46.5 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 19.7 MHz 25°C V 7.6 Bits fIN = 70.1 MHz 25°C I 7.3 7.6 Bits fIN = 170 MHz 25°C I 7.3 7.6 Bits WORST SECOND OR THIRD HARMONIC DISTORTION fIN = 19.7 MHz 25°C V −65 dBc fIN = 70.1 MHz 25°C I −65 −60 dBc fIN = 170 MHz 25°C I −65 −60 dBc WORST OTHER fIN = 19.7 MHz 25°C V −70 dBc fIN = 70.1 MHz 25°C I −70 −63 dBc fIN = 170 MHz 25°C I −70 −63 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR)1 fIN = 19.7 MHz 25°C V −65 dBc fIN = 70.1 MHz 25°C I −65 −60 dBc fIN = 170 MHz 25°C I −65 −60 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) fIN1 = 69.3 MHz, fIN2 = 70.3 MHz 25°C V −68 dBc 1 Nyquist bin energy ignored.

AVDD = 3.3 V, DRVDD = 3.3 V, differential clock input, DCS enabled, unless otherwise noted. 1 Valid time is approximately equal to minimum tPD. CLOAD equals 5 pF maximum.

8 CYCLES

Figure 2. Timing Diagram

Rev. A | Page 7 of 28 ABSOLUTE MAXIMUM RATINGS Thermal impedance (θJA) = 46.4°C/W (4-layer PCB). Table 5. Parameter Min Rating Max Rating ELECTRICAL AVDD (With Respect to AGND) −0.5 V +4.0 V DRVDD (With Respect to DRGND) −0.5 V +4.0 V AGND (With Respect to DRGND) −0.5 V +0.5 V Digital I/O (With Respect to DRGND) −0.5 V DRVDD + 0.5 V Analog Inputs (With Respect to AGND) −0.5 V AVDD + 0.5 V ENVIRONMENTAL Operating Temperature −40°C 85°C Junction Temperature 150°C Case Temperature 150°C Storage Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EXPLANATION OF TEST LEVELS Table 6. Level Descriptions I 100% production tested. II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. ESD CAUTION ESD (electrostatic discharge) se nsitive device . Electrostatic charges as high as 4000 V readily accumulate on the human bod y and test eq uipment and can discharge wi thout detection. Although this product features proprietary ESD protection circ uitry, permanent dama ge may occur on devices subjected to high energy electrostatic di scharges. Ther efore, pro per ESD precautions are rec ommended to avoid performan ce degradation or loss of functionality.

Figure 3. Pin Configuration Table 7. Pin Function Descriptions

1 CLK+ Input Clock—True 23 D6_C Data Output Bit 6—Complement

2 CLK− Input Clock—Complement 24 D6_T Data Output Bit 6—True

4 AGND Analog Ground 26 D7_T Data Output Bit 7—True (MSB)

6 DRGND Digital Ground 28 S1 Data Format Select and Duty-Cycle Stabilizer Selection

7 D0_C Data Output Bit 0—Complement (LSB) 29 PDWN Power-Down Selection (AVDD = Power Down)

8 D0_T Data Output Bit 0—True (LSB) 30 AGND Analog Ground

10 D1_T Data Output Bit 1—True 32 AGND Analog Ground

11 D2_C Data Output Bit 2—Complement 33 SENSE Reference Mode Selection (See Table 9)

12 D2_T Data Output Bit 2—True 34 VREF Voltage Reference Input/Output

13 D3_C Data Output Bit 3—Complement 35 AGND Analog Ground

15 DRGND Digital Ground 37 AGND Analog Ground

16 DCO− Data Clock Output—Complement 38 VIN− Analog Input—Complement

17 DCO+ Data Clock Output—True 39 VIN+ Analog Input—True

20 D4_T Data Output Bit 4—True 42 LVDSBIAS LVDS Output Current Adjust

21 D5_C Data Output Bit 5—Complement 43 NC1 No Connect (Leave Floating)

22 D5_T Data Output Bit 5—True 44 AGND Analog Ground

1 Pin 43 will self-bias to 1.5 V. It can be left floating (as recommended) or tied to AVDD or ground with no ill effects.

Rev. A | Page 9 of 28 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the encode command and the instant the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in a Logic 1 state to achieve rated performance; pulse width low is the minimum time that the clock pulse should be left in a low state. See the timing implications of changing tEH in the Clocking the AD9480 section. At a given clock rate, these specifications define an acceptable clock duty cycle. Crosstalk Coupling onto one channel being driven by a low level (−40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically, and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180° and taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits The effective number of bits (ENOB) is calculated by the measured SINAD based on (assuming full-scale input) 6.02 dB1.76−= MEASUREDSINADENOB Full-Scale Input Power Expressed in dBm. Computed by = 001010 .log INPUT FULLSCALE FULLSCALE Z rmsV Power Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK− and the time when all output data bits are within valid logic levels. Noise (For Any Range Within the ADC) This value includes both thermal and quantization noise. ⎛ −−××= 1010001 dBFSdBcdBm noise SignalSNRFSZV . where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SNR is the value for the particular input level. Signal is the signal level within the ADC reported in dB below full scale. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage.

Rev. A | Page 10 of 28 Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (that is, degrades as signal level is lowered) or dBFS (that is, always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (that is, always relates back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic), reported in dBc. Transient Response Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

• Offset binary
• Internal voltage reference POWER CONNECTOR Power is supplied to the board via two detachable 4-pin power strips.

Table 11. Power Connector 1 AVDD, DRVDD, and VCTRL are the minimum required power connections.

2 LVEL16 clock buffer can be powered from AVDD or VCTRL LVEL16 buffer

be driven differentially, and minimizes even-order harmonics. T1, as shown in Figure 41 and Figure 42). position is SENSE = ground, setting the full scale to 1 V p-p. (default) or AVDD by jumper placement at the device. crystal oscillator that can serve as a convenient clock source. Figure 40. XTAL Footprint resistors on R54, R55, R56, and R57 and remove C6 and C5. Jumper E21 or Jumper E22 to Jumper E23.

Rev. A | Page 20 of 28 VOLTAGE REFERENCE The AD9480 has an internal 1 V reference mode. The ADC uses the internal 1 V reference as the default when SENSE is set to ground. An optional on-board external 1.0 V reference (ADR510) can be used by setting the SENSE jumper to AVDD, by placing a jumper on E20 to E3, and by placing a 0 Ω resistor on R36. When using an external programmable reference (R20, R30), the SENSE jumper must be removed. DATA OUTPUTS The off-chip drivers provide LVDS-compatible output levels with an LVDS RSET resistor of 3.74 kΩ. The ADC digital outputs can be terminated on the board by 100 Ω resistors at the connector if receiving logic does not have the required termination resistance. (The on-chip LVDS output drivers require a far-end, 100 Ω differential termination.)

Rev. A | Page 21 of 28 EVALUATION BOARD BILL OF MATERIALS (BOM) Table 12. No. Quantity Reference Designator Device Package Value 1 23 C1 to C6, C10 to C12, C17 to C23, C26 to C28, C31 to C33, C35 Capacitors 0402 0.1 µF 2 1 C13 Capacitor Tantalum (3528) 10 µF 3 4 C7, C14 to C16 Capacitors Tantalum (6032) 10 µF 4 2 J1, J3 SMAs 5 2 P12, P13 4-pin power connector posts Z5.531.3425.0 Wieland 6 2 P12, P13 4-pin power detachable connectors 25.602.5453.0 Wieland 7 2 R22, R27 Resistors 0603 50 Ω 8 10 R2 to R5, R7 to R10, R15, R42 (All not placed) Resistors 0603 100 Ω 9 6 R1, R44, R45, R50, R58, R59 Resistors 0603 1000 Ω 10 1 R41 Resistors 0603 1200 Ω 11 3 R40, R43, R47 Resistors 0603 25 Ω 12 3 R38, R39, R51 Resistors 0603 10 Ω 13 2 R25, R26 Resistors 0603 82 Ω 14 2 R23, R24 Resistors 0603 510 Ω 15 2 R32, R34 Resistors 0603 130 Ω 16 2 R29, R31 Resistors 0603 0 Ω 17 2 R33, R52 Resistors 0603 10 kΩ 18 1 R63 Resistor 0603 3.74 kΩ 19 1 T1 Transformer CD542 Mini-Circuits T1-1WT 20 1 U13 AD8351 MSOP-10 21 1 U2 SN65LVDS1 SN65LVDS1 DBV Not placed 22 1 U14 ADR510 SOT-23 Not placed 23 1 U15 VCC6PECL6 VCC6-QAB-250M000 Not placed 24 1 U1 XO-400 Dip4(14) Not placed 25 1 U12 AD9480 TQFP-44 26 1 U11 MC100LVEL16D S08NB 27 1 T2 ETC1-1-13 1-1 TX Not placed 28 7 C8, C9, C24, C25, C29, C30, and C34 (All not placed) Capacitors 0402 Not placed 29 12 R6, R20, R21, R28, R30, R36, R46, R48, R49, and R55 to R57 (All not placed) Resistors 0603 User-determined 30 18 E5 to E8, E17, E35, E73 to E84 Jumpers 31 1 P10 Output Data Connector 40-pin right angle Digi-Key S2131-20-ND

Figure 41. PCB Schematic (1 of 2)

Figure 42. PCB Schematic (2 of 2)

12.00 BSC SQ

0.08 MAX

Figure 49. 44-Lead Thin Plastic Quad Flat Package [TQFP] 2 Optimized differential nonlinearity. 3 Evaluation board shipped with AD9480BSUZ-250 installed.

Rev. A | Page 27 of 28 NOTES

Rev. A | Page 28 of 28 NOTES ©2005 A nalog D evices, Inc. All rights reserved. Trademarks an d registered tra demarks are the prop erty of their respective owners . D04619–0–4/05(A)