AD9467BCPZRL7-200

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16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter Data Sheet AD9467 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 © 2010–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

75.5 dBFS SNR to 210 MHz at 250 MSPS 90 dBFS SFDR to 300 MHz at 250 MSPS SFDR at 170 MHz at 250 MSPS 92 dBFS at −1 dBFS 100 dBFS at −2 dBFS 60 fs rms jitter Excellent linearity at 250 MSPS DNL = ±0.5 LSB typical INL = ±3.5 LSB typical 2 V p-p to 2.5 V p-p (default) differential full-scale input (programmable) Integrated input buffer External reference support option Clock duty cycle stabilizer Output clock available Serial port control Built-in selectable digital test pattern generation Selectable output data format LVDS outputs (ANSI-644 compatible) 1.8 V and 3.3 V supply operation

APPLICATIONS

Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Communications instrumentation GENERAL DESCRIPTION The AD9467 is a 16-bit, monolithic, IF sampling analog-to- digital converter (ADC). It is optimized for high performance over wide bandwidths and ease of use. The product operates at a

250 MSPS conversion rate and is designed for wireless receivers,

instrumentation, and test equipment that require a high dynamic range. The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances. FUNCTIONAL BLOCK DIAGRAM 16 2 PIPELINE ADC CLOCK AND TIMING MANAGEMENT REF LVDS OUTPUT STAGING AVDD1 (1.8V) DRVDD (1.8V) AVDD2 (3.3V) AVDD3 (1.8V) SPIVDD (1.8V TO 3.3V) XVREFAGND DRGND AD9467 BUFFER VIN+ CLK+ CLK– VIN– CSB SDIO SCLK OR+/OR– D15+/D15– TO D0+/D0– DCO+/DCO– 09029-001 Figure 1. A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. The internal power-down feature supported via the SPI typically consumes less than 5 mW when disabled. Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns. The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range. PRODUCT HIGHLIGHTS 1. IF optimization capability used to improve SFDR. 2. Outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers. 3. Ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture. 4. Packaged in a Pb-free, 72-lead LFCSP package. 5. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of input clock pulse widths. 6. Standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding).

Rev. D | Page 2 of 32 TABLE OF CONTENTS

REVISION HISTORY

2/13—Rev. C to Rev. D 9/11—Rev. B to Rev. C 3/11—Rev. A to Rev. B 2/11—Rev. 0 to Rev. A Changes to Differential Configurations Section and Changes to Addr. (Hex) 15, Bits[2:0], Addr. (Hex) 10, Bits[7:0], Changes to Addr. (Hex) 36, Default Value (Hex) Column and 10/10—Revision 0: Initial Version

Rev. D | Page 3 of 32 SPECIFICATIONS internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. Table 1. AD9467BCPZ-200 AD9467BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Unit RESOLUTION 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −150 0 +150 −150 0 +150 LSB TEMPERATURE DRIFT Offset Error Full ±0.020 ±0.023 %FSR/°C Gain Error Full ±0.011 ±0.036 %FSR/°C ANALOG INPUTS Common-Mode Voltage 25°C 2.3 2.15 V Differential Input Resistance 25°C 530 530 Ω Differential Input Capacitance 25°C 3.5 3.5 pF Full Power Bandwidth 25°C 900 900 MHz XVREF INPUT Input Voltage Full 1 1.25 1 1.25 V Input Capacitance Full 3 3 pF POWER SUPPLY IAVDD1 Full 485 536 580 514 567 618 mA IAVDD2 Full 49 55 61 49 55 61 mA IAVDD3 Full 21 24 27 27 31 35 mA IDRVDD Full 35 38 41 36 40 43 mA Power-Down Dissipation Full 4.4 90 4.4 90 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

Rev. D | Page 4 of 32 AC SPECIFICATIONS 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. Table 2. AD9467BCPZ-200 AD9467BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Unit ANALOG INPUT FULL SCALE 2.5 2/2.5 2.5 2/2.5 V p-p SIGNAL-TO-NOISE RATIO (SNR) fIN = 5 MHz 25°C 74.6/76.4 74.7/76.4 dBFS fIN = 97 MHz Full 73.8 dBFS fIN = 140 MHz 25°C 74.3/76.0 74.4/76.0 dBFS fIN = 170 MHz Full 72.3 dBFS fIN = 210 MHz 25°C 73.9/75.5 74.0/75.5 dBFS fIN = 300 MHz 25°C 73.5/74.7 73.3/74.6 dBFS SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 5 MHz 25°C 74.6/76.3 74.6/76.3 dBFS fIN = 97 MHz Full 73.1 dBFS fIN = 140 MHz 25°C 74.3/75.9 74.4/76.0 dBFS fIN = 170 MHz Full 71.8 dBFS fIN = 210 MHz 25°C 73.9/75.3 73.9/75.4 dBFS fIN = 300 MHz 25°C 73.3/74.3 73.1/74.4 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 5 MHz 25°C 12.1/12.4 12.1/12.4 Bits fIN = 97 MHz 25°C 12.1/12.4 12.1/12.3 Bits fIN = 97 MHz Full Bits fIN = 140 MHz 25°C 12.1/12.3 12.1/12.3 Bits fIN = 170 MHz 25°C 12.0/12.3 12.0/12.3 Bits fIN = 170 MHz Full Bits fIN = 210 MHz 25°C 12.0/12.2 12.0/12.2 Bits fIN = 300 MHz 25°C 11.9/12.0 11.9/12.1 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) (INCLUDING SECOND AND THIRD HARMONIC DISTORTION)2 fIN = 5 MHz 25°C 95/95 98/97 dBFS fIN = 97 MHz 25°C 86 95/95 95/93 dBFS fIN = 97 MHz Full 83 dBFS fIN = 140 MHz 25°C 94/93 94/95 dBFS fIN = 170 MHz 25°C 95/90 84 93/92 dBFS fIN = 170 MHz Full 84 dBFS fIN = 210 MHz 25°C 93/88 93/92 dBFS fIN = 300 MHz 25°C 92/86 93/90 dBFS SPURIOUS-FREE DYNAMIC RANGE (SFDR) (INCLUDING SECOND AND THIRD HARMONIC DISTORTION)2 fIN = 5 MHz @ −2 dB Full Scale Full 100/96 100/100 dBFS fIN = 97 MHz @ −2 dB Full Scale Full 100/98 97/97 dBFS fIN = 140 MHz @ −2 dB Full Scale Full 98/96 100/95 dBFS fIN = 170 MHz @ −2 dB Full Scale Full 96/93 100/100 dBFS fIN = 210 MHz @ −2 dB Full Scale Full 94/93 93/93 dBFS fIN = 300 MHz @ −2 dB Full Scale Full 90/89 90/90 dBFS

Rev. D | Page 5 of 32 AD9467BCPZ-200 AD9467BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Unit WORST OTHER (EXCLUDING SECOND AND THIRD HARMONIC DISTORTION)2 fIN = 5 MHz 25°C 96/98 98/97 dBFS fIN = 97 MHz 25°C 86 97/97 97/93 dBFS fIN = 97 MHz Full 83 dBFS fIN = 140 MHz 25°C 97/96 97/95 dBFS fIN = 170 MHz 25°C 98/98 90 97/93 dBFS fIN = 170 MHz Full 87 dBFS fIN = 210 MHz 25°C 96/97 97/95 dBFS fIN = 300 MHz 25°C 95/95 97/95 dBFS TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS @ 2.5 V p-p FS fIN1 = 70 MHz, fIN2 = 72 MHz 25°C 95 97 dBFS fIN1 = 170 MHz, fIN2 = 172 MHz 25°C 93 91 dBFS 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 See the SFDR Optimization—Buffer Current Adjustment section for optimum settings.

Rev. D | Page 6 of 32 DIGITAL SPECIFICATIONS internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. Table 3. AD9467BCPZ-200 AD9467BCPZ-250 Parameter1 Temp Min Typ Max Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 250 mV p-p Input Common-Mode Voltage Full 0.8 0.8 V Input Resistance (Differential) 25°C 20 20 kΩ Input Capacitance 25°C 2.5 2.5 pF LOGIC INPUTS (SCLK, CSB, SDIO) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0.3 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 0.5 0.5 pF LOGIC OUTPUT (SDIO)3 Logic 1 Voltage (IOH = 800 μA) Full 1.7/3.1 1.7/3.1 V Logic 0 Voltage (IOL = 50 μA) Full 0.3 0.3 V DIGITAL OUTPUTS (D0+ to D15+, D0− to D15−, DCO+, DCO−, OR+, OR−) Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 247 545 247 545 mV Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 V Output Coding (Default) Offset binary Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This depends on if SPIVDD is tied to a 1.8 V or 3.3 V supply.

internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Can be adjusted via the SPI interface. 3 Measurements were made using a part soldered to FR-4 material. Figure 2. 16-Bit Output Data Timing

Rev. D | Page 8 of 32 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter With Respect To Rating Electrical AVDD1, AVDD3 AGND −0.3 V to +2.0 V AVDD2, SPIVDD AGND −0.3 V to +3.9 V DRVDD DRGND −0.3 V to +2.0 V AGND DRGND −0.3 V to +0.3 V AVDD2, SPIVDD AVDD1, AVDD3 −2.0 V to +3.9 V AVDD1, AVDD3 DRVDD −2.0 V to +2.0 V AVDD2, SPIVDD DRVDD −2.0 V to +3.9 V Digital Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−) DRGND −0.3 V to DRVDD + 0.2 V CLK+, CLK− AGND −0.3 V to AVDD1 + 0.2 V VIN+, VIN− AGND −0.3 V to +3.6 V XVREF AGND −0.3 V to AVDD1 + 0.2 V SCLK, CSB, SDIO AGND −0.3 V to SPIVDD + 0.2 V Environmental Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Storage Temperature Range (Ambient) −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL IMPEDANCE Table 6. Air Flow Velocity (m/sec) θJA1, 2 θJB1, 3, 4 θJC1, 5 Unit 1.0 13.7°C/W N/A N/A °C/W 2.5 12.3°C/W N/A N/A °C/W 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per JEDEC JESD51-8 (still air). 4 N/A = not applicable. 5 Per MIL-STD 883, Method 1012.1. ESD CAUTION

1. EXPOSED THERMAL PAD MUST BE CONNECTED TO AGND.

Figure 3. Pin Configuration, Top View Table 7. Pin Function Descriptions 0 EPAD Exposed Paddle. The exposed paddle must be connected to AGND. 42, 44 AVDD3 1.8 V Analog Supply. 17, 38 DRGND Digital Output Driver Ground. 18, 37 DRVDD 1.8 V Digital Output Driver Supply. 67 VIN− Analog Input Complement. 6 CLK− Clock Input Complement. 19 D1−/D0− D1 and D0 (LSB) Digital Output Complement. 20 D1+/D0+ D1 and D0 (LSB) Digital Output True. 21 D3−/D2− D3 and D2 Digital Output Complement. 22 D3+/D2+ D3 and D2 Digital Output True. 23 D5−/D4− D5 and D4 Digital Output Complement. 24 D5+/D4+ D5 and D4 Digital Output True. 25 D7−/D6− D7 and D6 Digital Output Complement. 26 D7+/D6+ D7 and D6 Digital Output True. 29 D9−/D8− D9 and D8 Digital Output Complement. 30 D9+/D8+ D9 and D8 Digital Output True. 31 D11−/D10− D11 and D10 Digital Output Complement. 32 D11+/D10+ D11 and D10 Digital Output True. 33 D13−/D12− D13 and D12 Digital Output Complement. 34 D13+/D12+ D13 and D12 Digital Output True. 35 D15−/D14− D15 (MSB) and D14 Digital Output Complement.

Rev. D | Page 10 of 32 Pin No. Mnemonic Description 36 D15+/D14+ D15 (MSB) and D14 Digital Output True. 27 DCO− Data Clock Digital Output Complement. 28 DCO+ Data Clock Digital Output True. 39 OR− Out-of-Range Digital Output Complement. 40 OR+ Out-of-Range Digital Output True. 47 DNC Do Not Connect (Leave Pin Floating). 48 SDIO Serial Data Input/Output. 49 SCLK Serial Clock. 50 CSB Chip Select Bar. 57 XVREF External VREF Option.

Figure 28. Two-Tone FFT with fIN1 = 70 MHz and fIN2 = 72 MHz,

2.5 V p-p FS, AD9467-200

Figure 29. Two-Tone FFT with fIN1 = 170 MHz and fIN2 = 172 MHz, Figure 30. Two-Tone FFT with fIN1 = 70 MHz and fIN2 = 72 MHz,

2.5 V p-p FS, AD9467-250

Figure 31. Two-Tone FFT with fIN1 = 170 MHz and fIN2 = 172 MHz, Figure 32. SNR/SFDR vs. Analog Input Level, fIN = 97.3 MHz, 2.5 V p-p FS, Figure 33. SNR/SFDR vs. Analog Input Level, fIN = 97.3 MHz, 2.5 V p-p FS,

Figure 34. SINAD/SFDR vs. Temperature, fIN = 97.3 MHz, Figure 35. SINAD/SFDR vs. Temperature, fIN = 97.3 MHz, Figure 36. INL, fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-200 Figure 37. DNL, fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-200 Figure 38. INL, fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-250 Figure 39. DNL, fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-250

(CLK+ and CLK−) should be clocked with a differential signal. and require no additional biasing. are critical to low jitter performance. Figure 58. Transformer-Coupled Differential Clock Figure 60. The AD9510/AD9511/AD9512/AD9513/AD9514/ family of clock drivers offers excellent jitter performance. 150Ω RESISTORS ARE OPTIONAL. Figure 59. Differential PECL Sample Clock 150Ω RESISTORS ARE OPTIONAL. Figure 60. Differential LVDS Sample Clock applications are particularly sensitive to jitter (see Figure 61). where aperture jitter may affect the dynamic range of the AD9467. be retimed by the original clock at the last step. performance as it relates to ADCs.

16 BITS

14 BITS

12 BITS

10 BITS

8 BITS

Figure 61. Ideal SNR vs. Input Frequency and Jitter

patterns may not adhere to the data format select option. instead of all 1s (see Table 9 for the initial values). AD9467 inverts the bit stream with relation to the ITU standard. Table 9. PN Sequence input is above or below the input full scale of the converter. and the OR bit going high is the pipeline latency of the part. and SDIO information is ignored. Table 10. Flexible Output Test Modes

0000 Off (default) N/A1 N/A1 N/A1

0001 Midscale short 1000 0000 0000 0000 Same Yes

0100 Checkerboard 1010 1010 1010 1010 0101 0101 0101 0101 No

0101 PN sequence long2 N/A1 N/A1 Yes

0110 PN sequence short2 N/A1 N/A1 Yes

0111 One-/zero-word toggle 1111 1111 1111 1111 0000 0000 0000 0000 No

2 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths to verify data capture to the receiver.

Interfacing to High Speed ADCs via SPI. low control that enables or disables the read and write cycles. Table 11. Serial Port Pins synchronize serial interface reads and writes. CSB remains low until the communication cycle is complete. memory transfers without requiring additional instructions. input to an output at the appropriate point in the serial frame. an input during write phases and as an output during readback. pins that can be connected together and the resulting VOH level. Figure 67. SDIO Pin Loading the ADC (see the AN-812 Application Note).

Figure 68. Serial Timing Details Table 12. Serial Timing Definitions

(Address 0x08 to Address 0x107). Interfacing to High Speed ADCs via SPI. when writing the default values suggested in this data sheet. reserved and have a 0 written into their registers during power-up. Table 13, where an X refers to an undefined feature. Table 13. Memory Map Register1

Rev. D | Page 29 of 32 Addr. (Hex) Parameter Name (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 Default Value (Hex) Default Notes/ Comments ADC Functions 08 modes X X X X X X Internal power- down mode 00 = chip run (default) 01 = full power- down 0x00 Determines various generic modes of chip operation. 0D test_io X X Reset PN long gen 1 = on 0 = off (default) Reset PN short gen 1 = on 0 = off (default) Output test mode—see Table 10 in the Digital Outputs and Timing section 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one-/zero-word toggle 0x00 When this register is set, the test data is placed on the output pins in place of normal data. 0F adc_input XVREF 1 = on 0 = off (default) X X X X Analog disconnect 1 = on 0 = off (default) X X 0x00 Analog input functions. 10 offset 8-bit digital offset adjustment 0111 1111 = 127 0111 1110 = 126 0000 0010 = 2 0000 0001 = 1 0000 0000 = 0 1111 1111 = -1 1111 1110 = -2 1000 0001 = -126 1000 0000 = -127 0x00 Bipolar, twos complement digital offset adjustment in LSBs. 14 output_mode X 0 X Digital output disable 1 = on 0 = off (default)

1 Output

1 = on 0 = off (default) Data format select 00 = offset binary (default) 01 = twos complement 10 = Gray code 0x08 Configures the outputs and the format of the data. 15 output_adjust X X X X Coarse LVDS adjust 0 = 3.0 mA (default) 1 = 1.71 mA Output current drive adjust 001 = 3.0 mA (default) 010 = 2.79 mA 011 = 2.57 mA 100 = 2.35 mA 101 = 2.14 mA 110 = 1.93 mA 111 = 1.71 mA 0x00 Determines LVDS or other output properties. 16 output_phase DCO output invert 1 = on 0 = off (default) X X X X X X X 0x00 Determines digital clock output phase. 18 vref X X X X Input full-scale range adjust 0000 = 2.0 V p-p 0110 = 2.1 V p-p 0111 = 2.2 V p-p 1000 = 2.3 V p-p 1001 = 2.4 V p-p 1010 = 2.5 V p-p (default) 0x0A

Rev. D | Page 30 of 32 Addr. (Hex) Parameter Name (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 Default Value (Hex) Default Notes/ Comments 2C analog_input X X X X X Input coupling mode 0 = ac coupling (default) 1 = dc coupling X X 0x00 Determines the input coupling mode. 36 Buffer Current Select 1 110101 = +530% 110100 = +520% 001000 = +80% (default) 000010 = +20% 000001 = +10% 000000 = nominal, 0% 111111 = −10% 111110 = −20% 110111 = −90% 110110 = −100% 1 0 0x22

107 Buffer Current

110101 = +530% 110100 = +520% 001000 = +80% (default) 000010 = +20% 000001 = +10% 000000 = nominal, 0% 111111 = −10% 111110 = −20% 110111 = −90% 110110 = −100% X X 0x20 1 X = undefined feature, don’t write.

optimum performance can be easily achieved. the PCB. These vias should be solder-filled or plugged. Figure 69. Typical PCB Layout

0.20 REF

0.80 MAX

0.05 MAX

0.02 NOM

8.50 REF

0.25 MIN

Figure 70. 72-Lead Lead Frame Chip Scale Package, Exposed Pad [LFCSP_VQ] reg istered trademarks are the property of their respective owners.