AD9460

AD9460 16-Bit, 80 MSPS/105 MSPS ADC Data Sheet (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 32

Technical content

16-Bit, 80 MSPS/105 MSPS ADC AD9460 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

105 MSPS guaranteed sampling rate (AD9460-105)

79.4 dBFS SNR/91 dBc SFDR with 10 MHz input (3.4 V p-p input, 80 MSPS) 78.3 dBFS SNR/ with 170 MHz input (4.0 V p-p input, 80 MSPS) 77.8 dBFS SNR/87 dBc SFDR with 170 MHz input (3.4 V p-p input, 80 MSPS) 77.2 dBFS SNR/84 dBc SFDR with 170 MHz input (3.4 V p-p input, 105 MSPS) 90 dBFS two-tone SFDR with 139 MHz/140 MHz input (3.4 V p-p input, 105 MSPS) 60 fsec rms jitter Excellent linearity DNL = ±0.5 LSB typical INL = ±3.0 LSB typical 2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output data capture clock available

3.3 V and 5 V supply operation

VIN– CLK– DCO AVDD1 AVDD2 DCS MODE DFS OUTPUT MODE T/H BUFFER PIPELINE ADC OR D15 TO D0 REF REFBSENSE REFT 06006-001 Figure 1.

APPLICATIONS

Multicarrier, multimode, cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Communications instrumentation GENERAL DESCRIPTION The AD9460 is a 16-bit, monolithic, sampling, analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use. The AD9460 operates up to 105 MSPS, providing a superior signal- to-noise ratio (SNR) for instrumentation, medical imaging, and radar receivers using baseband (<100 MHz) and IF frequencies. The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances. Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data mode. The AD9460 is available in a Pb-free, 100-lead, surface-mount, plastic package (TQFP_EP) specified over the industrial tem- perature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. True 16-bit linearity. 2. High performance: outstanding SNR performance for baseband IFs in data acquisition, instrumentation, magnetic resonance imaging, and radar receivers. 3. Ease of use: on-chip reference and high input impedance, track-and-hold with adjustable analog input range, and an output clock simplifies data capture. 4. Packaged in a Pb-free, 100-lead TQFP/EP . 5. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of clock pulse widths. 6. Out-of-range (OR) outputs indicate when the signal is beyond the selected input range.

Rev. 0 | Page 2 of 32 TABLE OF CONTENTS

REVISION HISTORY

7/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 32 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , LVDS mode, specified minimum sampling rate, 3.4 V p-p differential input, internal trimmed reference (1.0 V mode), analog input amplitude = −1.0 dBFS, DCS = AGND (on), SFDR = AGND, unless otherwise noted. Table 1. AD9460BSVZ-80 AD9460BSVZ-105 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION Full 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Gain Error 25°C −3 ±0.5 +3 −3 ±0.5 +3 % FSR Integral Nonlinearity (INL)1 25°C −6 ±3 +6 −6 ±3 +6 LSB VOLTAGE REFERENCE Output Voltage VREF = 1.7 V Full 1.7 1.7 V Load Regulation @ 1.0 mA Full ±2 ±2 mV Reference Input Current (External VREF = 1.7 V) Full 350 350 μA INPUT REFERRED NOISE 25°C 2.4 2.5 LSB rms ANALOG INPUT Input Span VREF = 1.7 V Full 3.4 3.4 V p-p VREF = 1.0 V Full 2.0 2.0 V p-p Internal Input Common-Mode Voltage Full 3.5 3.5 V External Input Common-Mode Voltage Full 3.2 3.9 3.2 3.9 V Input Resistance2 Full 1 1 kΩ Input Capacitance2 Full 6 6 pF POWER SUPPLIES Supply Voltages Supply Currents1 AVDD1 Full 290 310 337 373 mA AVDD21, 3 Full 101 110 116 133 mA IDRVDD1—LVDS Outputs Full 70 78.5 71 81 mA IDRVDD1—CMOS Outputs Full 14 14 mA PSRR Offset Full 1 1 mV/V Gain Full 0.2 0.2 %/V POWER CONSUMPTION3 LVDS Outputs Full 1.7 1.8 1.9 2.2 W CMOS Outputs (DC Input) Full 1.5 1.7 W 1 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. 2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure. 3 For SFDR = AVDD1, IAVDD2 power increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.

Rev. 0 | Page 4 of 32 AC SPECIFICATIONS AVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , LVDS mode, specified minimum sample rate, 3.4 V p-p differential input, internal trimmed reference (1.7 V mode), AIN = −1.0 dBFS, DCS = AGND (on), SFDR = AGND, unless otherwise noted. Table 2. AD9460BSVZ-80 AD9460BSVZ-105 Parameter Temp Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 10 MHz 25°C 77.6 78.4 77.2 78.1 dB Full 77.4 76.9 fIN = 170 MHz 25°C 76.1 76.8 75.0 76.2 dB Full 75.0 74.5 fIN = 225 MHz 25°C 75.7 75.2 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 10 MHz 25°C 76.1 78.0 75.2 77.4 dB Full 74.4 74.5 fIN = 170 MHz 25°C 74.0 76.1 72.0 75.1 dB Full 72.1 71.2 fIN = 225 MHz 25°C 74.6 73.6 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 12.8 12.7 bits fIN = 170 MHz 25°C 12.5 12.4 bits fIN = 225 MHz 25°C 12.3 12.1 bits SPURIOUS-FREE DYNAMIC RANGE (SFDR, SECOND OR THIRD HARMONIC) fIN = 10 MHz 25°C 80 91 80 88 dBc Full 78 76 fIN = 170 MHz 25°C 80 87 78 84 dBc Full 78 74 fIN = 225 MHz 25°C 82 81 dBc WORST SPUR EXCLUDING SECOND OR THIRD HARMONICS fIN = 10 MHz 25°C 94 100 92 98 dBc Full 91 91 fIN = 170 MHz 25°C 90 98 89 98 dBc Full 88 85 fIN = 225 MHz 25°C 97 92 dBc TWO-TONE SFDR fIN = 139.6 MHz @ −7 dBFS, 140.6 MHz @ −7 dBFS 25°C 89 90 dBFS ANALOG BANDWIDTH Full 615 615 MHz

Rev. 0 | Page 5 of 32 DIGITAL SPECIFICATIONS Table 3. AD9460BSVZ-80/105 Parameter Temp Min Typ Max Unit CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Full 2.0 V Low Level Input Voltage Full 0.8 V High Level Input Current Full 200 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 2 pF DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)1 DRVDD = 3.3 V High Level Output Voltage Full 3.25 V Low Level Output Voltage Full 0.2 V DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR) VOD Differential Output Voltage2 Full 247 545 mV VOS Output Offset Voltage Full 1.125 1.375 V CLOCK INPUTS (CLK+, CLK−) Differential Input Voltage Full 0.2 V Common-Mode Voltage Full 1.3 1.5 1.6 V Input Resistance Full 1.1 1.4 1.7 kΩ Input Capacitance Full 2 pF 1 Output voltage levels measured with 5 pF load on each output. 2 LVDS RTERM = 100 Ω. SWITCHING SPECIFICATIONS AVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , unless otherwise noted. Table 4. AD9460BSVZ-80 AD9460BSVZ-105 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Maximum Conversion Rate Full 80 105 MSPS Minimum Conversion Rate Full 1 1 MSPS CLK Period Full 12.5 9.5 ns CLK Pulse Width High1 (tCLKH) Full 5.0 3.8 ns CLK Pulse Width Low1 (tCLKL) Full 5.0 3.8 ns DATA OUTPUT PARAMETERS Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+) Full 3.35 3.35 ns Pipeline Delay (Latency) Full 13 13 cycles Aperture Delay (tA) Full ns Aperture Uncertainty (Jitter, tJ) Full 60 60 fs, rms 1 With duty cycle stabilizer (DCS) enabled. 2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load. 3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

13 CLOCK CYCLES

Figure 2. LVDS Mode Timing Diagram Figure 3. CMOS Timing Diagram

Rev. 0 | Page 7 of 32 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating ELECTRICAL AVDD1 to AGND −0.3 V to +4 V AVDD2 to AGND −0.3 V to +6 V DRVDD to DGND −0.3 V to +4 V AGND to DGND −0.3 V to +0.3 V AVDD1 to DRVDD −4 V to +4 V AVDD2 to DRVDD −4 V to +6 V AVDD2 to AVDD1 −4 V to +6 V D0± Through D15± to DGND −0.3 V to DRVDD + 0.3 V CLK+/CLK− to AGND −0.3 V to AVDD1 + 0.3 V OUTPUT MODE, DCS MODE, and DFS to AGND −0.3 V to AVDD1 + 0.3 V VIN+, VIN− to AGND −0.3 V to AVDD2 + 0.3 V VREF to AGND −0.3 V to AVDD1 + 0.3 V SENSE to AGND −0.3 V to AVDD1 + 0.3 V REFT, REFB to AGND −0.3 V to AVDD1 + 0.3 V ENVIRONMENTAL Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering 10 sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The heat sink of the AD9460 package must be soldered to ground. Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the θ JA. It is required that the exposed heat sink be soldered to the ground plane. Table 6. Package Type θJA1 θJB 2 θJC 3 Unit 100-Lead TQFP_EP 19.8 8.3 2 °C/W 1 Typical θJA = 19.8°C/W (heat sink soldered) for a multilayer board in still air. 2 Typical θJB = 8.3°C/W (heat sink soldered) for a multilayer board in still air.

3 Typical θJC = 2°C/W (junction to exposed heat sink) represents the thermal

resistance through heat sink path ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD pr ecautions are recommended to avoid performance degradation or loss of functionality.

74 D10+

73 D10–

72 D9+

69 D8–

70 D8+

71 D9–

75 DRGND

68 DCO+

67 DCO–

66 D7+

64 DRVDD

63 DRGND

62 D6+

61 D6–

60 D5+

59 D5–

58 D4+

57 D4–

56 D3+

55 D3–

54 D2+

53 D2–

52 D1+

51 D1–

65 D7–

Figure 4. 100-Lead TQFP_EP Pin Configuration in LVDS Mode Table 7. Pin Function Descriptions—100-Lead TQFP_EP in LVDS Mode 1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS. 2 DNC Do Not Connect. This pin should float. 3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode. OUTPUT MODE = 1 (AVDD1) for LVDS outputs. 4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND. AVDD1 3.3 V (±5%) Analog Supply. input range); connect to AVDD1 for external reference. programming resistors. Decouple to ground with 0.1 μF and 10 μF capacitors.

Rev. 0 | Page 9 of 32 Pin No. Mnemonic Description 10 REFT Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB (Pin 11) with 0.1 μF and 10 μF capacitors. 11 REFB Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT (Pin 10) with 0.1 μF and 10 μF capacitors. 12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%). 22 VIN+ Analog Input—True. 23 VIN− Analog Input—Complement. 40 CLK+ Clock Input—True. 41 CLK− Clock Input—Complement. 47, 63, 75, 87 DRGND Digital Output Ground. 48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V). 49 D0− (LSB) D0 Complement Output Bit (LVDS Levels). 50 D0+ D0 True Output Bit. 51 D1− D1 Complement Output Bit. 52 D1+ D1 True Output Bit. 53 D2− D2 Complement Output Bit. 54 D2+ D2 True Output Bit. 55 D3− D3 Complement Output Bit. 56 D3+ D3 True Output Bit. 57 D4− D4 Complement Output Bit. 58 D4+ D4 True Output Bit. 59 D5− D5 Complement Output Bit. 60 D5+ D5 True Output Bit. 61 D6− D6 Complement Output Bit. 62 D6+ D6 True Output Bit. 65 D7− D7 Complement Output Bit. 66 D7+ D7 True Output Bit. 67 DCO− Data Clock Output—Complement. 68 DCO+ Data Clock Output—True. 69 D8− D8 Complement Output Bit. 70 D8+ D8 True Output Bit. 71 D9− D9 Complement Output Bit. 72 D9+ D9 True Output Bit. 73 D10− D10 Complement Output Bit. 74 D10+ D10 True Output Bit. 77 D11− D11 Complement Output Bit. 78 D11+ D11 True Output Bit. 79 D12− D12 Complement Output Bit. 80 D12+ D12 True Output Bit. 81 D13− D13 Complement Output Bit. 82 D13+ D13 True Output Bit. 83 D14− D14 Complement Output Bit. 84 D14+ D14 True Output Bit. 85 D15− D15 Complement Output Bit. 86 D15+ (MSB) D15 True Output Bit. 89 OR− Out-of-Range Complement Output Bit. 90 OR+ Out-of-Range True Output Bit. 100 SFDR SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for optimum SFDR performance; power dissipation from AVDD2 increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.

74 D4+

73 D3+

72 D2+

69 DNC

70 D0+ (LSB)

71 D1+

66 DNC

62 DNC

61 DNC

60 DNC

59 DNC

58 DNC

57 DNC

56 DNC

55 DNC

54 DNC

53 DNC

52 DNC

51 DNC

65 DNC

Figure 5. 100-Lead TQFP_EP Pin Configuration in CMOS Mode Table 8. Pin Function Descriptions—100-Lead TQFP_EP in CMOS Mode 1 DCS MODE Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS. 2, 49 to 62, 65 to 66, 69 DNC Do Not Connect. These pins should float. 3 OUTPUT MODE CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode. OUTPUT MODE = 1 (AVDD1) for LVDS outputs. 4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement. DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND. AVDD1 3.3 V (±5%) Analog Supply. input range); connect to AVDD1 for external reference. resistors. Decouple to ground with 0.1 μF and 10 μF capacitors. 11) with 0.1 μF and 10 μF capacitors.

Rev. 0 | Page 11 of 32 Pin No. Mnemonic Description 11 REFB Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT (Pin 10) with 0.1 μF and 10 μF capacitors. 12 to 17, 25 to 31, 35, 37 AVDD2 5.0 V Analog Supply (±5%). 22 VIN+ Analog Input—True. 23 VIN− Analog Input—Complement. 40 CLK+ Clock Input—True. 41 CLK− Clock Input—Complement. 47, 63, 75, 87 DRGND Digital Output Ground. 48, 64, 76, 88 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V). 67 DCO− Data Clock Output—Complement. 68 DCO+ Data Clock Output—True. 70 D0+ (LSB) D0 True Output Bit (CMOS Levels). 71 D1+ D1 True Output Bit. 72 D2+ D2 True Output Bit. 73 D3+ D3 True Output Bit. 74 D4+ D4 True Output Bit. 77 D5+ D5 True Output Bit. 78 D6+ D6 True Output Bit. 79 D7+ D7 True Output Bit. 80 D8+ D8 True Output Bit. 81 D9+ D9 True Output Bit. 82 D10+ D10 True Output Bit. 83 D11+ D11 True Output Bit. 84 D12+ D12 True Output Bit. 85 D13+ D13 True Output Bit. 86 D14+ D14 True Output Bit. 89 D15+ (MSB) D15 True Output Bit. 90 OR+ Out-of-Range True Output Bit. 100 SFDR SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for optimum SFDR performance; power dissipation from AVDD2 increases by ~70 mW for the AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.

Figure 24. 105 MSPS, SNR/SFDR vs. Analog Input Frequency, 3.4 V p-p Figure 25. 105 MSPS, SNR/SFDR vs. Analog Input Frequency,

3.4 V p-p, CMOS Mode

Figure 26. 105 MSPS, 170.3 MHz SNR/SFDR vs. Analog Input Level Figure 27. 105 MSPS, SNR/SFDR vs. Analog Input Common Mode Figure 28. 105 MSPS, 170.3 MHz SNR/SFDR vs. Analog Input Level, Figure 29. 80 MSPS, SNR/SFDR vs. Analog Input Frequency,

Figure 40. Gain vs. Temperature Figure 41. SNR vs. Analog Input Range Figure 42. SFDR vs. Analog Input Range

105 SNR dB

80 SNR dB

80 SFDR dBc

105 SFDR dBc85

Figure 43. Single-Tone SNR/SFDR vs. Sample Rate, 170.3 MHz

Rev. 0 | Page 19 of 32 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter, tJ) The sample-to-sample variation in aperture delay. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 16-bit resolution indicates that all 65,536 codes must be present over all operating ranges. Integral Nonlinearity (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may be a harmonic. SFDR can be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale). Total Harmonic Distortion (THD) The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: ( ) 6.02 1.76−= SINADENOB Gain Error The first code transition should occur at an analog value of ½ LSB above negative full scale. The last transition should occur at an analog value of 1½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Maximum Conversion Rate The clock rate at which parametric testing is performed. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Offset Error The major carry transition should occur for an analog value of ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Output Propagation Delay (tPD) The delay between the clock rising edge and the time when all bits are within valid logic levels. Power-Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at the maximum limit. Temp er atu re D r i ft The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX.

3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT

internal reference or an externally applied reference voltage. analog-to-digital conversion core and establish its input span. the reference pin for either an internal or an external reference. Figure 44. Internal Reference Configuration Figure 45. Programmable Reference Configuration

Table 9. Reference Configuration Summary

0.2 V to VREF

Figure 40 for gain variation vs. temperature. even-order harmonics. There are also benefits at the PCB level. analog input configurations. Figure 46. Differential Analog Input Range for VREF = 1.7 V to the 3.5 V bias voltage and to the input of a differential buffer. differential signals (see Figure 47). Figure 47. Transformer-Coupled Analog Input Circuit shown in the evaluation board schematic (see Figure 50). advised to give careful thought to the clock source.

LVDS-compatible output levels via Pin 3 (OUTPUT MODE). Figure 3 for detailed timing diagrams. format. Table 10 summarizes the output coding. the pin assignment for the device is as defined in Table 7. high (AVDD1, 3.3 V) disables the controller. AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105. Table 10. Digital Output Coding

Figure 50. Evaluation Board Schematic

Figure 51. Evaluation Board Schematic, Encode, Optional Encode and Power Options

Figure 52. Evaluation Board Schematic, Bypass Capacitors

Figure 53. Evaluation Board Schematic

Table 11. AD9460 Customer Evaluation Board Bill of Materials Item Qty. Reference Designator Description Package Value1 Manufacturer Mfg. Part No.

Rev. 0 | Page 30 of 32 Item Qty. Reference Designator Description Package Value1 Manufacturer Mfg. Part No. 27 2 C1, C44, C551 Capacitor TAJD 10 μF, DNP Digi-Key Corporation 478-1699-2 28 22 C13, C14, C16, C17, C19, C29, C31, C36, C37, C41, C45, C49, C61, C69, C70, C72, C73, C75, C93, C108, C109, C1101 CAP402 402 DNP 29 1 C981 Capacitor 805 DNP Digi-Key Corporation 490-1717-1-ND

30 E151 Header EHOLE DNP Mouser

31 J51 SMA SMA DNP Digi-Key

32 P61 Header C40MS DNP Samtec, Inc. TSW-120-08-L-D-RA 33 2 R1, R21 BRES402 402 DNP 34 3 R5, R7, R91 BRES402 402 DNP 35 1 U21 ECLOSC DIP4(14) DNP 36 4 H1, H2, H3, H41 MTHOLE6 MTHOLE6 DNP 37 2 T1, T21 Balun transformer SM-22 DNP M/A-COM ETC1-1-13 38 1 T51 Transformer ADT1-1WT DNP Mini-Circuits ADT1-WT 39 2 P21, P221 Term strip PTMICRO4 DNP Newark Electronics 1 DNP = do not populate. All items listed in this category are not populated.

14.00 BSC SQ

16.00 BSC SQ

0.50 BSC

0.08 MAX

9.50 SQEXPOSED

1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. Figure 54. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

Rev. 0 | Page 32 of 32 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06006-0-7/06(0)