AD9446

AD9446 16-Bit, 80/100 MSPS, ADC Data Sheet (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 36

Technical content

16-Bit, 80/100 MSPS ADC AD9446 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

FEATURES

100 MSPS guaranteed sampling rate (AD9446-100)

83.6 dBFS SNR with 30 MHz input (3.8 V p-p input, 80 MSPS) 82.6 dBFS SNR with 30 MHz input (3.2 V p-p input, 80 MSPS) 89 dBc SFDR with 30 MHz input (3.2 V p-p input, 80 MSPS) 95 dBFS 2-tone SFDR with 9.8 MHz and 10.8 MHz (100 MSPS) 60 fsec rms jitter Excellent linearity DNL = ±0.4 LSB typical INL = ±3.0 LSB typical 2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output clock available

3.3 V and 5 V supply operation

APPLICATIONS

Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Communications instrumentation GENERAL DESCRIPTION The AD9446 is a 16-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use. The product operates up to a 100 MSPS, providing superior SNR for instrumentation, medical imaging, and radar receivers employing baseband (<100 MHz) IF frequencies. The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances. FUNCTIONAL BLOCK DIAGRAM CMOS OR LVDS OUTPUT STAGING CLOCK AND TIMING MANAGEMENT AGND DRGND DRVDD VREF CLK+ VIN+ AD9446 VIN– CLK– DCO 05490-001 AVDD1 AVDD2 DCS MODE DFS OUTPUT MODE T/H BUFFER 16PIPELINE ADC OR D15 TO D0 REF REFBSENSE REFT Figure 1. Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data mode. The AD9446 is available in a Pb-free, 100-lead, surface-mount, plastic package (100-lead TQFP/EP) specified over the industrial temperature range −40°C to +85°C. PRODUCT HIGHLIGHTS 1. True 16-bit linearity. 2. High performance: outstanding SNR performance for baseband IFs in data acquisition, instrumentation, magnetic resonance imaging, and radar receivers. 3. Ease of use: on-chip reference and high input impedance track-and-hold with adjustable analog input range and an output clock simplifies data capture. 4. Packaged in a Pb-free, 100-lead TQFP/EP package. 5. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of clock pulse widths. 6. OR (out-of-range) outputs indicate when the signal is beyond the selected input range.

Rev. 0 | Page 2 of 36 TABLE OF CONTENTS

REVISION HISTORY

10/05—Revision 0: Initial Version

Rev. 0 | Page 3 of 36 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , LVDS mode, specified minimum sampling rate, 3.2 V p-p differential input, internal trimmed reference (1.6 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted. Table 1. AD9446BSVZ-80 AD9446BSVZ-100 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION Full 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −5 ±0.1 +5 −5 ±0.1 +5 mV Gain Error Full −3 ±0.6 +3 −3 ±0.5 +3 % FSR Integral Nonlinearity (INL)1 25°C −5 ±3.0 +5 −6 ±3.0 +6 LSB VOLTAGE REFERENCE Output Voltage1 VREF = 1.6 V (3.2 V p-p Analog Input Range) Full 1.6 1.6 V Load Regulation @ 1.0 mA Full ±2 ±2 mV Reference Input Current (External 1.6 V Reference) Full μA INPUT REFERRED NOISE 25°C 1.5 1.9 LSB rms ANALOG INPUT Input Span VREF = 1.6 V Full 3.2 3.2 V p-p VREF = 1.0 V (External) Full 2.0 2.0 V p-p Internal Input Common-Mode Voltage Full 3.5 3.5 V External Input Common-Mode Voltage Full 3.2 3.8 3.2 3.8 V Input Resistance2 Full 1 1 kΩ Input Capacitance2 Full 6 6 pF POWER SUPPLIES Supply Voltage Supply Current IAVDD1 Full 335 365 368 401 mA IAVDD21 Full 204 234 223 255 mA IDRVDD1—LVDS Outputs Full 68 75 69 75 mA IDRVDD1—CMOS Outputs Full 14 14 mA PSRR Offset Full 1 1 mV/V Gain Full 0.2 0.2 %/V POWER CONSUMPTION LVDS Outputs Full 2.4 2.6 2.6 2.8 W CMOS Outputs (DC Input) Full 2.2 2.3 W 1 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. 2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.

Rev. 0 | Page 4 of 36 AC SPECIFICATIONS AVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , LVDS mode, specified minimum sample rate, 3.2 V p-p differential input, internal trimmed reference (1.6 V mode), AIN = −1 dBFS, DCS on, unless otherwise noted. Table 2. AD9446BSVZ-80 AD9446BSVZ-100 Parameter Temp Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 10 MHz 25°C 79.6 81.8 78.4 79.7 dB fIN = 30 MHz 25°C 80.5 81.6 78.3 79.5 dB Full 79.2 77.9 dB fIN = 70 MHz 25°C 79.0 80.6 77.7 79.0 dB Full 78.2 77.6 dB fIN = 92 MHz 25°C 80.1 78.9 dB fIN = 125 MHz 25°C 78.8 78.2 dB fIN = 170 MHz 25°C 77.1 77.0 dB fIN = 10 MHz (2 V p-p Input) 25°C 78.3 76.6 dB fIN = 30 MHz (2 V p-p Input) 25°C 78.3 76.6 dB fIN = 70 MHz (2 V p-p Input) 25°C 77.6 76.2 dB fIN = 92 MHz (2 V p-p Input) 25°C 77.5 76 dB fIN = 125 MHz (2 V p-p Input) 25°C 76.7 75.6 dB fIN = 170 MHz (2 V p-p Input) 25°C 75.5 75.1 dB SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 10 MHz 25°C 77.1 80.5 76.9 78.9 dB fIN = 30 MHz 25°C 75.9 80.4 75.5 78.6 dB Full 74.9 71.7 dB fIN = 70 MHz 25°C 75.5 78.6 73.8 77.7 dB Full 74.4 69.1 dB fIN = 92 MHz 25°C 79.2 77.1 dB fIN = 125 MHz 25°C 74.9 76.9 dB fIN = 170 MHz 25°C 66.0 70.5 dB fIN = 10 MHz (2 V p-p Input) 25°C 77.9 76.2 dB fIN = 30 MHz (2 V p-p Input) 25°C 77.8 76.1 dB fIN = 70 MHz (2 V p-p Input) 25°C 77.1 75.9 dB fIN = 92 MHz (2 V p-p Input) 25°C 77.1 75.7 dB fIN = 125 MHz (2 V p-p Input) 25°C 75.7 75.3 dB fIN = 170 MHz (2 V p-p Input) 25°C 72.5 73.6 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 13.2 13.0 Bits fIN = 30 MHz 25°C 13.2 12.9 Bits fIN = 70 MHz 25°C 12.9 12.8 Bits fIN = 92 MHz 25°C 13.0 12.7 Bits fIN = 125 MHz 25°C 12.3 12.6 Bits fIN = 170 MHz 25°C 10.8 11.6 Bits

Rev. 0 | Page 5 of 36 AD9446BSVZ-80 AD9446BSVZ-100 Parameter Temp Min Typ Max Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR, Second or Third Harmonic) fIN = 10 MHz 25°C 82 90 82 92 dBc fIN = 30 MHz 25°C 82 89 82 89 dBc Full 80 79 dBc fIN = 70 MHz 25°C 80 87 81 89 dBc Full 79 77 dBc fIN = 92 MHz 25°C 84 84 dBc fIN = 125 MHz 25°C 80 83 dBc fIN = 170 MHz 25°C 66 74 dBc fIN = 10 MHz (2 V p-p Input) 25°C 92 94 dBc fIN = 30 MHz (2 V p-p Input) 25°C 93 92 dBc fIN = 70 MHz (2 V p-p Input) 25°C 92 92 dBc fIN = 92 MHz (2 V p-p Input) 25°C 90 89 dBc fIN = 125 MHz (2 V p-p Input) 25°C 85 87 dBc fIN = 170 MHz (2 V p-p Input) 25°C 77 82 dBc WORST SPUR EXCLUDING SECOND OR THIRD HARMONICS fIN = 10 MHz 25°C −98 −89 −96 −91 dBc fIN = 30 MHz 25°C −97 −89 −97 −89 dBc Full −89 −87 dBc fIN = 70 MHz 25°C −98 −90 −96 −90 dBc Full −89 −88 dBc fIN = 92 MHz 25°C −98 −95 dBc fIN = 125 MHz 25°C −96 −96 dBc fIN = 170 MHz 25°C −95 −92 dBc fIN = 10 MHz (2 V p-p Input) 25°C −97 −93 dBc fIN = 30 MHz (2 V p-p Input) 25°C −97 −96 dBc fIN = 70 MHz (2 V p-p Input) 25°C −94 −94 dBc fIN = 92 MHz (2 V p-p Input) 25°C −97 −99 dBc fIN = 125 MHz (2 V p-p Input) 25°C −97 −95 dBc fIN = 170 MHz (2 V p-p Input) 25°C −93 −95 dBc TWO-TONE SFDR fIN = 10.8 MHz @ −7 dBFS,

9.8 MHz @ −7 dBFS

25°C 96 95 dBFS fIN = 70.3 MHz @ −7 dBFS,

69.3 MHz @ −7 dBFS

25°C 92 92 dBFS ANALOG BANDWIDTH Full 325 540 MHz

Rev. 0 | Page 6 of 36 DIGITAL SPECIFICATIONS Table 3. AD9446BSVZ-80 AD9446BSVZ-100 Parameter Temp Min Typ Max Min Typ Max Unit CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Full 2.0 2.0 V Low Level Input Voltage Full 0.8 0.8 V High Level Input Current Full 200 200 μA Low Level Input Current Full −10 +10 −10 +10 μA Input Capacitance Full 2 2 pF DIGITAL OUTPUT BITS—CMOS MODE (D0 to D15, OTR)1 DRVDD = 3.3 V High Level Output Voltage Full 3.25 3.25 V Low Level Output Voltage Full 0.2 0.2 V DIGITAL OUTPUT BITS—LVDS MODE (D0 to D15, OTR) VOD Differential Output Voltage2 Full 247 545 247 545 mV VOS Output Offset Voltage Full 1.125 1.375 1.125 1.375 V CLOCK INPUTS (CLK+, CLK−) Differential Input Voltage Full 0.2 0.2 V Input Capacitance Full 2 2 pF 1 Output voltage levels measured with 5 pF load on each output. 2 LVDS RTERM = 100 Ω. SWITCHING SPECIFICATIONS AVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , unless otherwise noted. Table 4. AD9446BSVZ-80 AD9446BSVZ-100 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Maximum Conversion Rate Full 80 100 MSPS Minimum Conversion Rate Full 1 1 MSPS CLK Period Full 12.5 10 ns CLK Pulse Width High1 (tCLKH) Full 5.0 4.0 ns CLK Pulse Width Low1 (tCLKL) Full 5.0 4.0 ns DATA OUTPUT PARAMETERS Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+) Full 3.35 3.35 ns Pipeline Delay (Latency) Full 13 13 Cycles Aperture Delay (tA) Full ns Aperture Uncertainty (Jitter, tJ) Full 60 60 fsec rms 1 With duty cycle stabilizer (DCS) enabled. 2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load. 3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

13 CLOCK CYCLES

Figure 2. LVDS Mode Timing Diagram Figure 3. CMOS Timing Diagram

Rev. 0 | Page 8 of 36 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter With Respect to Rating ELECTRICAL AVDD1 AGND −0.3 V to +4 V AVDD2 AGND −0.3 V to +6 V DRVDD DGND −0.3 V to +4 V AGND DGND −0.3 V to +0.3 V AVDD1 DRVDD −4 V to +4 V AVDD2 DRVDD −4 V to +6 V AVDD2 AVDD1 −4 V to +6 V D0± to D15± DGND –0.3 V to DRVDD + 0.3 V CLK+/CLK− AGND –0.3 V to AVDD1 + 0.3 V OUTPUT MODE, DCS MODE, DFS AGND –0.3 V to AVDD1 + 0.3 V VIN+, VIN− AGND –0.3 V to AVDD2 + 0.3 V VREF AGND –0.3 V to AVDD1 + 0.3 V SENSE AGND –0.3 V to AVDD1 + 0.3 V REFT, REFB AGND –0.3 V to AVDD1 + 0.3 V ENVIRONMENTAL Storage Temperature Range –65°C to +125°C Operating Temperature Range –40°C to +85°C Lead Temperature (Soldering 10 sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The heat sink of the AD9446 package must be soldered to ground. Table 6. Package Type θJA θJB θJC Unit 100-lead TQFP/EP 19.8 8.3 2 °C/W Typical θJA = 19.8°C/W (heat sink soldered) for multilayer board in still air. Typical θJB = 8.3°C/W (heat sink soldered) for multilayer board in still air. Typical θJC = 2°C/W (junction to exposed heat sink) represents the thermal resistance through heat sink path. Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the θ JA. It is required that the exposed heat sink be soldered to the ground plane. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 9 of 36 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter, tJ) The sample-to-sample variation in aperture delay. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 16-bit resolution indicates that all 65,536 codes must be present over all operating ranges. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: 6.02 1.76−= SINADENOB Gain Error The first code transition should occur at an analog value of ½ LSB above negative full scale. The last transition should occur at an analog value of 1½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Maximum Conversion Rate The clock rate at which parametric testing is performed. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Offset Error The major carry transition should occur for an analog value of ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Output Propagation Delay (tPD) The delay between the clock rising edge and the time when all bits are within valid logic levels. Power-Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at the maximum limit. Signal-to-Noise and Distortion (SINAD) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may be a harmonic. SFDR can be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale). Temp er atu re D r i ft The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX. Total Harmonic Distortion (THD) The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.

74 D10+

73 D10–

72 D9+

69 D8–

70 D8+

71 D9–

75 DRGND

68 DCO+

67 DCO–

66 D7+

64 DRVDD

63 DRGND

62 D6+

61 D6–

60 D5+

59 D5–

58 D4+

57 D4–

56 D3+

55 D3–

54 D2+

53 D2–

52 D1+

51 D1–

65 D7–

Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode

Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode DCS (recommended); DCS = high (AVDD1) to disable DCS. 2 DNC Do Not Connect. These pins should float.

3 OUTPUT

OUTPUT MODE = 1 (AVDD1) for LVDS outputs. high (AVDD1) for twos complement; DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND. AVDD1 3.3 V (±5%) Analog Supply. input range); connect to AVDD1 for external reference. 8 VREF 1.6 V Reference I/O. Function dependent on SENSE and external programming resistors. Decouple to ground with 0.1 μF and 10 μF capacitors. with 0.1 μF and 10 μF capacitors. (Pin 10) with 0.1 μF and 10 μF capacitors. 23 VIN− Analog Input—Complement. 41 CLK− Clock Input—Complement. 47, 63, 75, 87, DRGND Digital Output Ground. 49 D0− (LSB) D0 Complement Output Bit (LVDS Levels). 51 D1− D1 Complement Output Bit. 53 D2− D2 Complement Output Bit. 55 D3− D3 Complement Output Bit. 57 D4− D4 Complement Output Bit. 59 D5− D5 Complement Output Bit. 61 D6− D6 Complement Output Bit. 65 D7− D7 Complement Output Bit. 67 DCO− Data Clock Output—Complement. 68 DCO+ Data Clock Output—True. 69 D8− D8 Complement Output Bit. 71 D9− D9 Complement Output Bit. 73 D10− D10 Complement Output Bit. 74 D10+ D10 True Output Bit. 77 D11− D11 Complement Output Bit. 78 D11+ D11 True Output Bit.

Rev. 0 | Page 12 of 36 Pin No. Mnemonic Description 79 D12− D12 Complement Output Bit. 80 D12+ D12 True Output Bit.

81 D13− D13 Complement Output Bit

82 D13+ D13 True Output Bit.

83 D14− D14 Complement Output Bit

84 D14+ D14 True Output Bit. 85 D15− D15 Complement Output Bit. 86 D15+ (MSB) D15 True Output Bit. 89 OR− Out-of-Range Complement Output Bit. 90 OR+ Out-of-Range True Output Bit.

74 D4+

73 D3+

72 D2+

69 DNC

70 D0+ (LSB)

71 D1+

66 DNC

62 DNC

61 DNC

60 DNC

59 DNC

58 DNC

57 DNC

56 DNC

55 DNC

54 DNC

53 DNC

52 DNC

51 DNC

65 DNC

Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode

Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode enable DCS (recommended); DCS = high (AVDD1) to disable DCS. 2, 49 to 62, 65 to 66, 69, DNC Do Not Connect. These pins should float. OUTPUT MODE = 1 (AVDD1) for LVDS outputs. 4 DFS Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format. 5 LVDS_BIAS Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND. AVDD1 3.3 V (±5%) Analog Supply. 8 VREF 1.6 V Reference I/O. Function dependent on SENSE and external programming resistors. Decouple to ground with 0.1 μF and 10 μF capacitors. with 0.1 μF and 10 μF capacitors. with 0.1 μF and 10 μF capacitors. 23 VIN− Analog Input—Complement. 41 CLK− Clock Input—Complement. 47, 63, 75, 87, DRGND Digital Output Ground. 67 DCO− Data Clock Output—Complement. 68 DCO+ Data Clock Output—True. 70 D0+ (LSB) D0 True Output Bit (CMOS levels). 82 D10+ D10 True Output Bit. 83 D11+ D11 True Output Bit. 84 D12+ D12 True Output Bit. 85 D13+ D13 True Output Bit. 86 D14+ D14 True Output Bit. 89 D15+ (MSB) D15 True Output Bit. 90 OR+ Out-of-Range True Output Bit.

Figure 24. AD9446-100 SNR/SFDR vs. Analog Input Frequency, 100 MSPS, 3.2 V p-p Figure 25. AD9446-100 SNR/SFDR vs. Analog Input Frequency, 100 MSPS,

3.2 V p-p, CMOS Output Mode

Figure 26. AD9446-100 SNR/SFDR vs. Analog Input Level, 100 MSPS Figure 27. AD9446-100 SNR/SFDR vs. Analog Input Frequency, 100 MSPS, 2.0 V p-p Figure 28. AD9446-100 SNR vs. Input Range, 30.3 MHz, −30 dBFS Figure 29. AD9446-100 SNR/SFDR vs. Analog Input Level, 100 MSPS,

Figure 42. AD9446-100 Grounded Input Histogram Figure 43. AD9446-80 64k Point Two-Tone FFT/80 MSPS/69.3 MHz, 70.3 MHz Figure 44. AD9446-80 Two-Tone SFDR vs. Analog Input Level 80 MSPS/ Figure 45. AD9446-80 Grounded Input Histogram Figure 46. AD9446-100 Gain vs. Temperature Figure 47. AD9446-80 Power Supply Current vs. Sample Rate

10.3 MHz @ −1 dBFS

Figure 48. AD9446-100/SFDR vs. Analog Input Range,

100 MSPS

Figure 49. AD9446-100 VREF vs. Temperature Figure 50. AD9446-100 Power Supply Current vs. Sample Rate Figure 51. AD9446-100 SNR vs. Analog Input Range, Figure 52. AD9446-80 SFDR vs. Analog Input Range, Figure 53. AD9446-80/SNR vs. Analog Input Range,

80 MSPS

Figure 54. AD9446 Single-Tone SNR/SFDR vs. Sample Rate 2.3 MHz

3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT

internal reference or an externally applied reference voltage. analog-to-digital conversion core and establish its input span. the reference pin for either an internal or an external reference. Figure 55. Internal Reference Configuration Figure 56. Programmable Reference Configuration

Table 9. Reference Configuration Summary

0.2 V to VREF

maximum of 2.0 V . See Figure 46 for gain variation vs. even-order harmonics. There are also benefits at the PCB level. ended analog input configurations. Figure 57. Differential Analog Input Range for VREF = 1.6 V

Rev. 0 | Page 27 of 36 POWER CONSIDERATIONS Care should be taken when selecting a power source. The use of linear dc supplies is highly recommended. Switching supplies tend to have radiated components that may be received by the AD9446. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 μF chip capacitors. The AD9446 has separate digital and analog power supply pins. The analog supplies are denoted AVDD1 (3.3 V) and AVDD2 (5 V), and the digital supply pins are denoted DRVDD. Although the AVDD1 and DRVDD supplies can be tied together, best per- formance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that both AVDD1 and AVDD2 must be held within 5% of the specified voltage. The DRVDD supply of the AD9446 is a dedicated supply for the digital outputs in either LVDS or CMOS output mode. When in LVDS mode, the DRVDD should be set to 3.3 V . In CMOS mode, the DRVDD supply can be connected from 2.5 V to 3.6 V for compatibility with the receiving logic. DIGITAL OUTPUTS LVDS Mode The off-chip drivers on the chip can be configured to provide LVDS-compatible output levels via Pin 3 (OUTPUT MODE). LVDS outputs are available when OUTPUT MODE is CMOS logic high (or AVDD1 for convenience) and a 3.74 kΩ R SET resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic performance, including both SFDR and SNR, is maximized when the AD9446 is used in LVDS mode; designers are encouraged to take advantage of this mode. The AD9446 outputs include complimentary LVDS outputs for each data bit (Dx+/Dx−), the overrange output (OR+/OR−), and the output data clock output (DCO+/DCO−). The RSET resistor current is multiplied on-chip, setting the output current at each output equal to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended, with a 100 Ω termination resistor located as close to the receiver as possible. It is recommended to keep the trace length less than 2 inches and to keep differential output trace lengths as equal as possible. CMOS Mode In applications that can tolerate a slight degradation in dynamic performance, the AD9446 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. CMOS outputs are available when OUTPUT MODE is CMOS logic low (or AGND for convenience). In this mode, the output data bits, Dx, are single-ended CMOS, as is the overrange output, OR+. The output clock is provided as a differential CMOS signal, DCO+/DCO−. Lower supply voltages are recommended to avoid coupling switching transients back to the sensitive analog sections of the ADC. The capacitive load to the CMOS outputs should be minimized, and each output should be connected to a single gate through a series resistor (220 Ω) to minimize switching transients caused by the capacitive loading. TIMING The AD9446 provides latched data outputs with a pipeline delay of 13 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and Figure 3 for detailed timing diagrams.

Table 10 summarizes the output coding. the pin assignment for the device is as defined in Table 7. high (AVDD1, 3.3 V) disables the controller. Table 10. Digital Output Coding

Figure 61. AD9446 Evaluation Board Schematic

Figure 62. AD9446 Evaluation Board Schematic (Continued)

Figure 63. AD9446 Evaluation Board Schematic (Continued)

Figure 64. AD9446 Evaluation Board Schematic (Continued)

Table 11. AD9446 Customer Evaluation Board Bill of Material Designator Description Package Value Manufacturer Mfg. Part No.

Rev. 0 | Page 35 of 36 Item Qty. Reference Designator Description Package Value Manufacturer Mfg. Part No.

30 E151 Header EHOLE Mouser Electronics 517-6111TG

31 J51 SMA SMA Digi-Key Corporation ARFX1231-ND

32 P61 Header C40MS Samtec, Inc. TSW-120-08-L-D- RA 33 2 R1, R21 BRES402 402 XX 34 3 R5, R7, R91 BRES402 402 XX 35 1 U21 ECLOSC DIP4(14) 36 4 H1, H2, H3, H41 MTHOLE6 MTHOLE6 37 2 T1, T21 Balun transformer SM-22 M/A-COM ETC1-1-13 38 2 P21, P221 Term strip PTMICRO4 Newark Electronics 1 Parts not populated.

14.00 BSC SQ

16.00 BSC SQ

0.50 BSC

0.08 MAX

9.50 SQEXPOSED

1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. Figure 65. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] registered trademarks are the property of their respective owners.