AD9444

AD9444 14-Bit, 80 MSPS, A/D Converter Data Sheet (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 40

Technical content

14-Bit, 80 MSPS, A/D Converter AD9444 Rev. 0 Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

80 MSPS guaranteed sampling rate

100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz 73.1 dB SNR with 70 MHz input 97 dBc SFDR with 70 MHz input Excellent linearity DNL = ±0.4 LSB typical INL = ±0.6 LSB typical

1.2 W power dissipation

3.3 V and 5 V supply operation

2.0 V p-p differential full-scale input

LVDS outputs (ANSI-644 compatible) Data format select Output clock available

APPLICATIONS

Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar, infared imaging Communications instrumentation GENERAL DESCRIPTION The AD9444 is a 14-bit monolithic, sampling analog-to-digital converter (ADC) with an on-chip, track-and-hold circuit and is optimized for power, small size, and ease of use. The product operates at up to an 80 MSPS conversion rate and is optimized for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment. The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS-compatible (ANSI- 644) or CMOS-compatible and include the means to reduce the overall current needed for short trace distances. FUNCTIONAL BLOCK DIAGRAM CMOS OR LVDS OUTPUT STAGING CLOCK AND TIMING MANAGEMENT AGND DRGND DRVDD VREF CLK+ VIN+ AD9444 VIN– CLK– DCO 05089-001 AVDD1 AVDD2 DCS MODE DFS OUTPUT MODE T/H BUFFER 14PIPELINE ADC OR D13–D0 REF REFBSENSE REFT Figure 1. Optional features allow users to implement various selectable operating conditions, including data format select and output data mode. The AD9444 is available in a 100-lead surface-mount plastic package (100-lead TQFP/EP) specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. High performance: Outstanding SFDR performance for mul- ticarrier, multimode 3G and 4G cellular base station receivers. 2. Ease of use: On-chip reference and track-and-hold. An output clock simplifies data capture. 3. Packaged in a Pb-free, 100-lead TQFP/EP. 4. Clock DCS maintains overall ADC performance over a wide range of clock pulse widths. 5. OR (out-of-range) outputs indicate when the signal is beyond the selected input range.

Rev. 0 | Page 2 of 40 TABLE OF CONTENTS

REVISION HISTORY

10/04—Revision 0: Initial Version

Rev. 0 | Page 3 of 40 DC SPECIFICATIONS AVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted. Table 1. AD9444BSVZ-80 Parameter Temp Test Level Min Typ Max Unit RESOLUTION Full VI 14 Bits ACCURACY No Missing Codes Full VI Guaranteed Offset Error Full VI 6 ±0.3 6 mV Gain Error1 Full VI −3.0 ±0.4 +3.0 % FSR Differential Nonlinearity (DNL)2 Full VI −0.8 ±0.4 +0.8 LSB Integral Nonlinearity (INL)2 25°C I −1.3 ±0.6 +1.3 LSB Full VI −1.7 +1.7 LSB TEMPERATURE DRIFT Offset Error Full V 12 µV/°C Gain Error Full V 0.002 %FS/°C VOLTAGE REFERENCE Output Voltage1 Full VI 0.87 1.0 1.13 V Load Regulation @ 1.0 mA Full V ±2 mV Reference Input Current (External 1.0 V Reference) Full VI 80 125 µA INPUT REFERRED NOISE 25°C V 1.0 LSB rms ANALOG INPUT Input Span Full V 2 V p-p Input Common-Mode Voltage Full V 3.5 V Input Resistance3 Full V 1 kΩ Input Capacitance3 Full V 2.5 pF POWER SUPPLIES Supply Voltage AVDD1 Full IV 3.14 3.3 3.46 V AVDD2 Full IV 4.75 5.0 5.25 V DRVDD—LVDS Outputs Full IV 3.0 3.6 V DRVDD—CMOS Outputs Full IV 3.0 3.3 3.6 V Supply Current AVDD1 Full VI 217 240 mA AVDD22 Full VI 71 80 mA IDRVDD2—LVDS Outputs Full VI 55 62 mA IDRVDD2—CMOS Outputs Full V 12 mA PSRR Offset Full V 1 mV/V Gain Full V 0.2 %/V POWER CONSUMPTION DC Input—LVDS Outputs Full VI 1.21 1.4 W DC Input—CMOS Outputs Full V 1.07 W Sine Wave Input2—LVDS Outputs Full VI 1.25 W Sine Wave Input2—CMOS Outputs Full V 1.11 W 1 The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444. 2 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. 3 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to for the equivalent analog input structure. Figure 6

Rev. 0 | Page 4 of 40 AC SPECIFICATIONS AVDD1 = 3.3 V , AVDD2 = 5.0 V , DRVDD = 3.3 V , LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted. Table 2. AD9444BSVZ-80 Parameter Temp Test Level Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR) fIN = 10 MHz 25°C IV 73.0 74.0 dB Full IV 72.7 dB fIN = 35 MHz 25°C I 72.4 73.7 dB Full IV 72.3 dB fIN = 70 MHz 25°C IV 72.3 73.1 dB Full IV 72.0 dB fIN = 100 MHz 25°C V 72.3 dB SIGNAL-TO-NOISE-AND DISTORTION (SINAD) fIN = 10 MHz 25°C IV 73.0 74.0 dB Full IV 72.7 dB fIN = 35 MHz 25°C I 72.4 73.7 dB Full IV 72.2 dB fIN = 70 MHz 25°C IV 72.2 73.1 dB Full IV 72.0 dB fIN = 100 MHz 25°C V 72.3 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C V 12.1 Bits fIN = 35 MHz 25°C V 12.0 Bits fIN = 70 MHz 25°C V 11.9 Bits fIN = 100 MHz 25°C V 11.8 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 10 MHz 25°C IV 91 97 dBc Full IV 87 dBc fIN = 35 MHz 25°C I 91 97 dBc Full IV 87 dBc fIN = 70 MHz 25°C IV 90 97 dBc Full IV 87 dBc fIN = 100 MHz 25°C V 96 dBc WORST HARMONIC, SECOND OR THIRD fIN = 10 MHz 25°C IV −97 −91 dBc Full IV −87 dBc fIN = 35 MHz 25°C I −97 −91 dBc Full IV −87 dBc fIN = 70 MHz 25°C IV −97 −90 dBc Full IV −87 dBc fIN = 100 MHz 25°C V −96 dBc WORST SPUR EXCLUDING SECOND OR HARMONICS fIN = 10 MHz 25°C IV −102 −93 dBc Full IV −93 dBc fIN = 35 MHz 25°C I −103 −93 dBc Full IV −93 dBc fIN = 70 MHz 25°C IV −102 −93 dBc Full IV −93 dBc fIN = 100 MHz 25°C V −99 dBc TWO-TONE SFDR fIN = 10.8 MHz @ −7 dBFS, 9.8 MHz @ −7 dBFS 25°C V −102 dBFS fIN = 70.3 MHz @ −7 dBFS, 69.3 MHz @ −7 dBFS 25°C V −100 dBFS ANALOG BANDWIDTH Full V 650 MHz

Rev. 0 | Page 5 of 40 DIGITAL SPECIFICATIONS Table 3. AD9444BSVZ-80 Parameter Temp Test Level Min Typ Max Unit CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Full IV 2.0 V Low Level Input Voltage Full IV 0.8 V High Level Input Current Full VI +200 µA Low Level Input Current Full VI −10 +10 µA Input Capacitance Full V 2 pF DIGITAL OUTPUT BITS—CMOS Mode (D0 to D13, OTR)1 DRVDD = 3.3 V High Level Output Voltage Full IV 3.25 V Low Level Output Voltage Full IV 0.2 V DIGITAL OUTPUT BITS LVDS Mode (D0 to D13, OTR) VOD Differential Output Voltage2 Full VI 247 545 mV VOS Output Offset Voltage Full VI 1.125 1.375 V CLOCK INPUTS (CLK+, CLK−) Differential Input Voltage Full IV 0.2 V Common-Mode Voltage Full VI 1.3 1.5 1.6 V Differential Input Resistance Full V 8 10 12 kΩ Differential Input Capacitance Full V 4 pF 1 Output voltage levels measured with 5 pF load on each output. 2 LVDS RTERM = 100 Ω.

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted. 1 With duty cycle stabilizer (DCS) enabled. 2 Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load. 3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

12 CLOCK CYCLES

Figure 2. LVDS Mode Timing Diagram

12 CYCLES

Figure 3. CMOS Timing Diagram II 100% production tested at 25°C and sample tested at specified temperatures. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

Rev. 0 | Page 8 of 40 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter With Respect to Min Max Unit ELECTRICAL AVDD1 AGND −0.3 +4 V AVDD2 AGND −0.3 +6 V DRVDD DGND −0.3 +4 V AGND DGND −0.3 +0.3 V AVDD1 DRVDD −4 +4 V AVDD2 DRVDD −4 +6 V AVDD2 AVDD1 −4 +6 V D0 to D13 DGND –0.3 DRVDD + 0.3 V CLK, MODE AGND –0.3 AVDD1 + 0.3 V VIN+, VIN− AGND –0.3 AVDD2 + 0.3 V VREF AGND –0.3 AVDD1 + 0.3 V SENSE AGND –0.3 AVDD1 + 0.3 V REFT, REFB AGND –0.3 AVDD1 + 0.3 V ENVIRONMENTAL Storage Temperature –65 +125 °C Operating Temperature Range –40 +85 °C Lead Temperature Range (Soldering 10 sec) 300 °C Junction Temperature 150 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Resistance The heat sink of the AD9444 package must be soldered to ground. Table 6. Package Type θJA θJB θJC Unit 100-Lead TQFP/EP 19.8 8.3 2 °C/W Typical θJA = 19.8°C/W (heat-sink soldered) for multilayer board in still air. Typical θJB = 8.3°C/W (heat-sink soldered) for multilayer board in still air. Typical θJC = 2°C/W (junction to exposed heat sink) represents the thermal resistance through heat-sink path. Airflow increases heat dissipation effectively reducing θJA. Also, more metal directly in contact with the package leads, from metal traces, through holes, ground, and power planes, reduces the θJA. It is required that the exposed heat sink be soldered to the ground plane. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprie- tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 9 of 40 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter, tJ) The sample-to-sample variation in aperture delay. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes must be present over all operating ranges. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula 6.02 1.76−= SINADENOB Gain Error The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value 1 ½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1 ½ LSBs beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Maximum Conversion Rate The clock rate at which parametric testing is performed. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Offset Error The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Output Propagation Delay (tPD) The delay between the clock rising edge and the time when all bits are within valid logic levels. Power-Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Signal-to-Noise and Distortion (SINAD) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo- nent may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full scale). Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX. Total Harmonic Distortion (THD) The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.

80 D13–

79 D12+

78 D12–

77 D11+

76 D11–

75 DRVDD

74 DRGND

73 D10+

72 D10–

71 D9+

70 D9–

69 D8+

68 D8–

67 DRGND

66 D7+

65 D7–

64 DCO+

63 DCO–

62 DRVDD

61 DRGND

60 D6+

59 D6–

58 D5+

57 D5–

56 D4+

Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode

Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode AVDD1 3.3 V (±5%) Analog Supply.

5 OUTPUT

7 LVDSBIAS Set Pin for LVDS Output Current. 10 SENSE Reference Mode Selection. 13 REFT Differential Reference Output. 0.1 µF and 10 µF capacitors. 14 REFB Differential Reference Output. 0.1 µF and 10 µF capacitors. AVDD2 5.0 V Analog Supply (±5%). 22 VIN− Analog Input—Complement. 37 CLK− Clock Input—Complement.

43 D0− (LSB) D0 Complement Output Bit

45 D1− D1 Complement Output Bit. 49 D2− D2 Complement Output Bit. 51 D3− D3 Complement Output Bit. 55 D4− D4 Complement Output Bit. 57 D5− D5 Complement Output Bit. 59 D6− D6 Complement Output Bit. 63 DCO− Data Clock Output—Complement. 64 DCO+ Data Clock Output—True. 65 D7− D7 Complement Output Bit. 68 D8− D8 Complement Output Bit. 70 D9− D9 Complement Output Bit. 72 D10− D10 Complement Output Bit. 73 D10+ D10 True Output Bit. 76 D11− D11 Complement Output Bit. 77 D11+ D11 True Output Bit. 78 D12− D12 Complement Output Bit. 79 D12+ D12 True Output Bit. 80 D13− D13 Complement Output. 81 D13+ (MSB) D13 True Output Bit.

84 OR− Out-of-Range Complement

85 OR+ Out-of-Range True Output Bit.

100 DCS MODE Clock Duty Cycle Stabilizer (DCS)

Control Pin, CMOS-Compatible.

66 D0 (LSB)

65 DNC

60 DNC

59 DNC

58 DNC

57 DNC

56 DNC

Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode

Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode AVDD1 3.3 V (±5%) Analog Supply. 6 DFS Data Format Select Pin. 10 SENSE Reference Mode Selection.

1 V reference, and connect to

AVDD2 for external reference.

13 REFT Differential Reference Out-

14 REFB Differential Reference Out-

AVDD2 5.0 V Analog Supply (±5%). 22 VIN− Analog Input—Complement. 37 CLK− Clock Input—Complement.

63 DCO− Data Clock Output—

64 DCO+ Data Clock Output—

66 D0 (LSB) D0 Output Bit (LSB)

84 D13 (MSB) D13 Output Bit.

100 DCS MODE Clock Duty Cycle Stabilizer

high (AVDD1) to disable DCS.

Figure 30. 64K FFT, 61.44 MSPS, 4 @ WCDMA, IF = 46.08 MHz Figure 31. NPR, 80 MSPS/18 MHz Notch Figure 32. Single-Tone SNR/SFDR vs. Clock Duty Cycle, Figure 33. Ground Input Histogram

80 MSPS, VIN+ = VIN−, 32K Samples

Figure 34. ISUPPLY vs. Sample Rate, AIN = 10.3 MHz @ −0.5 dBFS Figure 35. Single-Tone SNR/SFDR vs.

Table 10. Digital Output Coding grounding techniques that should be applied at the system level. necessary to achieve the specified noise performance. (see Figure 47 to Figure 50 and Figure 59 to Figure 61). model of the AD9444 and many other high speed ADCs. without hardware evaluation boards. data and the DCO output clock of the AD9444.

Figure 47. LVDS Mode Evaluation Board Schematic

Figure 50. LVDS Mode Evaluation Board Schematic (Continued)

Rev. 0 | Page 30 of 40 LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) Table 11. Item Qty. REFDES Description Manufacturer MFG_PART_NO 1 1 AD9444PCB PCB, AD9444 LVDS Engineering Evaluation Board PCSM AD9444LVDSCUSTREVC 2 16 C1, C4, C6, C33, C34, C39, C44, C55 to C57, C64, C65, C76, C87 to C89 Capacitors, Tantalum, SMT BCAPTAJC, 10 µF, 16 V, 10% KEMET T491C106K016AS 3 38 C2, C3, C5, C9, C12, C20 to C24, C26 to C28, C30, C32, C35, C40, C42, C43, C46 to C48, C50, C52, C53, C58, C60, C61, C75, C80 to C82, C85, C86, C91 to C93, C97 Capacitors, 0.1 µF 10 V Ceramic X5R 0402 Panasonic ECJ-0EB1A104K 4 1 C51 Capacitor, Ceramic 10 µF 6.3 V X5R 0805 KEMET C0805C106K9PACTU 5 1 CR2 Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA Panasonic MA716-(TX) 6 17 E1 to E3, E24, to E27, E32, E34, E38, E39, E40, E41, E43, E46, E47, E52 40-Pin Breakable Header 3M 2340-611TN 7 2 J1, J4 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201 8 1 L1 10 nH Inductor Coilcraft 0603CJ-10NXGBU 9 1 P3 Header, 40-Pin, Male, 40-Pin Right Angle Samtec TSW-120-08-T-D-RA 10 1 P4 Power Jack Swithcraft RAPC722 11 1 R3 Resistor, 3.6 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2GEJ362X 12 2 R4, R6 Resistor, 36 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ360X 13 1 R8 Resistor, 49.9 Ω 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF49R9X 14 4 R9, R12, R14, R15 Resistor, 1.00 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF1001X 15 2 R28, R35 Resistor, 33 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ330X 16 3 R39, R52, R53 Resistor, 0 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GE0R00X 17 2 RZ4, RZ5 22 Ω Resistor Array, 16 Term CTS Corp. 742163220JTR 18 2 T3, T5 Transformer, ADT1-1WT, CD542, ADT1-1WT Mini-Circuits ADT1-1WT 19 1 U1 14-Bit, 80 MSPS ADC ADI AD9444BSVZ-80 20 3 U3, U4, U15 3.3 V Voltage Regulator ADI ADP3338-3.3 V 21 1 U14 5 V Voltage Regulator ADI ADP3338-5.0 V 22 1 U6 Clock Oscillator, 80 MHz CTS Reeves MX045-80 23 1 U7 LVDS-to-CMOS Translator with 100 Term Texas Instruments SN75LVDT386DGG 24 1 U10 2 Input XOR Gate Fairchild 74VCX86M 25 4 U6 Pin Sockets, Closed End AMP 5-330808-3

Rev. 0 | Page 31 of 40 Item Qty. REFDES Description Manufacturer MFG_PART_NO 26 24 C10, C11, C13, to C19, C29, C31, C36 to C38, C45, C49, C59, C62, C69, C70 to C73, C90 Capacitors, Select 10 V Ceramic X5R 0402 Panasonic 27 1 J51 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201 28 2 P5, P61 Power Connectors Weiland 29 1 R1, R2, R5, R7, R13 Resistors, Select 1/16 W 1% 0402 SMD Panasonic 30 1 R17 to R20, R27, R36 to R38, R401 Resistors, Select 1/16 W 1% 0402 SMD Panasonic 31 5 U21 XO Select Vectron 1 Parts not placed.

Figure 59. CMOS Mode Evaluation Board Schematic

Figure 60. CMOS Mode Evaluation Board Schematic (Continued)

Figure 61. CMOS Mode Evaluation Board Schematic (Continued)

Rev. 0 | Page 37 of 40 CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) Table 12. Item Qty. REFDES Description Manufacturer MFG_PART_NO 1 1 AD9444PCB PCB, AD9444 LVDS Evaluation Board PCSM AD9444LVDSCUSTREVC 2 16 C1, C4, C6, C33, C34, C39, C44, C55 to C57, C64 to C66, C87 to C89 Capacitors, Tantalum, SMT BCAPTAJC, 10 µF, 16 V, 10% KEMET T491C106K016AS 3 32 C2, C3, C5, C9, C12, C20 to C23, C26 to C28, C30, C32, C35, C40, C42, C43, C46 to C48, C50, C52, C53, C58, C60, C61, C75, C78, C85, C91, C92 Capacitors, 0.1 µF 10 V Ceramic X5R 0402 Panasonic ECJ-0EB1A104K 4 5 C24, C25, C41, C67, C68 Capacitors, 0.1 µF 16 V Ceramic X7R 0603 Panasonic ECJ-1VB1C104K 5 1 C51 Capacitor, Ceramic 10 µF 6.3 V X5R 0805 KEMET C0805C106K9PACTU 6 1 CR2 Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA Panasonic MA716-(TX) 7 20 E1 to E3, E24 to E27, E30 to E32, E38 to E42, E45 to E47, E49, E52 40-Pin Breakable Header 3M 2340-611TN 8 2 J1, J4 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201 9 1 L1 10 nH O402 Inductor Coilcraft 0402CS-10NX_B_ 10 1 P3 Header, 40-Pin, Male, 40-Pin Right Angle Samtec TSW-120-08-T-D-RA 11 1 P4 Power Jack Swithcraft RAPC722 12 1 R3 Resistor, 3.6 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2GEJ362X 13 2 R4, R6 Resistors, 36 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ360X 14 1 R8 Resistor, 49.9 Ω 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF49R9X 15 4 R9, R12, R15, R21 Resistors, 1.00 kΩ 1/16 W 1% 0402 SMD Panasonic ERJ-2RKF1001X 16 2 R14, R50 Resistors, 0 Ω 1/10 W 5% 0603 SMD Panasonic ERJ-3GEY0R00V 17 2 R28, R35 Resistors, 33 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GEJ330X 18 1 R39 Resistor, 0 Ω 1/16 W 5% 0402 SMD Panasonic ERJ-2GE0R00X 19 4 RZ1 to RZ3, RZ6 220 Ω Resistor Array, 16 Term CTS Corp. 742163221JTR 20 2 T3, T5 Transformer, ADT1-1WT, CD542, ADT1-1WT Mini-Circuits ADT1-1WT 21 1 U1 14-Bit, 80 MSPS ADC ADI AD9444BSVZ-80 22 4 U3, U8, U15 3.3 V Voltage Regulator ADI ADP3338-3.3 V 23 1 U14 5 V Voltage Regulator ADI ADP3338-5.0 V 24 1 U5 16-Bit Flip Flop Fairchild 74LVTH162374 25 4 U6 Pin Sockets, Closed End AMP 5-330808-3

Rev. 0 | Page 38 of 40 Item Qty. REFDES Description Manufacturer MFG_PART_NO 26 26 C10, C11, C13, C14 to C19, C29, C31, C36 to C37, C38, C45, C49, C59, C62,C69, C70 to C73, C90, C93, C961 Capacitors, Select 10 V Ceramic X5R 0402 Panasonic 27 1 J51 Connector, Gold, Male, Coaxial, SMA, Vertical Johnston Comp. 142-0701-201 28 15 R1,R2,R5,R7, R13, R17 to R20, R27, R36 to R401 Resistors, Select 1/16 W 1% 0402 SMD Panasonic 29 3 R16, R41, R421 Resistors, Select 1/16 W 5% 0603 SMD Panasonic 30 1 C631 Capacitor, Select 10 V Ceramic X5R 0603 Panasonic 31 1 U41 XOR 74VCX86D Fairchild 74VCX86D 32 2 P5, P61 Power Connectors Weiland 1 Parts not placed.

1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

1. THE EXPOSED HEAT SINK SOLDERED TO THE GROUND PLANE IS REQUIRED FOR THE 100-LEAD TQFP/EP.

0.50 BSC

Figure 70. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

Rev. 0 | Page 40 of 40 NOTES © 2004 Analo g De vices, Inc. All rights reserve d. Tra demarks and registered tra demarks are the prop erty of their respective owners . D05089–0–10/04(0)