DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 28
Technical content
12-Bit, 370 MSPS/500 MSPS,
1.8 V Analog-to-Digital Converter
Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
FEATURES
SNR = 65 dBFS at fIN up to 250 MHz at 500 MSPS ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS) SFDR = 78 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS) Integrated input buffer Excellent linearity DNL = ±0.5 LSB typical INL = ±0.6 LSB typical LVDS at 500 MSPS (ANSI-644 levels)
1 GHz full power analog bandwidth
On-chip reference, no external decoupling required Low power dissipation 690 mW at 500 MSPS—LVDS SDR mode 660 mW at 500 MSPS—LVDS DDR mode Programmable (nominal) input voltage range 1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data clock output with programmable clock and data alignment
APPLICATIONS
Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization GENERAL DESCRIPTION The AD9434 is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. The VREF pin can be used to monitor the internal reference or provide an external voltage reference (external reference mode must be enabled through the SPI port). The ADC requires a 1.8 V analog voltage supply and a differen- tial clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. FUNCTIONAL BLOCK DIAGRAM AGNDPWDNVREF AVDD VIN+ VIN– CML TRACK-AND-HOLD REFERENCE ADC CORE OUTPUT STAGING LVDS CLK+ CLK– CLOCK MANAGEMENT SERIAL PORT SCLK/DFS SDIO CSB DCO– DCO+ OR– OR+ D11± TO D0± DRGND DRVDD 12 12 AD9434 09383-001 Figure 1. Fabricated on an advanced BiCMOS process, the AD9434 is available in a 56-lead LFCSP , specified over the industrial temperature range (−40°C to +85°C). This part is protected under a U.S. patent. PRODUCT HIGHLIGHTS 1. High Performance. Maintains 65 dBFS SNR at 500 MSPS with a 250 MHz input. 2. Low Power. Consumes only 660 mW at 500 MSPS. 3. Ease of Use. LVDS output data and output clock signal allow interface to FPGA technology. The on-chip reference and sample- and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. 4. Serial Port Control. Standard serial port interface supports various product functions, such as data formatting, power-down, gain adjust, and output test pattern generation. 5. The AD9434 is pin compatible with the AD9230, and can be substituted in many applications with minimal design changes.
Rev. A | Page 2 of 28 TABLE OF CONTENTS
REVISION HISTORY
5/11—Rev. 0 to Rev. A Changes to Table 13, Register 10, Bits[7:0] Value, Register 14 Default Value, Register 15 Default Value, Register 17, Bit 7 Value 3/11—Revision 0: Initial Version
Rev. A | Page 3 of 28 SPECIFICATIONS DC SPECIFICATIONS Table 1. AD9434-370 AD9434-500 Parameter1 Temp Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error 25°C ±0.25 ±0.25 mV Gain Error 25°C 1.0 1.0 % FS Differential Nonlinearity (DNL) 25°C ±0.4 ±0.5 LSB Integral Nonlinearity (INL) 25°C ±0.4 ±0.6 LSB INTERNAL REFERENCE TEMPERATURE DRIFT Offset Error Full 18 18 μV/°C Gain Error Full 0.07 0.07 %/°C ANALOG INPUTS (VIN+, VIN−) Input Common-Mode Voltage Full 1.7 1.7 V Input Resistance (Differential) Full 1 1 kΩ Input Capacitance (Differential) 25°C 1.3 1.3 pF POWER SUPPLY Supply Currents IAVDD3 Full 260 280 283 301 mA IDRVDD3/SDR Mode4 Full 88 100 100 114 mA IDRVDD3/DDR Mode5 Full 70 80 82 96 mA Power Dissipation SDR Mode4 Full 625 685 690 747 mW DDR Mode5 Full 595 648 657 715 mW Standby Mode Full 40 50 40 50 mW Power-Down Mode Full 2.5 7 2.5 7 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 30.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9434. 5 Double data rate mode; user-programmable feature. See the Memory Map section.
Rev. A | Page 4 of 28 AC SPECIFICATIONS Table 2. AD9434-370 AD9434-500 Parameter1 , 2 Temp Min Typ Max Min Typ Max Unit S N R fIN = 30.3 MHz 25°C 66.3 65.9 dBFS fIN = 70.3 MHz 25°C 66.2 65.9 dBFS fIN = 100.3 MHz 25°C 66.1 65.8 dBFS Full 65.3 64.5 dBFS fIN = 250.3 MHz 25°C 65.5 65.2 dBFS fIN = 450.3 MHz 25°C 64.0 63.5 dBFS SINAD fIN = 30.3 MHz 25°C 66.1 65.9 dBFS fIN = 70.3 MHz 25°C 66.1 65.8 dBFS fIN = 100.3 MHz 25°C 66.0 65.8 dBFS Full 65.2 64.4 dBFS fIN = 250.3 MHz 25°C 65.3 64.8 dBFS fIN = 450.3 MHz 25°C 63.7 62.9 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30.3 MHz 25°C 10.7 10.7 Bits fIN = 70.3 MHz 25°C 10.7 10.6 Bits fIN = 100.3 MHz 25°C 10.7 10.6 Bits fIN = 250.3 MHz 25°C 10.6 10.5 Bits fIN = 450.3 MHz 25°C 10.3 10.2 Bits WORST HARMONIC (SECOND or THIRD) fIN = 30.3 MHz 25°C −93 −93 dBc fIN = 70.3 MHz 25°C −89 −91 dBc fIN = 100.3 MHz 25°C −83 −87 dBc Full −75 −74 dBc fIN = 250.3 MHz 25°C −80 −78 dBc fIN = 450.3 MHz 25°C −78 −69 dBc SFDR fIN = 30.3 MHz 25°C 89 84 dBc fIN = 70.3 MHz 25°C 88 82 dBc fIN = 100.3 MHz 25°C 83 83 dBc Full 75 74 dBc fIN = 250.3 MHz 25°C 79 78 dBc fIN = 450.3 MHz 25°C 78 68 dBc WORST OTHER HARMONIC (SFDR EXCLUDING SECOND and THIRD) fIN = 30.3 MHz 25°C −90 −85 dBc fIN = 70.3 MHz 25°C −90 −82 dBc fIN = 100.3 MHz 25°C −91 −84 dBc Full −75 −74 dBc fIN = 250.3 MHz 25°C −83 −85 dBc fIN = 450.3 MHz 25°C −82 −78 dBc TWO-TONE IMD fIN1 = 119.5 MHz, fIN2 = 122.5 MHz 25°C −85 −85 dBc ANALOG INPUT BANDWIDTH Full Power 25°C 1 1 GHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. A | Page 5 of 28 DIGITAL SPECIFICATIONS Table 3. AD9434-370 AD9434-500 Parameter1 T emp Min Typ Max Min Typ Max Unit CLOCK INPUTS Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 0.9 V Differential Input Voltage High Level Input (VIH) Full 0.2 1.8 0.2 1.8 V p-p Low Level Input (VIL) Full −1.8 −0.2 −1.8 −0.2 V p-p High Level Input Current (IIH) Full −10 +10 −10 +10 μA Low Level Input Current (IIL) Full −10 +10 −10 +10 μA Input Resistance (Differential) Full 8 10 12 8 10 12 kΩ Input Capacitance Full 4 4 pF LOGIC INPUTS Logic 1 Voltage Full 0.8 × DRVDD 0.8 × DRVDD V Logic 0 Voltage Full 0.2 × DRVDD 0.2 × DRVDD V Logic 1 Input Current (SDIO, CSB) Full 0 0 μA Logic 0 Input Current (SDIO, CSB) Full −60 −60 μA Logic 1 Input Current (SCLK, PDWN) Full 50 50 μA Logic 0 Input Current (SCLK, PDWN) Full 0 0 μA Input Capacitance 25°C 4 4 pF LOGIC OUTPUTS2 VOD Differential Output Voltage Full 247 454 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 1.125 1.375 V Output Coding Twos complement, Gray code, or offset binary (default) 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 LVDS RTERMINATION = 100 Ω.
Rev. A | Page 6 of 28 SWITCHING SPECIFICATIONS Table 4. AD9434-370 AD9434-500 Parameter Temp Min Typ Max Min Typ Max Unit Maximum Conversion Rate Full 370 500 MSPS Minimum Conversion Rate Full 50 50 MSPS CLK+ Pulse Width High (tCH)1, 2 Full 1.1 11 0.9 11 ns CLK+ Pulse Width Low (tCL) Full 1.1 11 0.9 11 ns Output (LVDS—SDR Mode)1 Data Propagation Delay (tPD) Full 0.85 0.85 ns Rise Time (tR) (20% to 80%) 25°C 0.15 0.15 ns Fall Time (tF) (20% to 80%) 25°C 0.15 0.15 ns DCO Propagation Delay (tCPD) Full 0.6 0.6 ns Data to DCO Skew (tSKEW) Full 0.15 0.38 0.15 0.38 ns Latency Full 15 15 Cycles Output (LVDS—DDR Mode)2 Data Propagation Delay (tPD) Full 0.6 0.6 ns Rise Time (tR) (20% to 80%) 25°C 0.15 0.15 ns Fall Time (tF) (20% to 80%) 25°C 0.15 0.15 ns DCO Propagation Delay (tCPD) Full 0.6 0.6 ns Data to DCO Skew (tSKEW) Full −0.07 +0.07 −0.07 +0.07 ns Latency Full 15 15 Cycles Aperture Time (tA) 25°C 0.85 0.85 ns Aperture Uncertainty (Jitter, tJ) 25°C 80 80 fs rms 1 See Figure 2. 2 See Figure 3.
Figure 2. Single Data Rate Mode
6 MSBs
6 LSBs
Figure 3. Double Data Rate Mode
Rev. A | Page 8 of 28 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Electrical AVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +2.0 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −2.0 V to +2.0 V D0+/D0− Through D11+/D11− to DRGND −0.3 V to DRVDD + 0.2 V DCO+, DCO− to DRGND −0.3 V to DRVDD + 0.2 V OR+, OR− to DRGND −0.3 V to DRVDD + 0.2 V CLK+ to AGND −0.3 V to AVDD + 0.2 V CLK− to AGND −0.3 V to AVDD + 0.2 V VIN+ to AGND −0.3 V to AVDD + 0.2 V VIN− to AGND −0.3 V to AVDD + 0.2 V CML to AGND −0.3 V to AVDD + 0.2 V VREF to AGND −0.3 V to AVDD + 0.2 V SDIO to DRGND −0.3 V to DRVDD + 0.2 V PDWN to AGND −0.3 V to DRVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 6. Package Type θJA θ JC Unit 56-Lead LFCSP_VQ (CP-56-5) 23.7 1.7 °C/W Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. ESD CAUTION
35 VIN+
36 VIN–
37 AVDD
38 AVDD
39 AVDD
40 CML
41 AVDD
42 AVDD
34 AVDD
33 AVDD
32 AVDD
31 VREF
30 AVDD
29 PWDN
- DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
- AGND AND DRGND SHOULD BE TIED TO A COMMON
- THE EXPOSED PADDLE MUST BE SOLDERED TO
Figure 4. Pin Configuration—Single Data Rate Mode Table 7. Pin Function Descriptions—Single Data Rate Mode 0 AGND 1 Analog Ground. The exposed paddle must be soldered to a ground plane. 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 8, 23, 48 DRGND1 Digital Output Ground. 36 VIN− Analog Input—Complement. optimized internal bias voltage for VIN+/VIN−. 45 CLK− Clock Input—Complement. 31 VREF Voltage Reference Internal/Input/Output. Nominally 0.75 V. 28 DNC Do Not Connect. Do not connect to this pin. This pin should be left floating. 25 SDIO Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 D0− D0 Complement Output (LSB). 52 D0+ D0 True Output (LSB). 53 D1− D1 Complement Output. 55 D2− D2 Complement Output.
Rev. A | Page 10 of 28 Pin No. Mnemonic Description 4 D4+ D4 True Output. 5 D5− D5 Complement Output. 6 D5+ D5 True Output. 9 D6− D6 Complement Output. 10 D6+ D6 True Output. 11 D7− D7 Complement Output. 12 D7+ D7 True Output. 13 D8− D8 Complement Output. 14 D8+ D8 True Output. 15 D9− D9 Complement Output. 16 D9+ D9 True Output. 17 D10− D10 Complement Output. 18 D10+ D10 True Output. 19 D11− D11 Complement Output (MSB). 20 D11+ D11 True Output (MSB). 21 OR− Overrange Complement Output. 22 OR+ Overrange True Output. 1 AGND and DRGND should be tied to a common quiet ground plane.
- DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
- AGND AND DRGND SHOULD BE TIED TO A COMMON
- THE EXPOSED PADDLE MUST BE SOLDERED TO
Figure 5. Pin Configuration—Double Data Rate Mode Table 8. Pin Function Descriptions—Double Data Rate Mode 0 AGND 1 Analog Ground. The exposed paddle must be soldered to a ground plane. 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 8, 23, 48 DRGND1 Digital Output Ground. 36 VIN− Analog Input—Complement. internal bias voltage for VIN+/VIN−. 45 CLK− Clock Input—Complement. 31 VREF Voltage Reference Internal/Input/Output. Nominally 0.75 V. 25 SDIO Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 D0/D6− D0/D6 Complement Output (LSB). 52 D0/D6+ D0/D6 True Output (LSB). 53 D1/D7− D1/D7 Complement Output. 54 D1/D7+ D1/D7 True Output. 55 D2/D8− D2/D8 Complement Output. 56 D2/D8+ D2/D8 True Output. 1 D3/D9− D3/D9 Complement Output. 3 D4/D10− D4/D10 Complement Output. 4 D4/D10+ D4/D10 True Output. 5 D5/D11− D5/D11 Complement Output (MSB).
Rev. A | Page 12 of 28 Pin No. Mnemonic Description 6 D5/D11+ D5/D11 True Output (MSB). 9 OR− Overrange Complement Output. (This pin is disabled if Pin 21 is reconfigured through the SPI to be OR−.) 10 OR+ Overrange True Output. (This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.) 11 to 20, 28 DNC Do Not Connect. Do not connect to these pins. These pins should be left floating. 21 DNC/(OR−) Do Not Connect. Do not connect to this pin. (This pin can be reconfigured as the overrange complement output through the serial port register.) 22 DNC/(OR+) Do Not Connect. Do not connect to this pin. (This pin can be reconfigured as the overrange true output through the serial port register.) 1 Tie AGND and DRGND to a common quiet ground plane.
Figure 24. AD9434-370 Grounded Input Histogram; 370 MSPS Figure 25. AD9434-500 Grounded Input Histogram; 500 MSPS Figure 26. AD9434-370 64k Point, Two-Tone FFT; 370 MSPS, Figure 27. AD9434-500 64k Point, Two-Tone FFT; 500 MSPS, 119.2 MHz,
122.5 MHz
Figure 28. AD9434-370 Two-Tone SFDR vs. Input Amplitude; 370 MSPS, Figure 29. AD9434-500 Two-Tone SFDR vs. Input Amplitude; 500 MSPS,
DLL to acquire and lock to the new rate. applications are particularly sensitive to jitter (see Figure 48). jitter, crystal-controlled oscillators make the best clock sources. original clock at the last step. performance as it relates to ADCs (visit www.analog.com).
16 BITS
14 BITS
12 BITS
10 BITS
8 BITS
Figure 48. Ideal SNR vs. Input Frequency and Jitter DRVDD supply and bias current of the LVDS output drivers. low returns the AD9434 to its normal operational mode. operation after allowing for the pipeline latency. the output current at each output equal to a nominal 3.5 mA. receiver inputs results in a nominal 350 mV swing at the receiver. for superior switching performance in noisy environments. of the design when the trace lengths exceed 24 inches.
sent to and read from the internal ADC memory map registers. read and write cycles (see Table 9).
- Pin 28 is a DNC (do not connect) on the AD9434, and should be left floating. The reset functionality of the AD9230 is not available through an external pin, but is available through the SPI interface.
- Pin 31 is the interface to the AD9434 reference circuit. It can be used to monitor the internal reference or provide an external reference voltage (nominally 0.5 V). If the internal reference is used, then this pin can float. The RBIAS func- tion of the AD9230 is not necessary with the AD9434.
- The input voltage range of the AD9434 is nominally 1.5 V p-p, whereas the AD9230 input range is 1.25 V p-p.
Table 9. Serial Port Pins SCLK SCLK (serial clock) is the serial shift clock in. and the relative position in the timing frame. gates the read and write cycles. During an instruction phase, a 16-bit instruction is transmitted. change direction from an input to an output. High Speed ADCs via SPI at www.analog.com. strappable functions supported on the AD9434. AVDD, which disables the serial port interface. Table 10. Mode Selection
Figure 52. Serial Port Interface Timing Diagram Table 11. Serial Timing Definitions Table 12. Output Data Format
functions register map (Address 0x08 to Address 0x2A). have a 0 written into their registers during power-up. Table 13. Memory Map Register
00 CHIP_PORT_CONFIG 0 LSB
01 CHIP_ID 8-bit chip ID, Bits[7:0] = 0x6A Read
02 CHIP_GRADE 0 0 0 Speed grade:
1 X X
1 X 1 Read
08 Modes 0 0 PDWN:
Rev. A | Page 26 of 28 Addr. (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments
10 Offset 8-bit device offset adjustment [7:0]
0111 1111 = +127 codes 0000 0000 = 0 codes 1000 0000 = −128 codes 0x00 Device offset trim: codes are relative to the output resolution. 0D TEST_IO (For user-defined mode only, set Bits[3:0] = 1000) 00 = Pattern 1 only 01 = toggle P1/P2 10 = toggle P1/0000 11 = toggle P1/P2/ 0000 Reset PN23 gen: 1 = on 0 = off (default) Reset PN9 gen: 1 = on 0 = off (default) Output test mode: 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN23 sequence 0110 = PN9 0111 = one/zero word toggle 1000 = user defined 1001 = unused 1010 = unused 1011 = unused 1100 = unused (Format determined by OUTPUT_MODE) 0x00 When set, the test data is placed on the output pins in place of normal data. Set pattern values: P1 = Reg 0x19, Reg 0x1A P2 = Reg 0x1B, Reg 0x1C. 0F AIN_CONFIG 0 0 0 0 0 Analog input disable: 1 = on 0 = off (default) 0 0 0x00
14 OUTPUT_MODE 0 0 0 Output
enable: 0 = enable (default) 1 = disable DDR: 1 = enabled 0 = disabled (default) Output invert: 1 = on 0 = off (default) Data format select: 00 = offset binary (default) 01 = twos complement 10 = Gray code 0x00
15 OUTPUT_ADJUST 0 0 0 0 LVDS
adjust: 0 = 3.5 mA (default) 1 = 2.0 mA LVDS fine adjust: 001 = 3.50 mA 010 = 3.25 mA 011 = 3.00 mA 100 = 2.75 mA 101 = 2.50 mA 110 = 2.25 mA 111 = 2.00 mA 0x00
16 OUTPUT_PHASE Output
1 = inverted 0 = normal (default) 0 0 0 0 0 0 0 0x00
17 FLEX_OUTPUT_DELAY 0 0 0 0 Output clock delay:
0000 = 0 0001 = −1/10 0010 = −2/10 0011 = −3/10 0100 = reserved 0101 = +5/10 0110 = +4/10 0111 = +3/10 1000 = +2/10 1001 = +1/10 0x00 Shown as fractional value of sampling clock period that is subtracted or added to initial t SKEW, see Figure 2
Rev. A | Page 27 of 28 Addr. (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments
18 FLEX_VREF VREF select
00 = internal VREF (20 kΩ pull-down) 01 = import VREF (0.59 V to 0.8 V on VREF pin) 10 = export VREF (from internal reference) 11 = not used
0 Input voltage range setting:
11100 = 1.60 00101 = 1.36 11101 = 1.58 00110 = 1.34 11110 = 1.55 00111 = 1.31 11111 = 1.52 01000 = 1.28 00000 = 1.50 01001 = 1.26 00001 = 1.47 01010 = 1.23 00010 = 1.44 01011 = 1.20 00011 = 1.42 01100 = 1.18 00100 = 1.39 0x00
19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
pattern, 1 LSB. 1A USER_PATT1_MSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 MSB. 1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSBs. 1C USER_PATT2_MSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 MSBs. 2A OVR_CONFIG 0 0 0 0 0 0 OR± position (DDR mode only): 0 = Pin 9, Pin 10 1 = Pin 21, Pin 22 OR± enable: 1 = on (default) 0 = off 0x01 2C Input coupling 0 0 0 0 0 DC coupling enable 0 0 0x00 Default is ac coupling. 1 X = don’t care.
0.20 REF
0.65 TYP
6.50 REF
0.60 MAX
0.05 MAX
0.02 NOM
0.25 MIN
Figure 53. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the prop erty of their respective owners.