AD9432BSQZ-80

AD9432BSQZ-80 AD | Alldatasheet

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REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9432 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 12-Bit, 80 MSPS/105 MSPS A/D Converter FUNCTIONAL BLOCK DIAGRAM 12AIN ENCODE AD9432 GND VREFOUT D11–D0 VREFIN AIN ENCODE VCC VDD TIMING REF OUTPUT STAGING PIPELINE ADCBUF T/H OR

FEATURES

On-Chip Reference and Track/Hold On-Chip Input Buffer 850 mW Typical Power Dissipation at 105 MSPS

500 MHz Analog Bandwidth

SNR = 67 dB @ 49 MHz AIN at 105 MSPS SFDR = 80 dB @ 49MHz AIN at 105 MSPS

2.0 V p-p Differential Analog Input Range

Single 5.0 V Supply Operation

3.3 V CMOS/TTL Outputs

Two’s Complement Output Format

APPLICATIONS

Basestations and ‘Zero-IF’ Subsystems Wireless Local Loop (WLL) Local Multipoint Distribution Service (LMDS) HDTV Broadcast Cameras and Film Scanners GENERAL INTRODUCTION The AD9432 is a 12-bit monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and is optimized for high-speed conversion and ease of use. The product operates at a 105 MSPS conversion rate with outstanding dyn amic per- formance over its full operating range. The ADC requires only a single 5.0 V power supply and a 105 MHz encode clock for full-performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3 V logic. The encode input supports either differential or single-ended and is TTL/CMOS-compatible. Fabricated on an advanced BiCMOS process, the AD9432 is available in a 52-lead plastic quad flatpack package (LQFP) specified over the industrial temperature range (–40°C to +85°C).

REV. E–2– AD9432–SPECIFICATIONS Test AD9432BST/BSQ-80 AD9432BST/BSQ-105 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits DC ACCURACY No Missing Codes Full VI Guaranteed Guaranteed Gain Error1 25°C I –5 +2 +7 –5 +2 +7 % FS Gain Tempco1 Full V 150 150 ppm/ °C ANALOG INPUT Input Voltage Range (AIN– AIN) Full V ±1.0 ±1.0 V Common-Mode Voltage Full V 3.0 3.0 V Input Offset Voltage Full VI –5 ±0+ 5 – 5 ±0+ 5 m V Input Resistance Full VI 2 3 4 2 3 4 k Ω Input Capacitance 25 °CV 4 4 p F Analog Bandwidth, Full Power 25 °C V 500 500 MHz ANALOG REFERENCE Tempco Full V 50 50 ppm/ °C Input Bias Current Full VI 15 50 15 50 µΑ SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 80 105 MSPS Minimum Conversion Rate Full IV 1 1 MSPS Encode Pulsewidth High (t EH)2 5 °C IV 4.0 6.2 4.0 4.8 ns Encode Pulsewidth Low (t EL)2 5 °C IV 4.0 6.2 4.0 4.8 ns Aperture Delay (tA)2 5 °C V 2.0 2.0 ns Aperture Uncertainty (Jitter) 25 °C V 0.25 0.25 ps rms Output Valid Time (t V)2 Full VI 3.0 5.3 3.0 5.3 ns Output Propagation Delay (t PD)2 Full VI 5.5 8.0 5.5 8.0 ns Output Rise Time (t R)2 Full V 2.1 2.1 ns Output Fall Time (tF) Full V 1.9 1.9 ns Out-of-Range Recovery Time 25 °CV 2 2 n s Transient Response Time 25 °CV 2 2 n s Latency Full IV 10 10 Cycles DIGITAL INPUTS Encode Input Common Mode Full V 1.6 1.6 V Differential Input (ENC– ENC) Full V 750 750 mV Single-Ended Logic “1” Voltage Full IV 2.0 2.0 V Logic “0” Voltage Full IV 0.8 0.8 V Input Resistance Full VI 3 5 8 3 5 8 k Ω Input Capacitance 25 °C V 4.5 4.5 pF DIGITAL OUTPUTS Logic “1” Voltage (VDD = 3.3 V) Full VI V DD – 0.05 V DD – 0.05 V Logic “0” Voltage (VDD = 3.3 V) Full VI 0.05 0.05 V Output Coding Two’s Complement Two’s Complement POWER SUPPLY Power Dissipation3 Full VI 790 1000 850 1100 mW Power Supply Rejection Ratio (PSRR) 25 °C I –5 +0.5 +5 –5 +0.5 +5 mV/V IVCC Full VI 158 200 170 220 mA IVDD Full VI 9.5 12.2 12.5 16 mA (VDD = 3.3 V, VCC = 5.0 V; external reference; differential encode input, unless otherwise noted.)

REV. E –3– AD9432 Test AD9432BST/BSQ-80 AD9432BST/BSQ-105 Parameter Temp Level Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE4 Signal-to-Noise Ratio (SNR) (Without Harmonics) f fIN = 40 MHz 25 °C I 65 67.2 67.2 dB fIN = 49 MHz 25 °C I 67.0 64 67.0 dB fIN = 70 MHz 25 °C V 66.1 66.1 dB Signal-to-Noise Ratio (SINAD) (With Harmonics) f IN = 10.3 MHz 25 °C I 65 67.2 65 67.2 dB fIN = 40 MHz 25 °C I 64.5 66.9 66.9 dB fIN = 49 MHz 25 °C I 66.7 63 66.7 dB fIN = 70 MHz 25 °C V 65.8 65.8 dB Effective Number of Bits fIN = 10 MHz 25 °C V 11.0 11.0 Bits fIN = 40 MHz 25 °C V 10.9 10.9 Bits fIN = 49 MHz 25 °C V 10.9 10.9 Bits fIN = 70 MHz 25 °C V 10.7 10.7 Bits Second and Third Harmonic Distortion fIN = 10 MHz 25 °C I –75 –85 –75 –85 dBc fIN = 40 MHz 25 °C I –73 –85 –83 dBc fIN = 49 MHz 25 °C I –83 –72 –80 dBc fIN = 70 MHz 25 °C V –80 –78 dBc Worst Harmonic or Spur (Excluding Second and Third) fIN = 10 MHz 25 °C I –80 –90 –80 –90 dBc fIN = 40 MHz 25 °C I –80 –90 –90 dBc fIN = 49 MHz 25 °C I –90 –80 –90 dBc fIN = 70 MHz 25 °C V –90 –90 dBc Two-Tone Intermod Distortion (IMD) fIN1 = 29.3 MHz; fIN2 = 30.3 MHz 25 °C V –75 –75 dBc fIN1 = 70.3 MHz; fIN2 = 71.3 MHz 25 °C V –66 –66 dBc NOTES 1Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p dif ferential analog input). 2tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital ou tput load during test is not to exceed an ac load of 10 pF or a dc current of ±40 µA. Rise and fall times measured from 10% to 90%. 3Power dissipation measured with encode at rated speed and a dc analog input. (Outputs Static, I VDD = 0.) 4SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 2 V full-scale input range. Specifications subject to change without notice.

REV. E AD9432 –4– ABSOLUTE MAXIMUM RATINGS * *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9432 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PowerQuad is a registered trademark of AMkor Technology, Inc. THERMAL CHARACTERISTICS 52-Lead Plastic LQFP (ST-52) /H9258JA = 50°C/W, No Airflow 52-lead PowerQuad® 4 LQFP (SQ-52) /H9258JA = 25°C/W, Soldered Exposed Heat Sink, No Airflow /H9258JA = 33°C/W, Unsoldered Exposed Heat Sink, No Airflow /H9258JC = 2°C/W, Bottom of package (Exposed Heat Sink) Simulated Typical performance for 4-layer JEDEC board, horizontal orientation. ORDERING GUIDE Temperature Package Package Model Ranges Descriptions Option AD9432BSQ –40 °C to +85°C 52-Lead Thermally SQ-52 -80, -105 Enhanced Plastic Quad Flatpack AD9432BST –40 °C to +85°C 52-Lead Plastic Quad ST-52 -80, -105 Flatpack (LQFP) AD9432/PCB 25 °C Evaluation Board EXPLANATION OF TEST LEVELS Test Level I 100% production tested. II 100% production tested at 25 °C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25 °C; guaranteed by design and characterization testing for industrial temperature range.

REV. E AD9432 –5– PIN CONFIGURATION 52 51 50 49 48 43 42 41 4047 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) GND GND GND OR AD9432 GND VCC VCC GND GND GND VDD DGND D0 (LSB) VCC GND GND VCC VCC ENCODE ENCODE GND VCC GND DGND VDD (MSB) D11 D10 DGND VDD VDD DGND DNC VCC GND VREFIN VREFOUT VCC AIN AIN GND GND VCC VCC DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between a differential crossing of ENCODE and ENCODE and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic “1” state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise Plus Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. PIN FUNCTION DESCRIPTIONS Pin Number (AD9432BST) Mnemonic Function 1, 3, 4, 9, 11, 33, 34, 35, 38, 39, 40, 43, 48, 51 GND Analog Ground 2, 5, 6, 10, 36, 37, 42, 44, 47, 52 V CC Analog Supply (5 V)

7 ENCODE Encode Clock for ADC–Complementary

8 ENCODE Encode Clock for ADC–True (ADC samples on rising edge of ENCODE)

14 OR Out of Range Output

15–20, 25–30 D11–D6, D5–D0 Digital Output 12, 21, 24, 31 DGND Digital Output Ground 13, 22, 23, 32 V DD Digital Output Power Supply (2.7 V to 3.6 V)

41 DNC Do Not Connect

45 VREFIN Reference Input for ADC (2.5 V Typical); Bypass with 0.1 µF to Ground. 46 VREFOUT Internal Reference Output (2.5 V Typical)

49 AIN Analog Input–True

50 AIN Analog Input–Complementary

REV. E AD9432 –7– ENCODE – MSPS 02 0 dB 40 60 80 100 120 140 160 AIN = 10.3MHz SINAD SFDR SNR TPC 1. SNR/SINAD/SFDR vs. fS: fIN = 10.3 MHz ENCODE – MSPS 02 0 dBc 40 60 80 100 120 140 160 –90 –95 –100 –85 –80 –75 –70 –65 –60 –55 –50 AIN = 10.3MHz 2nd 3rd TPC 2. Harmonics vs. fS: fIN = 10.3 MHz ANALOG INPUT FREQUENCY – MHz 02 0 dB 40 60 80 100 120 140 160 200 ENCODE = 105MSPS SINAD (–0.5dBFS) SINAD (–3.0dBFS) SINAD (–6.0dBFS) 180 TPC 3. SINAD vs. fIN: fS = 105 MSPS AIN INPUT FREQUENCY – MHz (–0.5dBFS) SNR – dB 50 100 150 200 250 TPC 4. SNR vs. AIN Input Frequency, Encode = 105 MSPS ANALOG INPUT FREQUENCY – MHz 0 100 dBc 20 12040 14060 16080 100 180 2nd or 3rd (–3.0dBFS) 2nd or 3rd (–6.0dBFS) 2nd or 3rd (–0.5dBFS) 200 ENCODE = 105MSPS TPC 5. Harmonics vs. fIN: fS = 105 MSPS ANALOG INPUT FREQUENCY – MHz 02 0 dBc 40 60 80 100 120 140 160 100 180 200 WORST OTHER (–3.0dBFS) WORST OTHER (–6.0dBFS) WORST OTHER (–0.5dBFS) ENCODE = 105MSPS TPC 6. Worst-Case Spur (Other than Second and Third) vs. fIN: fS = 105 MSPS Typical Performance Characteristics–

REV. E AD9432 –8– dB SAMPLES –80 –90 –100 –70 –60 –50 –40 –30 –20 –10 –110 –120 ENCODE = 105MSPS AIN = 10.3MHz (–0.53dBFS) SNR = 67.32dB SINAD = 67.07dB SFDR = –85dBc TPC 7. Spectrum: fS = 105 MSPS, fIN = 10.3 MHz SAMPLES dB –80 –90 –100 –70 –60 –50 –40 –30 –20 –10 –110 –120 ENCODE = 105MSPS AIN = 27.0MHz (–0.52dBFS) SNR = 67.3dB SINAD = 67.0dB SFDR = –83.1dBc TPC 8. Spectrum: fS = 105 MSPS, fIN = 27 MHz SAMPLES dB –80 –90 –100 –70 –60 –50 –40 –30 –20 –10 –110 –120 ENCODE = 105MSPS AIN = 40.9MHz (–0.56dBFS) SNR = 67.2dB SINAD = 66.9dB SFDR = –80dBc TPC 9. Spectrum: fS = 105 MSPS, fIN = 40.9 MHz SAMPLES dB –80 –90 –100 –70 –60 –50 –40 –30 –20 –10 –110 –120 ENCODE = 105MSPS AIN = 50.3MHz (–0.46dBFS) SNR = 67.0dB SINAD = 66.7dB SFDR = –80dBc TPC 10. Spectrum: fS = 105 MSPS, fIN = 50.3 MHz SAMPLES dBc –80 –90 –100 –70 –60 –50 –40 –30 –20 –10 –110 –120 AIN1 = 29.3MHz (–7dBFS) AIN2 = 30.3MHz (–7dBFS) ENCODE = 105MSPS TPC 11. Two-Tone Spectrum, Wideband: fS = 105 MSPS, AIN1 = 29.3 MHz, AIN2 = 30.3 MHz SAMPLES dBc –80 –90 –100 –70 –60 –50 –40 –30 –20 –10 –110 –120 AIN1 = 70.3MHz (–7dBFS) AIN2 = 71.3MHz (–7dBFS) ENCODE = 105MSPS TPC 12. Two-Tone Spectrum, Wideband: fS = 105 MSPS, AIN1 = 70.3 MHz, AIN2 = 71.3 MHz

REV. E AD9432 –9– ANALOG INPUT POWER LEVEL – dBFS –80 –70 WORST-CASE SPURIOUS – dBc AND dBFS 100 110 –50 0 dBFS dBc ENCODE = 105MSPS AIN = 50.3MHz TPC 13. Single Tone SFDR LSB DNL –0.50 –0.75 –0.25 0.00 0.25 0.50 0.75 1.00 –1.00 TPC 14. Differential Nonlinearity: fS = 105 MSPS LSB INL –0.50 –0.75 –0.25 0.00 0.25 0.50 0.75 1.00 –1.00 TPC 15. Integral Nonlinearity: fS = 105 MSPS CURRENT – mA VOLTAGE – V 48 1 0 2.0 2.5 3.0 1.5 TPC 16. Voltage Reference Output vs. Current Load

and output clock are available at a standard 37-pin connector P7. by coupling two transformers in series as shown in Figure 13. Figure 13. Improving Second Harmonic Distortion

14 ACQS

Figure 14. Analog Input Levels Figure 14. The analog inputs are dc biased by two on-chip ure 14. The lower trace is the input at SMB P2 (on a 2 V/div scale). common-mode dc levels required at the AD9432 encode inputs. required at the output latches, DAC, and 37-pin connector. generated on the card is also shown in the plot. Figure 15. Encode+ Clock and Latch Clock

265 ACQS

Figure 16. Data Bit and Clock at 37-Pin Connector placing an AD780 voltage reference on the board (not supplied). the ADC, as it will not accurately indicate the ADC performance. load. Provision to power down the DAC is at Pin 15 at the DAC. components, and routing are located on the bottom layer.

• Verify power at IC pins.
• Check that all jumpers are in the correct position for the desired mode of operation.
• Verify VREF is at 2.5 V.
• Try running encode clock and analog inputs at low speeds (10 MSPS/1 MHz) and monitor 574 outputs, DAC output, and ADC outputs for toggling. The AD9432 Evaluation Board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.

REV. E AD9432 –14– PCB Bill of Materials # Quantity REFDES Device Package Value 1 30 C1–C8, C10–C13, C17, C19–C22, Capacitor 603 0.1 µF C27–C29, C41, C42, C47, C48, C53, C56, C58, C60, C61, C70 2 1 C9 Capacitor 603 0.01 µF 3 4 C14, C18, C31, C34 Capacitor CAPTAJD 10 µF 4 1 C15 Capacitor CAPTAJD 1 µF 5 18 E1–E13, E30, E32, E40, E42, E43 E-HOLE Test Point 6 3 P1, P2, P3 Connector SMB 7 1 P7 37-Pin Connector Female AMP 747462-2 8 2 P30, P40 Power Connector 9 6 R1, R2, R7, R8, R10, R18 Resistor 1206 50 Ω (R1, R2, R10 Optional) 10 2 R3, R35 Resistor 1206 100 Ω 11 4 R25, R26, R31, R32 Resistor 1206 500 Ω 12 2 R6, R24 Resistor 1206 2 k Ω 13 4 RP1–RP4 RES PAK 100 Ω 14 1 T1 Transformer Mini-Circuits ADT1-1WT 15 1 U1 DAC SOIC AD9752 16 1 U2 Reference (Not Supplied) SOIC AD780N 17 2 U3, U4 Inverter (U4 Not Supplied) SC70 NC7SZ04P5 18 1 U9 ADC 52QFP AD9432 19 2 U12–U13 Latch SOIC 74AC574M 20 1 Z1 PECL/TTL Translator SOIC MC100ELT23 21 2 Z2, Z3 Differential Receiver SOIC MC10EL16 22 3 R4, R5, R15 Resistor 1206 24.9 Ω

REV. E AD9432 –15– 9 D4 100/H9024 RP2 RPAK_742 9 OR D11 D10 100/H9024 RPAK_742 OR (MSB) D11 D10 VREFIN VREFOUT AIN AIN ENC ENC AD9432 RP1 VCC VD VCC AGND AGND 0.1/H9262F VCC FLOAT AGND AGND 0.1/H9262F E3EXTREF AGND VCC NC +VIN TEMP GND 2.5/3V NC VOUT TRIM (NOT SUPPLIED) AD780N C15 1/H9262F AGND VCC C14 10/H9262F AGND EXTREF R10 50/H9024 (OPTIONAL) C11 0.1/H9262F AGND ADT1-1WT AGND ANALOG SMBPN 0.01/H9262F C70 0.1/H9262F AGNDAGND D08 D18 VCC GND MC100ELT23 AGND AGND AGND 0.1/H9262F 0.1/H9262F AIN AIN AGND VCC2 AGND 0.1/H9262F AGND VD 0.1/H9262F VCC Y NC A GND 3 4 AGND NC7SZ04P5 U4 (NOT SUPPLIED) CLOCK AGND VD 100/H9024 100/H9024 50/H9024 50/H9024 DR DR MC10EL16 AGND VCC2 AGND C60 0.1/H9262F AGND AGND R25 500/H9024 R26 500/H9024 AGND AGND R31 500/H9024 R32 500/H9024 AGND VCC AGND C61 0.1/H9262F NC D DB VBB VCC Q QB VEE MC10EL16 C58 0.1/H9262F AGND NC D DB VBB VCC Q QB VEE 24.9/H9024 24.9/H9024 R35 100/H9024 C47 0.1/H9262F ENCODE SMBPN 0.1/H9262FAGND 100/H9024 PRI SEC NC = NO CONNECT (R1, R2, OPTIONAL) Figure 17a. PCB Schematic

REV. E AD9432 –16– 100/H9024 RP3 AGND GND OUT_EN GND VCC CLOCK U13 CLOCK VD 100/H9024 RP4 GND D10 D11 OR GND OUT_EN GND VCC CLOCK U12 CLOCK VD B10 B11 RPAK_742 RPAK_742 INV MSB BOR 74AC574M 74AC574M AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND DR AGND 1 BOR B11 B10 DR P37 P36 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 AGND VCC2 C17 0.1/H9262FCLOCK GND AGNDC10 0.1/H9262F C13 0.1/H9262F R24 2k/H9024 R15 24.9/H9024 R18 50/H9024 AGNDAGND SMBPN C12 0.1/H9262FAGND VCC2 DACOUT AGNDAGNDAGNDVCC2 2k/H9024 E1 E8 CLK DVDD DCON NC2 AVDD ICOMP IOUTA IOUTB ACON NC3 FSADJ REFIO REFLO SLEEP D11 D10 NC NC1 AD9752 MSB B10 AGND 0.1/H9262F VCC25 NC A GND VCC Y NC7SZ04P5 AGND INV E12 E11 E10 E32 E30 AGND GROUND PLANE CONNECTING E-HOLES E7DR E6CLOCK E40DR E43D11 E42D0 SCOPE TEST POINTS P30 P40 AGND VD (+3V) AGND VCC (+5V) AGND VCC2 (+5V) NC NC AGND C34 10/H9262F C48 0.1/H9262F C19 0.1/H9262F C20 0.1/H9262F C21 0.1/H9262F C22 0.1/H9262F C56 0.1/H9262F C53 0.1/H9262F VCC OUT BYPASS C18 10/H9262F AGND VCC2 C41 0.1/H9262F C42 0.1/H9262F AGND VD C27 0.1/H9262F C29 0.1/H9262F AGND VD C28 0.1/H9262F C31 10/H9262F OUT BYPASS LATCHES AGND NC = NO CONNECT Figure 17b. PCB Schematic (Continued)

REV. E AD9432 –18– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 52-Lead Plastic Quad Flatpack (LQFP) (ST-52) TOP VIEW (PINS DOWN) 2739 0.026 (0.65) BSC 0.472 (12.00) SQ 0.394 (10.0) SQ 0.015 (0.38) 0.009 (0.22) 0.063 (1.60) MAX SEATING PLANE 0.030 (0.75) 0.018 (0.45) 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN THERMALLY ENHANCED 52-Lead Power Thin Plastic Quad Flatpack (LQFP_ED) (SQ-52) 0.013 (0.32) 0.009 (0.22) 0.472 (12.00) SQ 0.402 (10.20) 0.394 (10.00) SQ 0.386 (9.80) TOP VIEW (PINS DOWN) 4052 0.307 (7.80) 0.063 (1.60) MAX VIEW ASEA TING PLANE 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 0.006 (0.15) 0.002 (0.05) VIEW A 0.004 (0.10) COPLANARITY 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) 40 52 EXPOSED HEA TSINK (CENTERED) 0.093 (2.35) 0.087 (2.20) 0.081 (2.05) (4 PLCS) 0.236 (6.00) 0.232 (5.90) 0.228 (5.80) 0.236 (6.00) 0.232 (5.90) 0.228 (5.80) 0.104 (2.65) 0.098 (2.50) 0.093 (2.35) (4 PLCS) BOTTOM VIEW (PINS UP) NOTES 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONL Y AND ARE NOT APPROPRIA TE FOR USE IN DESIGN. 2. AL THOUGH NOT REQUIRED IN ALL APPLICA TIONS, THE AD9432 HAS AN EXPOSED MET ALLIC P AD ON THE P ACKAGE BOTTOM WHICH IS INTENDED TO ENHANCE THE HEA T REMOVAL P A TH. TO MAXIMIZE THE REMOVAL OF HEA T, A LAND P A TTERN WITH CLOSEL Y SP ACED THERMAL VIAS TO THE GROUND PLANE(S) SHOULD BE INCORPORA TED ON THE PCB WITHIN THE FOOTPRINT OF THE P ACKAGE CORRESPONDING TO THE EXPOSED MET AL P AD DIMENSIONS OF THE P ACKAGE. THE SOLDERABLE LAND AREA SHOULD BE SOLDER MASK DEFINED AND BE A T LEAST THE SAME SIZE AND SHAPE AS THE EXPOSED P AD AREA ON THE P ACKAGE. A T LEAST 0.25 MM CLEARANCE BETWEEN THE OUTER EDGES OF THE LAND P A TTERN AND THE INNER EDGES OF THE P AD P A TTERN SHOULD BE MAINT AINED TO AVOID ANY SHORTS.

REV. E AD9432 –19–

Revision History

Data Sheet changed from REV. D to REV. E.

–20– C00587–0–1/02(E) PRINTED IN U.S.A.