AD9432 (Rev. F)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 16
Technical content
12-Bit, 80 MSPS/105 MSPS ADC AD9432 Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
FEATURES
On-chip reference and track-and-hold On-chip input buffer Power dissipation: 850 mW typical at 105 MSPS
500 MHz analog bandwidth
SNR: 67 dB @ 49 MHz AIN at 105 MSPS SFDR: 80 dB @ 49 MHz AIN at 105 MSPS
2.0 V p-p analog input range
5.0 V supply operation
3.3 V CMOS/TTL outputs
Twos complement output format
APPLICATIONS
Base stations and zero-IF subsystems Wireless local loop (WLL) Local multipoint distribution service (LMDS) HDTV broadcast cameras and film scanners GENERAL INTRODUCTION The AD9432 is a 12-bit, monolithic sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit and is optimized for high speed conversion and ease of use. The prod- uct operates up to a 105 MSPS conversion rate with outstanding dynamic performance over its full operating range. The ADC requires only a single 5.0 V power supply and a 105 MHz encode clock for full performance operation. No external refer- ence or driver components are required for many applications. The digital outputs are TTL-/CMOS-compatible, and a separate output power supply pin supports interfacing with 3.3 V logic. The encode input supports either differential or single-ended mode and is TTL-/CMOS-compatible. Fabricated on an advanced BiCMOS process, the AD9432 is available in a 52-lead low profile quad flat package (LQFP) and in a 52-lead thin quad flat package (TQFP_EP). The AD9432 is specified over the industrial temperature range of −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM T/HBUF PIPELINE ADC REFTIMING OUTPUT STAGING AD9432 VCC VDD GND VREFOUT VREFIN D11 TO D0 OR ENCODE ENCODE AIN AIN 00587-001 Figure 1.
Rev. F | Page 2 of 16 TABLE OF CONTENTS
REVISION HISTORY
6/09—Rev. E to Rev. F Changes to Pin Configurations and Function Descriptions 1/02—Rev. D to Rev. E
Rev. F | Page 3 of 16 SPECIFICATIONS VDD = 3.3 V , VCC = 5.0 V; external reference; differential encode input, unless otherwise noted. Table 1. Parameter Temp Test 80 MSPS 105 MSPS Level Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits DC ACCURACY No Missing Codes Full VI Guaranteed Guaranteed Gain Error1 25°C I −5 +2 +7 −5 +2 +7 % FS Gain Tempco1 Full V 150 150 ppm/°C ANALOG INPUTS (AIN, AIN) Input Voltage Range Full V 2 2 V p-p Common-Mode Voltage Full V 3.0 3.0 V Input Offset Voltage Full VI −5 ±0 +5 −5 ±0 +5 mV Input Resistance Full VI 2 3 4 2 3 4 kΩ Input Capacitance 25°C V 4 4 pF Analog Bandwidth, Full Power 25°C V 500 500 MHz ANALOG REFERENCE Tempco Full V 50 50 ppm/°C Input Bias Current Full VI 15 50 15 50 μΑ SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 80 105 MSPS Minimum Conversion Rate Full IV 1 1 MSPS Encode Pulse Width High (tEH) 25°C IV 4.0 6.2 4.0 4.8 ns Encode Pulse Width Low (tEL) 25°C IV 4.0 6.2 4.0 4.8 ns Aperture Delay (tA) 25°C V 2.0 2.0 ns Aperture Uncertainty (Jitter) 25°C V 0.25 0.25 ps rms Output Valid Time (tV)2 Full VI 3.0 5.3 3.0 5.3 ns Output Propagation Delay (tPD)2 Full VI 5.5 8.0 5.5 8.0 ns Output Rise Time (tR)2 Full V 2.1 2.1 ns Output Fall Time (tF)2 Full V 1.9 1.9 ns Out-of-Range Recovery Time 25°C V 2 2 ns Transient Response Time 25°C V 2 2 ns Latency Full IV 10 10 Cycles DIGITAL INPUTS Encode Input Common Mode Full V 1.6 1.6 V Differential Input (ENCODE, ENCODE) Full V 750 750 mV Single-Ended Input Logic 1 Voltage Full IV 2.0 2.0 V Logic 0 Voltage Full IV 0.8 0.8 V Input Resistance Full VI 3 5 8 3 5 8 kΩ Input Capacitance 25°C V 4.5 4.5 pF DIGITAL OUTPUTS Logic 1 Voltage (VDD = 3.3 V) Full VI VDD − 0.05 VDD − 0.05 V Logic 0 Voltage (VDD = 3.3 V) Full VI 0.05 0.05 V Output Coding Twos complement Twos complement
Rev. F | Page 4 of 16 Parameter Temp Test 80 MSPS 105 MSPS Level Min Typ Max Min Typ Max Unit POWER SUPPLY Power Dissipation3 Full VI 790 1000 850 1100 mW IVCC Full VI 158 200 170 220 mA IVDD Full VI 9.5 12.2 12.5 16 mA Power Supply Rejection Ratio (PSRR) DYNAMIC PERFORMANCE4 Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10 MHz 25°C I 65.5 67.5 65.5 67.5 dB fIN = 40 MHz 25°C I 65 67.2 67.2 dB fIN = 49 MHz 25°C I 67.0 64 67.0 dB fIN = 70 MHz 25°C V 66.1 66.1 dB Signal-to-Noise and Distortion (SINAD) Ratio (with Harmonics) fIN = 10 MHz 25°C I 65 67.2 65 67.2 dB fIN = 40 MHz 25°C I 64.5 66.9 66.9 dB fIN = 49 MHz 25°C I 66.7 63 66.7 dB fIN = 70 MHz 25°C V 65.8 65.8 dB Effective Number of Bits (ENOB) fIN = 10 MHz 25°C V 11.0 11.0 Bits fIN = 40 MHz 25°C V 10.9 10.9 Bits fIN = 49 MHz 25°C V 10.9 10.9 Bits fIN = 70 MHz 25°C V 10.7 10.7 Bits Second-Order and Third-Order Harmonic Distortion fIN = 10 MHz 25°C I −75 −85 −75 −85 dBc fIN = 40 MHz 25°C I −73 −85 −83 dBc fIN = 49 MHz 25°C I −83 −72 −80 dBc fIN = 70 MHz 25°C V −80 −78 dBc Worst Other Harmonic or Spur (Excluding Second-Order and Third-Order Harmonics) fIN = 10 MHz 25°C I −80 −90 −80 −90 dBc fIN = 40 MHz 25°C I −80 −90 −90 dBc fIN = 49 MHz 25°C I −90 −80 −90 dBc fIN = 70 MHz 25°C V −90 −90 dBc Two-Tone Intermodulation Distortion (IMD) fIN1 = 29.3 MHz; fIN2 = 30.3 MHz 25°C V −75 −75 dBc fIN1 = 70.3 MHz; fIN2 = 71.3 MHz 25°C V −66 −66 dBc 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input). 2 tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital output swing. The digital output load during testing is not to exceed an ac load of 10 pF or a dc current of ±40 μA. Rise and fall times are measured from 10% to 90%. 3 Power dissipation measured with encode at rated speed and a dc analog input (outputs static, IVDD = 0). 4 SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 2 V full-scale input range.
Figure 2. Timing Diagram
THERMAL CHARACTERISTICS Table 2. performance in a 4-layer JEDEC board, horizontal orientation. Table 3. Thermal Resistance 1 Bottom of package (soldered exposed pad). V Parameter is a typical value only. characterization testing for industrial temperature range.
38 GND
37 VCC
36 VCC
33 GND
34 GND
35 GND
39 GND
32 VDD
31 DGND
30 D0 (LSB)
- ALTHOUGH NOT REQUIRED IN ALL APPLICATIONS, THE EXPOSED PADDLE
THE THERMAL CAPABILITY OF THE PACKAGE. Figure 3. Pin Configuration, LQFP Figure 4. Pin Configuration, TQFP_EP Table 4. Pin Function Descriptions 7 ENCODE Encode Clock for ADC, Complementary. 8 ENCODE Encode Clock for ADC, True. ADC samples on rising edge of ENCODE. 12, 21, 24, 31 DGND Digital Output Ground. 13, 22, 23, 32 V DD Digital Output Power Supply (2.7 V to 3.6 V). 15 to 20, 25 to 30 D11 to D6, D5 to D0 Digital Output. 45 VREFIN Reference Input for ADC (2.5 V Typical). Bypass with 0.1 μF capacitor to ground. 46 VREFOUT Internal Reference Output (2.5 V Typical). 50 AIN Analog Input, Complementary. increases the reliability of the solder joints, maximizing the thermal capability of the package.
Rev. F | Page 11 of 16 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between a differential crossing of ENCODE and ENCODE and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity (DNL) The deviation of any code from an ideal 1 LSB step. Effective Number of Bits (ENOB) The effective number of bits (ENOB) is calculated from the measured SNR based on the following equation: 02 . 6 log 20 dB 76 . 1 ⎟⎟ ⎛ −+ − AmplitudeInput AmplitudeScale FullSNR ENOB MEASURED Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the encode pulse should be left in the Logic 1 state to achieve the rated per- formance. Pulse width low is the minimum amount of time that the encode pulse should be left in the Logic 0 state. At a given clock rate, these specifications define an acceptable encode duty cycle. Harmonic Distortion The ratio of the rms signal amplitude fundamental frequency to the rms signal amplitude of a single harmonic component (second, third, and so on); reported in dBc. Integral Nonlinearity (INL) The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Maximum Conversion Rate The maximum encode rate at which parametric testing is performed. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio (PSRR) The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) Ratio The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral com- ponents, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo- nent may or may not be a harmonic. May be reported in dBc (degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone (f 1, f2) to the rms value of the worst third-order intermodulation product; reported in dBc. Products are located at 2f1 − f2 and 2f2 − f1. Two-Tone SFDR The ratio of the rms value of either input tone (f1, f2) to the rms value of the peak spurious component. The peak spurious com- ponent may or may not be an IMD product. May be reported in dBc (degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second-order and third-order harmonic); reported in dBc.
format is twos complement (see Table 6). Table 6. Twos Complement Output Coding (VREF = 2.5 V) The out-of-range (OR) output is logic low for normal operation. goes high. The OR output is internally generated each clock cycle. or −2048) while the OR output is high. decoupling capacitor at VREFIN. of the ADC tracks reference voltage changes linearly. dynamic performance of the converter. 10 clock cycles, whichever is longer.
Figure 32. 52-Lead Low Profile Quad Flat Package [LQFP]
12.00 BSC
7.30 BSC
0.08 MAX
Figure 33. 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] registered trademarks are the prop erty of their respective owners.