AD9430BSV-170

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Technical content

12-Bit, 170/210 MSPS

3.3 V A/D Converter

Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.

FEATURES

SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS ENOB of 10.6 @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS) SFDR = 80 dBc @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS) Excellent linearity: DNL = ±0.3 LSB (typical) INL = ±0.5 LSB (typical) 2 output data options: Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS Interleaved or parallel data output option LVDS at 210 MSPS

700 MHz full-power analog bandwidth

On-chip reference and track-and-hold Power dissipation = 1.3 W typical @ 210 MSPS

1.5 V input voltage range

3.3 V supply operation

Data sync input and data clock output provided Clock duty cycle stabilizer GENERAL DESCRIPTION The AD9430 is a 12-bit, monolithic, sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The product operates up to a 210 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The ADC requires a 3.3 V power supply and a differential ENCODE clock for full performance operation. The digital outputs are TTL/CMOS or LVDS compatible and support either twos complement or offset binary format. Separate output power supply pins support interfacing with 3.3 V CMOS logic. Two output buses support demultiplexed data up to 105 MSPS rates in CMOS mode. A data sync input is supported for proper output data port alignment in CMOS mode, and a data clock output is available for proper output data timing. In LVDS mode, the chip provides data at the ENCODE clock rate. Fabricated on an advanced BiCMOS process, the AD9430 is available in a 100-lead, surface-mount plastic package (100 e-PAD TQFP) specified over the industrial temperature range (–40°C to +85°C). FUNCTIONAL BLOCK DIAGRAM TRACK- AND-HOLD SCALABLE REFERENCE ADC 12-BIT PIPELINE CORE LVDS OUTPUTS CLOCK MANAGEMENT SENSE VREF AGND DRGND DRVDD AVDD DATA, OVERRANGE IN L VDS OR 2-PORT CMOS DCO– S5S4S2S1 CLK+ DS+ VIN+ AD9430 VIN– DS– CLK– DCO+SELECT CMOS OR L VDS CMOS OUTPUTS 02607-001 Figure 1.

APPLICATIONS

Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization PRODUCT HIGHLIGHTS 1. High performance. Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input. 2. Low power. Consumes only 1.3 W @ 210 MSPS. 3. Ease of use. LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 3.3 V supply simplifies system power supply design. 4. Out of range (OR) feature. The OR output bit indicates when the input signal is beyond the selected input range. 5. Pin compatible with 10-bit AD9411 (LVDS only).

AD9430* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Application Notes

• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• AN-302: Exploit Digital Advantages in an SSB Receiver
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-501: Aperture Uncertainty and ADC System Performance
• AN-586: LVDS Outputs for High Speed A/D Converters
• AN-616: AD9430 Evaluation Board Modifications for XTAL Oscillator Clocking
• AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-835: Understanding High Speed ADC Testing and Evaluation
• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

• AN-935: Designing an ADC Transformer-Coupled Front End Data Sheet
• AD9430: 12-Bit, 170/210 MSPS 3.3 V A/D Converter Data Sheet User Guides
• UG-173: High Speed ADC USB FIFO Evaluation Kit (HSC- ADC-EVALB-DCZ) TOOLS AND SIMULATIONS
• Visual Analog
• AD9430 IBIS Models REFERENCE MATERIALS Technical Articles
• Correlating High-Speed ADC Performance to Multicarrier 3G Requirements
• Design A Clock-Distribution Strategy With Confidence
• DNL and Some of its Effects on Converter Performance
• LVDS Ups A/D Converter Data Rates
• MS-2210: Designing Power Supplies for High Speed ADC DESIGN RESOURCES
• AD9430 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints DISCUSSIONS View all AD9430 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. E | Page 2 of 44 TABLE OF CONTENTS

Rev. E | Page 3 of 44

REVISION HISTORY

9/10—Rev. D to Rev. E Change to Operating Temperature Range Parameter, Table 5..10 8/05—Rev. C to Rev. D Change to I 11/04—Rev. B to Rev. C 7/03—Rev. A to Rev. B Add New AD9430 EV ALUATION BOARD, LVDS MODE 3/03—Rev. 0 to Rev. A 5/02—Revision 0: Initial Version

Rev. E | Page 4 of 44 DC SPECIFICATIONS AVDD = 3.3 V , DRVDD = 3.3 V , TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V , LVDS output mode, unless otherwise noted. Table 1. AD9430-170 AD9430-210 Parameter Temp Test Level Min Typ Max Min Typ Max Unit RESOLUTION 12 Bits ACCURACY No Missing Codes Full VI Guaranteed Guaranteed Offset Error 25°C I –3 +3 –3 +3 mV Gain Error 25°C I –5 +5 –5 +5 % FS Differential Nonlinearity (DNL) 25°C I –1 ± 0.3 +1 –1 ± 0.3 +1 LSB TEMPERATURE DRIFT Offset Error Full V 58 58 μV/°C Gain Error Full V 0.02 0.02 %/°C Reference Out (VREF) Full V +0.12/–0.24 +0.12/–0.24 mV/°C REFERENCE Output Current1 25°C IV 3.0 3.0 mA IVREF Input Current2 25°C I 20 20 μA ISENSE Input Current2 25°C I 1.6 5.0 1.6 5.0 mA ANALOG INPUTS (VIN+, VIN–)3 Differential Input Voltage Range (S5 = GND) Full V 1.536 1.536 V Differential Input Voltage Range (S5 = AVDD) Full V 0.766 0.766 V Input Resistance Full VI 2.2 3 3.8 2.2 3 3.8 kΩ Input Capacitance 25°C V 5 5 pF POWER SUPPLY (LVDS Mode) Supply Currents IANALOG (AVDD = 3.3 V)4 Full VI 335 372 390 450 mA IDIGITAL (DRVDD = 3.3 V)4 Full VI 55 62 55 62 mA Power Dissipation4 Full VI 1.29 1.43 1.5 1.7 W Power Supply Rejection 25°C V –7.5 –7.5 mV/V

Rev. E | Page 5 of 44 AD9430-170 AD9430-210 Parameter Temp Test Level Min Typ Max Min Typ Max Unit POWER SUPPLY (CMOS Mode) Supply Currents IAVDD (AVDD = 3.3 V)5 Full IV 335 372 390 450 mA IDRVDD (DRVDD = 3.3 V)5 Full IV 24 30 30 30 mA Power Dissipation5 Full IV 1.1 1.3 W Power Supply Rejection 25°C V –7.5 –7.5 mV/V 1 Internal reference mode; SENSE = Floats. 2 External reference mode; SENSE = DRVDD, VREF driven by external 1.23 V reference. 3 S5 (Pin 1) = GND. See the section. S5 = GND in all dc and ac tests, unless otherwise noted. Analog Input 4 IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated ENCODE rate, and in LVDS output mode. See Typical Performance Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in LVDS output mode. 5 IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated ENCODE rate, and in CMOS output mode. See Typical Performance Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in CMOS output mode.

Rev. E | Page 6 of 44 AC SPECIFICATIONS AVDD = 3.3 V , DRVDD = 3.3 V , TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V , LVDS output mode, unless otherwise noted.1 Table 2. AD9430-170 AD9430-210 Parameter Temp Test Level Min Typ Max Min Typ Max Unit SNR Analog Input @ –0.5 dBFS 10 MHz 25°C I 63.5 65 62.5 64.5 dB 70 MHz 25°C I 63 65 62.5 64.5 dB 100 MHz 25°C V 65 64.5 dB

240 MHz 25°C V 61 61 dB

Analog Input @ –0.5 dBFS 10 MHz 25°C I 63.5 65 62.5 64.5 dB 70 MHz 25°C I 63 65 62.5 64.5 dB 100 MHz 25°C V 65 64.5 dB

240 MHz 25°C V 60 60 dB

EFFECTIVE NUMBER OF BITS (ENOB) 10 MHz 25°C I 10.3 10.6 10.2 10.5 Bits 70 MHz 25°C I 10.3 10.6 10.2 10.5 Bits 100 MHz 25°C V 10.6 10.5 Bits 240 MHz 25°C V 9.8 9.8 Bits WORST HARMONIC (2nd or 3rd) Analog Input @ –0.5 dBFS, 10 MHz 10 MHz 25°C I –85 –75 –84 –74 dBc

70 MHz 25°C I –85 –75 –84 –74 dBc

100 MHz 25°C V –77 –77 dBc

240 MHz 25°C V –63 –63 dBc

WORST HARMONIC (4th or Higher) Analog Input @ –0.5 dBFS, 10 MHz 10 MHz 25°C I –87 –78 –87 –77 dBc

70 MHz 25°C I –87 –78 –87 –77 dBc

F1, F2 @ −7 dBFS 25°C V –75 –75 dBc ANALOG INPUT BANDWIDTH 25°C V 700 700 MHz 1 All ac specifications tested by differentially driving CLK+ and CLK−. 2 F1 = 28.3 MHz, F2 = 29.3 MHz.

Rev. E | Page 7 of 44 DIGITAL SPECIFICATIONS AVDD = 3.3 V , DRVDD = 3.3 V , TMIN = –40°C, TMAX = +85°C, unless otherwise noted. Table 3. Test AD9430-170 AD9430-210 Parameter Temp Level Min Typ Max Min Typ Max Unit ENCODE AND DS INPUTS (CLK+, CLK–, DS+, DS–)1 Differential Input Voltage2 Full IV 0.2 0.2 V Input Capacitance 25°C V 4 4 pF LOGIC INPUTS (S1, S2, S4, S5) Logic 1 Voltage Full IV 2.0 2.0 V Logic 0 Voltage Full IV 0.8 0.8 V Logic 1 Input Current Full VI 190 190 μA Logic 0 Input Current Full VI 10 10 μA Input Resistance 25°C V 30 30 kΩ Input Capacitance 25°C V 4 4 pF LOGIC OUTPUTS (CMOS Mode) Logic 1 Voltage4 Full IV DRVDD DRVDD V –0.05 –0.05 Logic 0 Voltage4 Full IV 0.05 0.05 V LOGIC OUTPUTS (LVDS Mode)4, 5 VOD Differential Output Voltage Full VI 247 454 247 454 mV VOS Output Offset Voltage Full VI 1.125 1.375 1.125 1.375 V Output Coding Twos complement or binary Twos complement or binary 1 ENCODE (Clock) and DS inputs identical on the chip. See the section. Equivalent Circuits 2 All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV. 3 ENCODE (Clock) inputs’ common-mode can be externally set, such that 0.9 V < (CLK+ or CLK−) < 2.6 V. 4 Digital output logic levels: DRVDD = 3.3 V, CLOAD = 5 pF. 5 LVDS RTERM = 100 Ω, LVDS output current set resistor (RSET) = 3.74 kΩ (1% tolerance).

Rev. E | Page 8 of 44 SWITCHING SPECIFICATIONS AVDD = 3.3 V , DRVDD = 3.3 V , TMIN = –40°C, TMAX = +85°C, unless otherwise noted. Table 4. Test AD9430-170 AD9430-210 Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit Maximum Conversion Rate1 Full VI 170 210 MSPS Minimum Conversion Rate1 Full V 40 40 MSPS CLK+ Pulse Width High (tEH)1 Full IV 2 12.5 2 12.5 ns CLK+ Pulse Width Low (tEL)1 Full IV 2 12.5 2 12.5 ns DS Input Setup Time (tSDS)2 Full IV –0.5 –0.5 ns DS Input Hold Time (tHDS)2 Full IV 1.75 1.75 ns OUTPUT (CMOS Mode) Valid Time (tV) Full IV 2 2 ns Propagation Delay (tPD) Full IV 3.8 5 3.8 5 ns Rise Time (tR) (20% to 80%) 25°C V 1 1 ns Fall Time (tF) (20% to 80%) 25°C V 1 1 ns DCO Propagation Delay (tCPD) Full IV 3.8 5 3.8 5 ns Data to DCO Skew (tPD to tCPD) Full IV –0.5 0 +0.5 –0.5 0 +0.5 ns Interleaved Mode (A, B Latency) Full IV 14, 14 14, 14 Cycles Parallel Mode (A, B Latency) Full IV 15, 14 15, 14 Cycles OUTPUT (LVDS Mode) Valid Time (tV) Full VI 2.0 2.0 ns Propagation Delay (tPD) Full VI 3.2 4.3 3.2 4.3 ns Rise Time (tR) (20% to 80%) 25°C V 0.5 0.5 ns Fall Time (tF) (20% to 80%) 25°C V 0.5 0.5 ns Latency Full IV 14 14 Cycles APERTURE DELAY (tA) 25°C V 1.2 1.2 ns APERTURE UNCERTAINTY (Jitter, tJ) 25°C V 0.25 0.25 ps rms OUT OF RANGE RECOVERY TIME (CMOS and LVDS) 25°C V 1 1 Cycles 1 All ac specifications tested by differentially driving CLK+ and CLK−. 2 DS inputs used in CMOS mode only.

14 CYCLES tPD tV

Figure 2. CMOS Timing Diagram

14 CYCLES

Figure 3. LVDS Timing Diagram

Rev. E | Page 10 of 44 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating AVDD, DRVDD 4 V Analog Inputs −0.5 V to AVDD + 0.5 V Digital Inputs −0.5 V to DRVDD + 0.5 V REFIN Inputs –0.5 V to AVDD + 0.5 V Digital Output Current 20 mA Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C θJA1 25°C/W, 32°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EXPLANATION OF TEST LEVELS Table 6. Level Description I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.

1 Typical θJA = 32°C/W (heat slug not soldered); typical θJA = 25°C/W (heat slug

soldered) for multilayer board in still air with solid ground plane. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrosta tic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge with out detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefor e, proper ESD precautions are re commended to avoid performance degradation or loss of functionality.

1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. Figure 4. CMOS Dual-Mode Pin Configuration Table 7. CMOS Mode Pin Function Descriptions GND sets fS = 1.536 V p-p differential. 3 S4 Interleaved, Parallel Select Pin. High = interleaved. 5 S2 Output Mode Select. Low = dual-port CMOS, high = LVDS. 10 SENSE Reference Mode Select Pin. Float for internal reference operation. 11 VREF 1.235 V Reference I/O—Function Dependent on SENSE. 22 VIN– Analog Input—Complement. 32 DS+ Data Sync (Input)—True. Tie low if not used. 33 DS–2 Data Sync (Input)—Complement. Tie high if not used.

Rev. E | Page 12 of 44 Pin Number Mnemonic Description 36 CLK+ Clock Input—True. 37 CLK– Clock Input—Complement. 44 DB0 B Port Output Data Bit (LSB). 45 DB1 B Port Output Data Bit. 46 DB2 B Port Output Data Bit. 47, 54, 62, 75, 83 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V). 48, 53, 61, 67, 74, 82 DRGND1 Digital Output Ground. 49 DB3 B Port Output Data Bit. 50 DB4 B Port Output Data Bit. 51 DB5 B Port Output Data Bit. 52 DB6 B Port Output Data Bit. 55 DB7 B Port Output Data Bit. 56 DB8 B Port Output Data Bit. 57 DB9 B Port Output Data Bit. 58 DB10 B Port Output Data Bit. 59 DB11 B Port Output Data Bit (MSB). 60 OR_B B Port Overrange. 63 DCO– Data Clock Output—Complement. 64 DCO+ Data Clock Output—True. 69 DA0 A Port Output Data Bit (LSB). 70 DA1 A Port Output Data Bit. 71 DA2 A Port Output Data Bit. 72 DA3 A Port Output Data Bit. 73 DA4 A Port Output Data Bit. 76 DA5 A Port Output Data Bit. 77 DA6 A Port Output Data Bit. 78 DA7 A Port Output Data Bit. 79 DA8 A Port Output Data Bit. 80 DA9 A Port Output Data Bit. 81 DA10 A Port Output Data Bit. 84 DA11 A Port Output Data Bit (MSB). 85 OR_A A Port Overrange. 1 AGND and DRGND should be tied together to a common ground plane. 2 DS Complement (DS−); can be tied to AVDD (as recommended) or left floating with no ill effects.

1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. Figure 5. LVDS Mode Pin Configuration Table 8. LVDS Mode Pin Function Descriptions GND sets fS = 1.536 V p-p differential. 2, 42 to 46 DNC Do Not Connect. 5 S2 Output Mode Select. GND = dual-port CMOS; AVDD = LVDS. 6 S1 Data Format Select. GND = binary, AVDD = twos complement. 11 VREF 1.235 V Reference I/O—Function Dependent on SENSE.

Rev. E | Page 14 of 44 Pin Number Mnemonic Description 22 VIN– Analog Input—Complement. 32 GND Data Sync (Input)—Not Used in LVDS Mode. Tie to GND. 36 CLK+ Clock Input—True (LVPECL Levels). 37 CLK– Clock Input—Complement (LVPECL Levels). 47, 54, 62, 75, 83 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V). 48, 53, 61, 67, 74, 82 DRGND1 Digital Output Ground. 49 D0– D0 Complement Output Bit (LSB). 50 D0+ D0 True Output Bit (LSB). 51 D1– D1 Complement Output Bit. 52 D1+ D1 True Output Bit. 55 D2– D2 Complement Output Bit. 56 D2+ D2 True Output Bit. 57 D3– D3 Complement Output Bit. 58 D3+ D3 True Output Bit. 59 D4– D4 Complement Output Bit. 60 D4+ D4 True Output Bit. 63 DCO– Data Clock Output—Complement. 64 DCO+ Data Clock Output—True. 65 D5– D5 Complement Output Bit. 66 D5+ D5 True Output Bit. 68 D6– D6 Complement Output Bit. 69 D6+ D6 True Output Bit. 70 D7– D7 Complement Output Bit. 71 D7+ D7 True Output Bit. 72 D8– D8 Complement Output Bit. 73 D8+ D8 True Output Bit. 76 D9– D9 Complement Output Bit. 77 D9+ D9 True Output Bit. 78 D10– D10 Complement Output Bit. 79 D10+ D10 True Output Bit. 80 D11– D11 Complement Output Bit. 81 D11+ D11 True Output Bit. 84 OR– Overrange Complement Output Bit. 85 OR+ Overrange True Output Bit. 1 AGND and DRGND should be tied together to a common ground plane.

2 Pin 33 can be tied to AVDD (as recommended) or left floating with no ill effects

Figure 30. IAVDD and IDRVDD vs. Clock Rate (AIN = 10.3 MHz @ –0.5 dBFS)

170 MSPS Grade, CLOAD = 5 pF

Figure 31. IAVDD and IDRVDD vs. Clock Rate Figure 32. SINAD and SFDR vs. Clock Pulse Width High Figure 33. SNR, SINAD, and SFDR vs. ENCODE Pulse Width High, Figure 34. VREFOUT vs. ILOAD Figure 35. Full-Scale Gain Error vs. Temperature

Figure 42. SFDR vs. AIN Input Level, AIN @ 10.3 MHz, 210 MSPS, Figure 43. SFDR vs. AIN Input Level, AIN @ 10.3 MHz, 210 MSPS, LVDS Mode, Figure 44. Noise Power Ratio Plot Figure 45. W-CDMA Four Channels Centered at 38.4 MHz, Figure 46. SNR, SINAD, and SFDR vs. Full-Scale Range, S5 = 0, Figure 47. Propagation Delay vs. Temperature, LVDS Mode,

170 MSPS/210 MSPS

Rev. E | Page 23 of 44 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Crosstalk Coupling onto one channel being driven by a low level (–40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the input phase 180° and again taking the peak measurement. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) Calculated from the measured SNR based on the equation 6.02 dB 1.76−= MEASUREDSNRENOB ENCODE Pulse Width/Duty Cycle Pulse width high is the minimum amount of time the ENCODE pulse (clock pulse) should be left in a Logic 1 state to achieve rated performance; pulse width low is the minimum time the ENCODE pulse should be left in a low state. See the timing implications of changing tEH in the Encode Input section. At a given clock rate, these specifications define an acceptable ENCODE duty cycle. Full-Scale Input Power Expressed in dBm. Computed using the following equation: 001 . 0 log 10 INPUT rmsSCALEFULL SCALEFULL Z V Power Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Minimum Conversion Rate The ENCODE rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The ENCODE rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK– and the time when all output data bits are within valid logic levels. Noise (for Any Range Within the ADC) Calculated as follows: ⎛ − −× × = 1010 001 . 0 dBFSdBcdBM NOISE SignalSNRFSZ V where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SNR is the value of the particular input level. Signal is the signal level within the ADC, reported in dB below full scale. This value includes input levels both thermal and quantization noise.

Rev. E | Page 24 of 44 Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Reported in dBc (degrades as signal level is lowered) or dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Reported in dBc (degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc. Transient Response Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

the clock is combined with the desired signal at the A/D output. give careful thought to the clock source. PECL device, the ac coupling is optional. Figure 50. Driving Clock Inputs with LVEL16 Table 9. Output Select Coding

1 X X X Twos complement

0 X X X Offset binary

2 S4 used in CMOS mode only (S2 = 0). S1 to S5 all have 30 kΩ resistive pull-downs on chip.

differential output trace lengths as equal as possible. Figure 54. Using an External Reference provides the required notch depth for testing. clock in LVDS mode switches at the ENCODE rate. pin for internal reference operation.

ADI ADC Analyzer software, allows for quick ADC evaluation.

• Offset binary
• Internal voltage reference
• CMOS parallel timing
• Full-scale adjust = low POWER CONNECTOR Power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks). AVDD, DRVDD, and VDL are the minimum required power connections.

Table 10. Power Connector, CMOS Mode driven differentially and minimizing even-order harmonics. (~1 dB to 2 dB) for high analog input frequencies (>100 MHz). If T2 is placed, two shorting traces at the pads need to be cut. sets S5 high, full scale = 0.75 V differential. low jitter, fast edge rates needed for optimum performance. the process and needs to be tuned for the specific application. shorting the SENSE pin to 3.3 V (place Jumper E26 to E25). EXT_VREF pin at the power connector. Data format select sets the output data format of the ADC. for interleaved timing mode. inverted by moving the appropriate jumper for that clock.

merchantability or fitness for a particular purpose. • Verify power at IC pins.

• Check that all jumpers are in the correct position for the desired mode of operation.
• Verify that VREF is at 1.23 V .
• Run the clock and analog inputs at low speeds (10 MSPS/ 1 MHz) and monitor latch and ADC for toggling. SIGNAL GENERATOR SIGNAL GENERATOR REFIN 10MHz REFOUT BAND-P ASS FILTER ANALOG CLOCK AD9430 EVALUATION BOARD AVDD GND DRVDDGND VDL GND 3.3V 3.3V 3.3V DATA CAPTURE AND PROCESSING 02607-059 –+ –+ –

Figure 58. Evaluation Board Connections

Table 11. CMOS PCB Evaluation Board Bill of Material

25.602.5453.0 Wieland

1 P3 and P23 are implemented as one physical 80-pin connector, the SAMTEC TSW-140-08-L-D-RA.

11 CLKLATB

11 CLKLATA

1. TO USE SINGLE ENDED ANALOG INPUT,

Figure 59. Evaluation Board Schematic—CMOS

Figure 60. Evaluation Board Schematic—CMOS (continued)

• Offset binary
• Internal voltage reference
• Full-scale adjust = low Note that the AD9430 LVDS evaluation board does not interface directly with the standard Analog Devices dual- channel data capture board (HSC-ADC-EV AL-DC). An LVDS- to-CMOS translation board is required and is available from Analog Devices. (No translation board is required for the AD9430 CMOS evaluation board.) POWER CONNECTOR Power is supplied to the board via a detachable 8-lead power strip (two 4-pin blocks). In Table 12, VCC, DRVDD, and VDL are the minimum required power connections, and the LVEL16 clock buffer can be powered from VCC or VDL at the E47 jumper.

Table 12. Power Connector, LVDS Mode be driven differentially and minimizing even-order harmonics. differential. Best performance is obtained at 1.5 V full scale. low jitter, fast edge rates needed for optimum performance. E46 powers the buffer from VCLK/V_XTAL (not in Table 11). the process and needs to be tuned for the specific application. shorting the SENSE pin to 3.3 V (place jumper E26 to E25). EXT_VREF pin at the power connector. Data format select (DFS) sets the output data format of the ADC. with a single 100 Ω resistor.

Table 13. LVDS PCB Evaluation Board Bill of Material

Figure 67. Evaluation Board Schematic—LVDS

Rev. E | Page 42 of 44 OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD 021809-A 26 50 76100

14.00 BSC SQ

16.00 BSC SQ

0.27 0.22 0.17

0.50 BSC

1.05 1.00 0.95 0.15 0.05 0.75 0.60 0.45 SEATING PLANE 1.20 MAX 2650 76 100 6.50 NOM7° 3.5° COPLANARITY 0.08 0.20 0.09 TOP VIEW (PINS DOWN) BOTTOM VIEW (PINS UP) CONDUCTIVE HEAT SINK PIN 1 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 76.100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-1) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9430BSV-170 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-100-1 AD9430BSVZ-170 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-100-1 AD9430BSV-210 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-100-1 AD9430BSVZ-210 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-100-1 1 Z = RoHS Compliant Part.

Rev. E | Page 43 of 44 NOTES

Rev. E | Page 44 of 44 NOTES ©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02607-0-9/10(E)