AD9410

AD9410 10-Bit, 210 MSPS ADC Converter Data Sheet (Rev. A)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 20

Technical content

10-Bit,

210 MSPS ADC

Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2007 Analog Devices, Inc. All rights reserved.

FEATURES

SNR = 54 dB with 99 MHz analog input

500 MHz analog bandwidth

On-chip reference and track and hold

1.5 V p-p differential analog input range

5.0 V and 3.3 V supply operation

3.3 V CMOS/TTL outputs

Power: 2.1 W typical at 210 MSPS Demultiplexed outputs each at 105 MSPS Output data format option Data sync input and data clock output provided Interleaved or parallel data output option

APPLICATIONS

Local multipoint distribution services (LMDS) High-end imaging systems and projectors Cable reverse paths Point-to-point radio links FUNCTIONAL BLOCK DIAGRAM T/H DS CLK– DS CLK+ DFS I/P REFERENCE DGNDAGND DCO DCO AD9410 10ADC 10-BIT CORE TIMING AND SYNCHRONIZATION PORT B PORT A REFIN REFOUT VD VDD VCC ORA DA9–DA0 ORB DB9–DB0 AIN AIN 01679-001 Figure 1. GENERAL DESCRIPTION The AD9410 is a 10-bit monolithic sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit and is optimized for high speed conversion and ease of use. The product operates at a 210 MSPS conversion rate, with outstanding dynamic performance over its full operating range. The ADC requires a 5.0 V and 3.3 V power supply and up to a 210 MHz differential clock input for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL-/CMOS-compatible and separate output power supply pins also support interfacing with 3.3 V logic. The clock input is differential and TTL-/CMOS-compatible. The 10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V) supplies. Two output buses support demultiplexed data up to 105 MSPS rates and binary or twos complement output coding format is available. A data sync function is provided for timing-dependent applications. An output clock simplifies interfacing to external logic. The output data bus timing is selectable for parallel or interleaved mode, allowing for flexibility in latching output data. Fabricated on an advanced BiCMOS process, the AD9410 is available in an 80-lead thin quad flat package, exposed pad specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. High Resolution at High Speed—The architecture is spe- cifically designed to support conversion up to 210 MSPS with outstanding dynamic performance. 2. Demultiplexed Output—Output data is decimated by two and provided on two data ports for ease of data transport. 3. Output Data Clock—The AD9410 provides an output data clock synchronous with the output data, simplifying the timing between data and other logic. 4. Data Synchronization—A DS input is provided to allow for synchronization of two or more AD9410s in a system, or to synchronize data to a specific output port in a single AD9410 system.

Rev. A | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

7/07—Rev. 0 to Rev. A Renamed Encode Input Section, Clock Input Section and Changes to Clock Input Section, Clock Outputs (DCO, DCO) 10/00—Revision 0: Initial Version

Rev. A | Page 3 of 20 SPECIFICATIONS DC SPECIFICATIONS Table 1. Parameter Temp Test Level Min Typ Max Unit RESOLUTION 10 Bits DC ACCURACY No Missing Codes Full IV Guaranteed Differential Nonlinearity 25°C I −1.0 ±0.5 +1.25 LSB Full VI −1.0 +1.5 LSB Integral Nonlinearity 25°C I −2.5 ±1.65 +2.5 LSB Full VI −3.0 +3.0 LSB Gain Error 25°C I −6.0 0 +6.0 % FS Gain Temperature Coefficient Full V 130 ppm/°C ANALOG INPUT Input Voltage Range (With Respect to AIN) Full V ±768 mV p-p Common-Mode Voltage Full V 3.0 V Input Offset Voltage 25°C I −15 +3 +15 mV Full VI −20 +20 mV Reference Voltage Full VI 2.4 2.5 2.6 V Reference Temperature Coefficient Full V 50 ppm/°C Input Resistance Full VI 610 875 1250 Ω Input Capacitance 25°C V 3 pF Analog Bandwidth, Full Power 25°C V 500 MHz POWER SUPPLY Power Dissipation AC1 25°C V 2.1 W Power Dissipation DC2 Full VI 2.0 2.4 W IVCC2 Full VI 128 145 mA IVD2 Full VI 401 480 mA Power Supply Rejection Ratio, PSRR 25°C I −7.5 +0.5 +7.5 mV/V 1 Clock input = 210 MSPS, AIN = –0.5 dBFS, 10 MHz sine wave, IVDD = 31 mA typical at CLOAD = 5 pF. 2 Clock input = 210 MSPS, AIN = dc, outputs not switching.

Rev. A | Page 4 of 20 SWITCHING SPECIFICATIONS Table 2. Parameter Temp Test Level Min Typ Max Unit SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 210 MSPS Minimum Conversion Rate Full IV 100 MSPS Clock Pulse Width High, tEH 25°C IV 1.2 2.4 ns Clock Pulse Width Low, tEL 25°C IV 1.2 2.4 ns Aperture Delay, tA 25°C V 1.0 ns Aperture Uncertainty (Jitter) 25°C V 0.65 ps rms Output Valid Time, tV Full VI 3.0 ns Output Propagation Delay, tPD Full VI 7.4 ns Output Rise Time, tR 25°C V 1.8 ns Output Fall Time, tF 25°C V 1.4 ns CLKOUT Propagation Delay, tCPD1 Full VI 2.6 4.8 6.4 ns Data to DCO Skew, (tPD – tCPD) Full IV 0 1 2 ns DS Setup Time, tSDS Full IV 0.5 ns DS Hold Time, tHDS Full IV 0 ns Interleaved Mode (A, B Latency) Full VI A = 6, B = 6 Cycles Parallel Mode (A, B Latency) Full VI A = 7, B = 6 Cycles 1 CLOAD = 5 pF. DIGITAL SPECIFICATIONS Table 3. Parameter Temp Test Level Min Typ Max Unit DIGITAL INPUTS DFS, Input Logic 1 Voltage Full IV 4 V DFS, Input Logic 0 Voltage Full IV 1 V DFS, Input Logic 1 Current Full V 50 μA DFS, Input Logic 0 Current Full V 50 μA I/P Input Logic 1 Current1 Full V 400 μA I/P Input Logic 0 Current1 Full V 1 μA CLK+, CLK− Differential Input Voltage Full IV 0.4 V CLK+, CLK− Differential Input Resistance Full V 1.6 kΩ CLK+, CLK− Common-Mode Input Voltage2 Full V 1.5 V DS, DS Differential Input Voltage Full IV 0.4 V DS, DS Common-Mode Input Voltage Full V 1.5 V Digital Input Pin Capacitance 25°C V 3 pF DIGITAL OUTPUTS Logic 1 Voltage (VDD = 3.3 V) Full VI VDD – 0.05 V Logic 0 Voltage (VDD = 3.3 V) Full VI 0.05 V Output Coding Binary or Twos Complement 1 I/P pin Logic 1 = 5 V, Logic 0 = GND. It is recommended to use a series 2.5 kΩ (±10%) resistor to VDD when setting to Logic 1 to limit input current. 2 See Clock Input section.

Rev. A | Page 5 of 20 AC SPECIFICATIONS Table 4. Parameter Temp Test Level Min Typ Max Unit DYNAMIC PERFORMANCE Transient Response 25°C V 2 ns Overvoltage Recovery Time 25°C V 2 ns Signal-to-Noise Ratio, SNR (Without Harmonics) fIN = 10.3 MHz 25°C I 52.5 55 dB fIN = 82 MHz 25°C I 52 54 dB fIN = 160 MHz 25°C V 53 dB Signal-to-Noise Ratio, SINAD (With Harmonics) fIN = 10.3 MHz 25°C I 51 54 dB fIN = 82 MHz 25°C I 50 53 dB fIN = 160 MHz 25°C V 52 dB Effective Number of Bits, ENOB fIN = 10.3 MHz 25°C I 8.3 8.8 Bits fIN = 82 MHz 25°C I 8.1 8.6 Bits fIN = 160 MHz 25°C V 8.4 Bits Second Harmonic Distortion fIN = 10.3 MHz 25°C I −56 −65 dBc fIN = 82 MHz 25°C I −55 −63 dBc fIN = 160 MHz 25°C V −65 dBc Third Harmonic Distortion fIN = 10.3 MHz 25°C I −58 −69 dBc fIN = 82 MHz 25°C I −57 −67 dBc fIN = 160 MHz 25°C V −62 dBc Spurious-Free Dynamic Range, SFDR fIN = 10.3 MHz 25°C I 56 61 dBc fIN = 82 MHz 25°C I 54 60 dBc fIN = 160 MHz 25°C V 58 dBc Two-Tone Intermod Distortion, IMD1 fIN1 = 80.3 MHz, fIN2 = 81.3 MHz 25°C V 58 dBFS 1 IN1, IN2 level = −7 dBFS.

Figure 2. Timing Diagram

Rev. A | Page 7 of 20 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating VD, VCC, VDD 6 V Analog Inputs 0 V to VCC + 0.5 V Digital Inputs 0 V to VDD + 0.5 V VREFIN 0 V to VD + 0.5 V Digital Output Current 20 mA Operating Temperature Range −55°C to +125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature1 150°C

1 Adequate dissipation of power from the AD9410 relies on all power and

ground pins of the device being soldered directly to a copper plane on a PCB. In addition, the thermally enhanced package of the AD9410BSVZ has an exposed paddle on the bottom that must be soldered to a large copper plane, which, for convenience, can be the ground plane. Sockets for package style of the AD9410 device are not recommended. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EXPLAINATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. IV . Parameter is guaranteed by design and characterization testing. V . Parameter is a typical value only. VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range. ESD CAUTION

Figure 3. Pin Configuration Table 6. Pin Function Descriptions 4 REFOUT Internal Reference Output. 5 REFIN Internal Reference Input. 11 AIN Analog Input—Complement. 19 CLK− Clock Input—Complement. 22 DS Data Sync (Input)—True. Tie low if not used. 23 DS Data Sync (Input)—Complement. Float and decouple with 0.1 μF capacitor if not used. 47 ORB Data Overrange for Channel B. 50 DCO Clock Output—Complement.

Rev. A | Page 9 of 20 Pin No. Mnemonic Function 51 DCO Clock Output—True. 54 to 58 DA0 to DA4 Digital Data Output for Channel A (LSB = DA0). 61 to 65 DA5 to DA9 Digital Data Output for Channel A (MSB = DA9). 66 ORA Data Overrange for Channel A. 79 DFS Data Format Select. High = twos complement, and low = binary. 80 I/P Interleaved or Parallel Output Mode. Low = parallel mode, and high = interleaved mode. If tying high, use a current limiting series resistor (2.5 kΩ) to the 5 V supply.

Rev. A | Page 10 of 20 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the clock command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180° and taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) ENOB is calculated from the measured SINAD based on the equation 02 . 6 log 20 76 . 1 ⎟⎟ + − AmplitudeInput AmplitudeScale FulldBSINAD ENOB MEASURED Clock Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time the clock pulse should be left in low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Full-Scale Input Power Expressed in dBm. Computed using the equation 001 . 0 log 10 INPUT FULLSCALE FULLSCALE Z VPOWER rms Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least-square curve fit. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The clock rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK− and the time when all output data bits are within valid logic levels. Out-of-Range Recovery Time Out-of-range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Noise (For Any Range Within the ADC) ⎛ −× × = 1010 001 . 0 | | dBFSdBm NOISE SIGNALFSZV where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SIGNAL is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise. Power Supply Rejection Ratio (PSRR) The ratio of a change in input offset voltage to a change in power supply voltage.

components, including harmonics, but excluding dc. components, excluding the first five harmonics and dc. (always related back to converter full scale). above negative full scale to 10% below positive full scale. related back to converter full scale). Table 7. Output Coding (VREF = 2.5 V)

Rev. A | Page 17 of 20 VOLTAGE REFERENCE A stable and accurate 2.5 V voltage reference is built into the AD9410 (VREFOUT). The input range can be adjusted by varying the reference voltage. No appreciable degradation in performance occurs when the reference is adjusted ±5%. The full-scale range of the ADC tracks reference voltage changes linearly within the ±5% tolerance. TIMING The AD9410 provides latched data outputs, with six pipeline delays in interleaved mode (see Figure 2). In parallel mode, the Port A has one additional cycle of latency added on-chip to line up transitions at the data ports, resulting in a latency of seven cycles for the Port A. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9410; these transients can detract from the dynamic performance of the converter. The minimum guaranteed conversion rate of the AD9410 is 100 MSPS. At internal clock rates below 100 MSPS, dynamic performance may degrade. Note that lower effective sampling rates can be obtained simply by sampling just one output port— decimating the output by two. Lower sampling frequencies can also be accommodated by restricting the duty cycle of the clock such that the clock high pulse width is a maximum of 5 ns. DATA SYNC (DS) The data sync input, DS, can be used in applications requiring that a given sample appear at a specific output Port A or Port B. When DS is held high, the ADC data outputs and clock do not switch and are held static. Synchronization is accomplished by the assertion (falling edge) of DS, within the timing constraints t SDS and tHDS relative to an clock rising edge. (On initial synchronization, tHDS is not relevant.) If DS falls within the required setup time (tSDS) before a given clock rising edge N, the analog value at that point is digitized and available at Port B six cycles later (interleaved mode). The next sample, N+1, is sampled by the next rising clock edge and available at Port A six cycles after that clock edge (interleaved mode). In dual parallel mode, Port A has a seven cycle latency, and Port B has a six cycle latency, but data is available at the same time.

Figure 29. PCB Schematic Example

0.08 MAX

0.65 BSC

9.50 SQEXPOSED

Figure 30. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

Rev. A | Page 20 of 20 NOTES ©2000–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01679-0-7/07(A)