AD9389

AD9389_15 AD | Alldatasheet

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Technical content

800 MHz High Performance

HDMI™/DVI Transmitter AD9389 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

HDMI/DVI transmitter compatible with HDMI 1.1 and HDCP 1.1 Single 1.8 V power supply Video/audio inputs are 3.3 V tolerant Supports HDCP 1.1 with encrypted internal HDCP key st orage 80-lead LQFP Digital video

80 MHz operation supports all video formats from 480i to

Programmable 2-way color space converter Supports RGB, YCbCr, DDR, ITU656 formats Auto input video format detection Digital audio Supports standard S/PDIF for stereo or compressed audio up to 192 kHz 8-channel LPCM I2S audio up to 192 kHz Special features for easy system design On-chip MPU to perform HDCP operations On-chip I 2C® master to handle EDID reading

5 V tolerant I2C and MPD I/Os, no extra device needed

No audio master clock needed for S/PDIF support

APPLICATIONS

Digital cameras and camcorders FUNCTIONAL BLOCK DIAGRAM REGISTER CONFIGURATION LOGIC SDA CLK VSYNC HSYNC DE D[23:0] S/PDIF MCLK HTPG SCL Tx0[1:0] Tx1[1:0] Tx2[1:0] TxC[1:0] SWING_ADJ I2S[3:0] DDSDA DDCSCL COLOR SPACE CONVERSION 4:2:2 TO 4:4:4 CONVERSION VIDEO DATA CAPTURE I2C MASTER I2C SLAVE HDCP CONTROLLER HDCP CIPHER HDM ITX CORE XOR MASK AUDIO DATA CAPTURE AD9389 05724-001 Figure 1. GENERAL DESCRIPTION The AD9389 is an 80 MHz high-definition multimedia inter- face (HDMI 1.1) transmitter. It supports HDTV formats up to 1080i and 720p, and graphic resolutions up to XGA (1024 × 768 @ 75 Hz). With the inclusion of HDCP , the AD9389 allows the secure transmission of protected content as specified by the HDCP 1.1 protocol. The AD9389 supports both S/PDIF and 8-channel I 2S audio. Its high fidelity 8-channel I2S can transmit either stereo or 7.1 surround audio at 192 kHz. The S/PDIF can carry stereo LPCM (linear pulse code modulation) audio or compressed audio including Dolby® Digital, DTS®, and THX®. The AD9389 helps to reduce system design complexity and cost b y incorporating such features as HDCP master, I2C master for EDID reading, a single 1.8 V power supply, and 5 V tolerance on I2C and hot plug detect pins. Fabricated in an advanced CMOS process, the AD9389 is pro- vid ed in a space-saving, 80-lead, surface-mount, Pb-free plastic LQFP and is specified over the 0°C to 70°C temperature range. EVALUATION KITS AND OTHER RESOURCES Evaluation kits, reference design schematics, software quick start guide, and codes are available from the Analog Devices local sales and marketing personnel. OBSOLETE

Rev. 0 | Page 2 of 48 TABLE OF CONTENTS

REVISION HISTORY

1/06—Revision 0: Initial Version OBSOLETE

Rev. 0 | Page 3 of 48 ELECTRICAL SPECIFICATIONS Table 1. Parameter Temp Test Le vel 1 Min Typ Max Unit DIGITAL INPUTS Input Voltage, High (VIH) Full VI 1.4 V Input Voltage, Low (VIL) Full VI 0.7 V Input Current, High (VIH) Full V −1.0 mA Input Current, Low (VIL) Full V +1.0 mA Input Capacitance 25°C V 3 pF DIGITAL OUTPUTS Output Voltage, High (VOH) Full VI AVDD − 0.1 V Output Voltage, Low (VOL) Full VI 0.4 V THERMAL CHARACTERISTICS θJC Junction-to-Case Thermal Resistance V 25 °C/W θJA Junction-to-Ambient Thermal Resistance V 30 °C/W Ambient Temperature Full V 0 25 70 °C DC SPECIFICATIONS Input Leakage Current, IIL 25°C VI −10 +10 μA Input Clamp Voltage (−16 mA) 25°C V −0.8 V Input Clamp Voltage (+16 mA) 25°C V +0.8 Differential High Level Output Voltage V AVCC V Differential Output Short-Circuit Current V 10 μA POWER SUPPLY VDD (All) Supply Voltage Full IV 1.71 1.8 1.89 V VDD Supply Voltage Noise Full V 50 mV p-p Complete Power-Down Current (Everything Except I2C) 25°C IV 6 13 mA Quiet Power Down Current (Monitor Detect On) 25°C VI 7 mA Transmitter Supply Current (27 MHz Typical Random Pattern) 25°C VI 165 mA Transmitter Supply Current (80 MHz Typical Random Pattern) 25°C IV 185 205 mA Transmitter Total Power (80 MHz Single Pixel Stripe Pattern; Worst Case Operating Conditions) Full VI 430 mW AC SPECIFICATIONS CLK Frequency 25°C IV 13.5 80 MHz CLK Duty Cycle 25°C VII 40 60 % Worst Case CLK Input Jitter Full VI 1.0 ns Setup Time to CLK Falling Edge VI TBD TBD ns Hold Time to CLK Falling Edge VI TBD TBD ns TMDS Differential Swing VII 800 1000 1200 mV VSYNC and HSYNC Delay from DE Falling Edge VI 1 UI VSYNC and HSYNC Delay to DE Rising Edge VI 1 UI DE High Time 25°C VI 8191 UI DE Low Time 25°C VI 138 UI Differential Output Swing Low-to-High Transition Time 25°C VII 75 490 ps Differential Swing Output High-to-Low Transition Time 25°C VII 75 490 ps OBSOLETE

Rev. 0 | Page 4 of 48 Parameter Temp Test Level1 Min Typ Max Unit AUDIO AC TIMING Sample Rate (I2S and S/PDIF) Full IV 32 192 kHz I2S Cycle Time 25°C IV 1 UI I2S Setup Time 25°C IV 15 ns I2S Hold Time 25°C IV 0 ns Audio Pipeline Delay 25°C IV 75 μs 1 See Table 3. OBSOLETE

Rev. 0 | Page 5 of 48 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Digital Inputs 5 V to 0.0 V Digital Output Current 20 mA Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EXPLANATION OF TEST LEVELS Table 3. Level Test I 100% production tested. II 100% production tested at 25°C and sample tested at specified tempe ratures. III Sample tested only. IV Parameter is guaranteed by design and characterization test ing. V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and charac terization testing. VII Limits defined by HDMI specification. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD pr ecautions are recommended to avoid performance degradation or loss of functionality. OBSOLETE

51 D22

47 SDA

46 SCL

45 DDSDA

44 DDCSCL

43 GND

42 GND

41 AVDD

50 D23

Figure 2. Pin Configuration Table 4. Complete Pinout List

NO CONNECT 48, 49 NC No Connect. Table 5. Pin Function Descriptions TxC+ Differential Clock Output at Pixel Clock Rate; T ransition Minimized Differential Signaling (TMDS). TxC− Differential Clock Output Complement. Tx2+ Differential Output of the Red Data a t 10× the Pixel Clock Rate; TMDS. Tx2− Differential Red Output Complement. Tx1+ Differential Output of the Green Data a t 10× the Pixel Clock Rate; TMDS. Tx1− Differential Green Output Complement. Tx0+ Differential Output of the Blue Data a t 10× the Pixel Clock Rate; TMDS. Tx0− Differential Blue Output Complement. DDSDA Serial Port Data I/O Master to Receiver. DDCSCL Serial Port Data Clock Master to Receiver. For a full, functional description of the 2-wire serial register, refer to the 2-Wire Serial Control Port section. D[23:0] Digital Input in RGB or YCbCr Format. DE Data Enable for Video Data. HSYNC Horizontal S ync Input. VSYNC Vertical Sync Input. This is the input for vertical sync. EXT_SW Place an 887 Ω resistor (1% tolerance) between this pin and ground. HPD Hot Plug Detect. This indicates to the interface whether the receiver is connected. S/PDIF S/PDIF Audio Input. This is the audio input from a Sony/Philips Digital Interface. MCLK Audio Reference Clock. Can be set from 128 × fS to 512 × fS. I2S[3:0] I 2S Audio Inputs. These represent the eight channels of audio (two per input) available through I2S. LRCLK Left/Right Channel Selection.

Rev. 0 | Page 8 of 48 Pin Mnemonic Description POWER SUPPLY DVDD Main Power Supply. These pins supply power to the main elements of the circuit. They should be filtered and as quiet as possible. AVDD Output Power Supply. PVDD Clock Generator Power Supply. The most sensitive portion of the AD9389 is the clock generation circuitry. These pins provide power to the clock PLL (phase-locked loop) and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins. GND Ground. The ground return for all circuitry on-chip. It is recommended that the AD9389 be assembled on a single solid ground plane, with careful attention given to ground current paths. I2C ADDRESSES The SDA/SCL programming address can be 0x72 or 0x7A based on whether the PD/A0 pin is pulled high (10 kΩ resistor = 0x7A) or pulled low (10 kΩ resistor = 0x72). The EDID EEPROM on the receiver is expected to have an address of 0xA0. LIST OF REFERENCE DOCUMENTS Table 6. Document Description EIA/CEA-861B Describes audio and video infoframes as well as the E-EDID structure for HDMI. ITU-R BT.656-3 Defining document for BT656. FORMAT STANDARDS In this document, data is represented in a variety of ways. Table 7. Data Type Format 0xNN Hexadecimal (base-16) numbers are represented using the C language nota tion, preceded by 0x. 0bNN Binary (base-2) numbers are represented using the C language notation, preceded by 0b. NN Decimal (base-10) numbers are represented using no additional prefixes or suffixes. Bit Bits are numbered in little-endian format, tha t is, the least significant bit (LSB) of a byte or word is referred to as Bit 0. OBSOLETE

protection for the data to be transmitted. and one of 16:9, 0x17[1] should be set accordingly. Table 8. Input Formats Supported

12 RGB (DDR)

12 YCbCr 4:4:4 (DDR)

24 RGB 4:4:4

24 YCbCr 4:4:4

8 YCbCr (DDR)

10 YCbCr (DDR)

12 YCbCr (DDR)

Table 9. Output Formats Supported

16 YCbCr 4:2:2

20 YCbCr 4:2:2

24 YCbCr 4:2:2

Figure 3. Timing for Data Input

Rev. 0 | Page 10 of 48 Normal 4:4:4 Input Format (RGB or YCbCr) Input ID = 0 An input format of RGB 4:4:4 or YCbCr 4:4:4 can be selected by setting the input ID (0x15[3:1]) to 0b000. The input color space (CS) must be selected by setting 0x16[0] to 0b0 for RGB or 0b1 for YCbCr. There is no need to set the input style (0x16[3:2]). Table 10. Data[23:0] Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 YCbCr 4:4:4 Cr[7:0] Y[7:0] Cb[7:0] YCbCr 4:2:2 Formats (24 bits, 20 bits, or 16 bits) with Separate Sync, Input ID = 1 An input with YCbCr 4:2:2 with separate syncs can be selected by setting the Input ID (0x15[3:1]) to 0b001. The input CS (0x16[0]) must be set to 0b1 for proper operation. The data bit width (24 bits, 20 bits, or 16 bits) must be set with 0x16[5:4]. The three input pin assignment styles are shown in Table 11. The input style can be set in 0x16[3:2]. Table 11. Data[23:0] Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Style 1 YCbCr 4:2:2 Sep. Cb[11:4] Y[11:4] Cb[3:0] Y[3:0] Sync (24 bit) Cr[11:4] Y[11:4] Cr[3:0] Y[3:0] YCbCr 4:2:2 Sep. Cb[9:2] Y[9:2] Cb[1:0] Y[1:0] Sync (20 bit) Cr[9:2] Y[9:2] Cr[1:0] Y[1:0] YCbCr 4:2:2 Sep. Cb[7:0] Y[7:0] Sync (20 bit) Cr[7:0] Y[7:0] Style 2 24-bit Cb[11:0] Y[11:0] Cr[11:0] Y[11:0] 20-bit Cb[9:0] Y[9:0] Cr[9:0] Y[9:0] 16-bit Cb[7:0] Y[7:0] Cr[7:0] Y[7:0] Style 3 24-bit Y[11:0] Cb[11:0] Y[11:0] Cr[11:0] 20-bit Y[9:0] Cb[9:0] Y[9:0] Cr[9:0] 16-bit Y[7:0] Cb[7:0] Y[7:0] Cr[7:0] OBSOLETE

Rev. 0 | Page 11 of 48 YCbCr 4:2:2 Formats (24 bits, 20 bits, or 16 bits) with Embedded Syncs, Input ID = 2 An input with YCbCr 4:2:2 with embedded syncs can be selected by setting the input ID (0x15[3:1]) to 0b010. HSYNC and VSYNC are embedded as Start of Active Video (SAV) and End of Active Video (EAV). The input CS (0x16[0]) must be set to 0b1 for proper operation. The data bit width (24 = 12 bits, 20 = 10 bits, or 16 = 8 bits) must be set with 0x16[5:4]. The three input pin assignment styles are shown in Table 12. The input style can be set in 0x16[3:2]. The only difference between Input ID 1 and Input ID 2 is that the syncs on ID 2 a re embedded in the data much like ITU 656 running at 1× clock and double width. Table 12. Data[23:0] Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Style 1 YCbCr 4:2:2 Sep. Cb[11:4] Y[11:4] Cb[3:0] Y[3:0] Sync (24 bit) Cr[11:4] Y[11:4] Cr[3:0] Y[3:0] YCbCr 4:2:2 Sep. Cb[9:2] Y[9:2] Cb[1:0] Y[1:0] Sync (20 bit) Cr[9:2] Y[9:2] Cr[1:0] Y[1:0] YCbCr 4:2:2 Sep. Cb[7:0] Y[7:0] Sync (16 bit) Cr[7:0] Y[7:0] Style 2 24-bit Cb[11:0] Y[11:0] Cr[11:0] Y[11:0] 20-bit Cb[9:0] Y[9:0] Cr[9:0] Y[9:0] 16-bit Cb[7:0] Y[7:0] Cr[7:0] Y[7:0] Style 3 24-bit Y[11:0] Cb[11:0] Y[11:0] Cr[11:0] 20-bit Y[9:0] Cb[9:0] Y[9:0] Cr[9:0] 16-bit Y[7:0] Cb[7:0] Y[7:0] Cr[7:0] YCbCr 4:2:2 Formats (Double Data Rate) Formats (12 bits, 10 bits, or 8 bits) with Separate Syncs, Input ID = 3 An input with YCbCr 4:2:2 DDR data and separate syncs can be selected by setting the input ID (0x15[3:1]) to 0b011. The Input CS (0x16 [0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with 0x16[5:4]. The two input pin assignment styles are shown in Table 13. The input style can be set in 0x16[3:2]. Table 13. Data[23:0] Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Style 1 12-bit Cb/Y/Cr/Y[11:4] [3:0] 10-bit Cb/Y/Cr/Y[9:2] [1:0] 8-bit Cb/Y/Cr/Y[7:0] Style 2 1 2 - b i t C b / Y / C r / Y [ 1 1 : 0 ] 1 0 - b i t C b / Y / C r / Y [ 9 : 0 ] 8 - b i t C b / Y / C r / Y [ 7 : 0 ] OBSOLETE

Rev. 0 | Page 12 of 48 YCbCr 4:2:2 DDR (Double Data Rate) Formats (12 bits, 10 bits, or 8 bits) with Embedded Syncs, Input ID = 4 An input with YCbCr 4:2:2 DDR data and embedded syncs (ITU 656) can be selected by setting the input ID (0x15[3:1]) to 0b100. The Input CS (0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with 0x16[5:4]. The two input pin assignment styles are shown in Table 14. The input style can be set in 0x16[3:2]. The order o f data input is the order in the table (for example, 12 bit data is accepted as: Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3). Table 14. Data[23:0] Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Style 1 12-bit Cb/Y/Cr/Y[11:4] [3:0] 10-bit Cb/Y/Cr/Y[9:2] [1:0] 8-bit Cb/Y/Cr/Y[7:0] Style 2 1 2 - b i t C b / Y / C r / Y [ 1 1 : 0 ] 1 0 - b i t C b / Y / C r / Y [ 9 : 0 ] 8 - b i t C b / Y / C r / Y [ 7 : 0 ] Normal 4:4:4 Input Format (RGB or YCbCr) Clocked at Double Data Rate (DDR), Input ID = 5 An input with YCbCr 4:4:4 DDR data and separate syncs can be selected by setting the input ID (0x15[3:1]) to 0b011. The input CS (0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with 0x16[5:4]. The three input pin assignment styles are shown in Table 15. The input style can be set in 0x16[3:2]. Table 15. Data[23:0] Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Style 1 (1 st edge, 2 nd edge) R [ 7 : 0 ] G [ 7 : 4 ] Y [ 3 : 0 ] C b [ 7 : 0 ] YCbCr 4:4:4 (DDR) (1 st edge, 2 nd edge) C r [ 7 : 0 ] Y [ 7 : 4 ] Style 2 (1 st edge, 2 nd edge) G [ 3 : 0 ] B [ 7 : 0 ] C r [ 7 : 0 ] Y [ 7 : 4 ] YCbCr 4:4:4 (DDR) st edge, 2 nd edge) Y [ 3 : 0 ] C b [ 7 : 0 ] Style 3 Y [ 7 : 0 ] C b [ 7 : 4 ] YCbCr 4:4:4 (DDR) (1 st edge, 2 nd edge) C b [ 3 : 0 ] C r [ 7 : 0 ] OBSOLETE

Rev. 0 | Page 13 of 48 YCbCr 4:2:2 Formats (24 bits, 20 bits, or 16 bits) DDR with Separate Sync, Input ID = 6 An input format of YCbCr 4:2:2 DDR can be selected by setting the input ID (0x15[3:1]) to 0b110. The three different input pin assignment styles are shown in Table 16. The input style can be set in 0x16[3:2]. The input CS (0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set to with 0x16[5:4]. The 1st or the 2nd edge can be the rising or falling edge. The data input edge is defined in 0x16[1]. 0b0 = rising edge; 0b1 = falling edge. Pixel 0 is the first pixel of the 4:2:2 word and should be where DE starts. Table 16. Data[23:0] Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Style 1 1st Edge Y[7:4] Cb[3:0] Y[3:0] 1st Pixel 2nd Edge Cb[11:4] Y[11:8] YCbCr 4:2:2 Sep. Syncs (DDR) 12-bit 2nd Pixel Cr[11:4] Y[11:8] C b [ 9 : 4 ] Y [ 9 : 6 ] YCbCr 4:2:2 Sep. Syncs (DDR) 10-bit C r [ 9 : 4 ] Y [ 9 : 6 ] C b [ 3 : 0 ] Y [ 3 : 0 ] C b [ 7 : 4 ] Y [ 7 : 4 ] C r [ 3 : 0 ] Y [ 3 : 0 ] YCbCr 4:2:2 Sep. Syncs (DDR) 8-bit C r [ 7 : 4 ] Y [ 7 : 4 ] Style 2 Y [ 1 1 : 0 ] C b [ 1 1 : 0 ] Y [ 1 1 : 0 ] 12-bit C r [ 1 1 : 0 ] Y [ 9 : 0 ] C b [ 9 : 0 ] Y [ 9 : 0 ] 10-bit C r [ 9 : 0 ] Y [ 7 : 0 ] C b [ 7 : 0 ] Y [ 7 : 0 ] 8-bit C r [ 7 : 0 ] Style 3 C b [ 1 1 : 0 ] Y [ 1 1 : 0 ] C r [ 1 1 : 0 ] 12-bit Y [ 1 1 : 0 ] C b [ 9 : 0 ] Y [ 9 : 0 ] C r [ 9 : 0 ] 10-bit Y [ 9 : 0 ] C b [ 7 : 0 ] Y [ 7 : 0 ] C r [ 7 : 0 ] 8-bit Y [ 7 : 0 ] OBSOLETE

recommended optimal value of 128 × fS/1000 Hz equals N. Table 18. Recommended N and Expected CTS Values for 1 This value alternates because of the restriction on N. Table 19. Recommended N and Expected CTS Values for 44.1 kHz Audio and Multiples Table 20. Recommended N and Expected CTS Values for 48 kHz Audio and Multiples

computes the CTS based on the actual audio and video rates. AD9389 in Register 0x01 to Register 0x03. clear or reset the bits to avoid system lock-up. 4× in order to maintain the minimum TMDS clock frequency. function: auto mode, manual mode, and max mode (0x3B[6:5]). repetition factor (0x3D[7:6]). epetition factor in 0x3B[4:3]. Table 21. Pixel Repetition—Valid Pixel Re peat Values for Each Format 1 Denotes change from EIA/CEA-861B valid values. Pixel repetition is required to support some audio formats at 720 × 480p and 720 × 576p video format timings.

Rev. 0 | Page 19 of 48 HDCP HANDLING The AD9389 has a built-in microcontroller to handle HDCP transmitter states, including handling downstream HDCP repeaters. To activate HDCP from a system level, the main controller needs to set 0xAF[7] to 1 to inform AD9389 that the video stream should be encrypted. The AD9389 takes control from there, and implements all remaining tasks defined by the HDCP 1.1 specification. The system controller should monitor the status of HDCP by r eading Register 0xB8[6] (indicating the HDCP link has been established). There are also some error flags (0xC5[7] and 0xC8[7:4]) to help debug the system. The AD9389 also supports AV functions to suspend HDCP t emporarily. To set AV mute, clear 0x45[7] and set 0x45[6] to 1. To clear AV mute, clear 0x45[6] and set 0x45[7] to 1. (Note that it is invalid to set the two mute bits at the same time.) For more information, refer to application note AN-810, EDID a nd HDCP Controller User Guide for the AD9889. EDID READING The AD9389 has an I2C master (DDC Pin 44 and Pin 45) to read the EDID based on system need. It buffers segment 0 once HPD is detected. The system can request other segments by programming Register 0xC4. An interrupt bit (0x96[2]) indicates the completion of EDID rebuffering. To read the EDID data from the AD9389, use the AD9389 p rogramming bus (Pin 46 and Pin 47) with I2C Address 0x7E. This is the default address but can be changed by writing the desired address into Register 0x43. For more information, refer to Application Note AN-810, ED ID and HDCP Controller User Guide for the AD9889. INTERRUPTS The AD9389 has interrupts to help with the system design: hot plug detection, receiver sense, VS detection, audio FIFO overflow, ITU 656 error, EDID ready, HDCP error, and BKSV ready. Interrupts can be cleared by writing 1 into the interrupt register (0x96, 0x97). There are read-only registers (0xC5, 0xC6) to show the state of these signals. Masks (0x94, 0x95) are available to let the user selectively activate each interrupt. To enable a specific interrupt register, write 1 to the corresponding mask bit. POWER MANAGEMENT The AD9389 power-down pin polarity depends on the AD9389’s I2C address selection. To use 0x72, the PD pin is high active. To use 0x7A, the PD pin is low active. The power-down pin polarity can be verified by reading Register 0x42[7]. The AD9389 can be powered down or reset either by Pin 33 or b y Register 0x41[6]. During power-down mode, all the circuits are inactive except the I2C slave and some circuits related to mode and activity detection. During power-down mode, the chip status can still be read through the I2C slave. To enter normal power-down mode, either drive Pin 33 to 1, or set 0x41[6] to 1. To further reduce power consumption, disable the receiver sense detection by setting Register 0xA4[2] to 1. For HDCP security reasons, the I 2C power-down bit is also reset by the power-down pin. Anytime after power down, the user needs to drive the PD pin back to 0, and set 0x41[6] to 0 to activate the chip. OBSOLETE

Rev. 0 | Page 20 of 48 2-WIRE SERIAL REGISTER MAP The AD9389 is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to write and read the control registers through the two-line serial interface port. Table 22. Control Register Map

Description

0x00 Read [7:0] 00000000 Chip Revision Revision of the chip, start from 0. 0x01 Read/Write [3:0] **0000 N[19:16] 20-bit N used with cycle time stamp (CTS) (see Table 18 to Table 20 for appropriate settings) to regenerate the audio clock i n the receiver. For remaining bits, see 0x02 and 0x03. Used only with I2S audio, not S/PDIF . 0x02 Read/Write [7:0] 00000000 N[15:8] The middle byte of N. 0x03 Read/Write [7:0] 00000000 N[7:0] The lower byte of N. [7:4] 0000 S/PDIF_SF S/PDIF sampling frequency for S/PDIF audio decoded fr om hardware. This information is used both by the audio Rx and the pixel repetition. 0011 = 32 kHz. 0000 = 44.1 kH 0010 = 48 kHz. 1000 = 88.2 kHz. 1010 = 96 kHz. 1100 = 176.4 kHz. 1110 = 192 kHz. Default = 0x0. 0x04 Read [3:0] 0000 CTS_Int[19:16] CTS measured (internal). This 20-bit value is used in the r eceiver with the N value to regenerate an audio clock. For remaining bits, see 0x05 and 0x06. 0x05 Read [7:0] 00000000 CTS_Int[15:8] Middle byte of measured CTS. 0x06 Read [7:0] 00000000 CTS_Int[7:0] Low byte of measured CTS. 0x07 Read/Write [3:0] **0000 CTS_Ext[19:16] CTS (external). This 20-bit value is used in the receiver with the N v alue to regenerate an audio clock. For remaining bits, see 0x08 and 0x09. 0x08 Read/Write [7:0] 00000000 CTS_Ext[15:8] Middle byte of external CTS. 0x09 Read/Write [7:0] 00000000 CTS_Ext[7:0] Low byte of external CTS. 0 = internal CTS. 1 = ex ternal CTS. Default = 0. [6:5] *10*** Avg_Mode CTS filter mode. 00 = no filter. 01 = divide b y 4. 10 = divide by 8. 11 = divide by16. Default = 10. [4] *0** Audio_Sel Audio type select. 0 = I2S. 1 = S/PDIF. Default = 0. 1 = MCLK active. 0 = MCLK inac tive. Default = 0. 1 = I2S MCLK active. 0 = I2S MCLK inactive. Default = 0. 0x0A Read/Write [1:0] ****01 MCLK_Ratio MCLK ratio. OBSOLETE

Rev. 0 | Page 21 of 48 Hex Address Read/Write or Read Only Bits Default Value Register Name 00 = × 128 fS. 01 = × 256 fS. 10 = × 384 fS. 11 = × 512 fS. Default = 01. 0 = rising edge. 1 = falling ed ge. Default = 0. 0x0B Read/Write 1 = flat line audio (audio sample not valid). 0 = nor mal. Default = 0. [4:0] **0111 Test bits Must be set to 0x7 for proper operation. [5:2] 1111 I2S enable I2S enable for the four I2S pins (active). 0001 = I2S0. 0010 = I2S1. 0100 = I2S2. 1000 = I2S3. Default = 1111 for all. 0x0C Read/Write [1:0] **00 I2S Format I2S format. 00 = standard I2S mode. 01 = right-justified I2S mode. 10 = left-justified I2S mode. 11 = raw IEC60958 mode. Default = 0. 0x0D Read/Write [4:0] *11000 I2S_bit_width I2S bit width. For right justified audio only. Default is 24. Not valid for widths greater than 24. [5:3] 000* SUBPKT0_L_src Registers 0x0E to 0x11 should be set based on the speaker mapping information obtained from EDID. Source of sub packet 0, left channel. Default = 000. 0x0E Read/Write [2:0] ***001 SUBPKT0_R_src Source of sub packet 0, right channel. Default = 001. [5:3] 010* SUBPKT1_L_src Source of sub packet 1, left channel. Default = 010. 0x0F Read/Write [2:0] *011 SUBPKT1_R_src Source of sub packet 1, right channel. Default = 011. [5:3] 100* SUBPKT2_L_src Source of sub packet 2, left channel. Default = 100. 0x10 Read/Write [2:0] *101 SUBPKT2_R_src Source of sub packet 2, right channel. Default = 101. [5:3] 110* SUBPKT3_L_src Source of sub packet 3, left channel. Default = 110. 0x11 Read/Write [2:0] *111 SUBPKT3_R_src Source of sub packet 3, right channel. Default = 111. 0 = copyright. 1 = not c opyright protected. [4:2] *000 a_info Additional information for channel status bits. 000 = 2 audio channe ls without pre-emphasis. 100 = 2 audio channels with 50/15 μs pre-emphasis. 010 = reserved. 110 = reserved. Default = 000. 0x12 Read/Write [1:0] ****00 Clk_Acc Clock accuracy. 00 = Level II, normal accuracy ±1000 × 10−6. 01 = Level III, variable pitch shifted clock. 10 = Level I, high accuracy ±50 × 10 −6. 11 = reserved. Default = 00. 0x13 Read/Write [7:0] 00000000 Category Code Category code for audio infoframe; see IEC 60958. OBSOLETE

Rev. 0 | Page 22 of 48 Hex Address Read/Write or Read Only Bits Default Value Register Name [7:4] 0000** Source Number Source number. 0x14 Read/Write [3:0] 0000 Word Length Audio word length. 0000 = not specified. 0100 = 16 bits 0011 = 17 bits. 0010 = 18 bits. 0001 = 19 bits. 0101 = 20 bits. 1000 = not specified. 1100 = 20 bits. 1011 = 21 bits. 1010 = 22 bits. 1001 = 23 bits. 1101 = 24 bits. Default = 0x0. [7:4] 0000 I2S_SF Sampling frequency for I2S audio. This information is used both by the audio Rx and the pixel repetition. 0011 = 32 kHz. 0000 = 44.1 kH 0010 = 48 kHz. 1000 = 88.2 kHz. 1010 = 96 kHz. 1100 = 176.4 kHz. 1110 = 192 kHz. Default = 0x0. [3:1] **000* VFE_input_id Input video format. 000 = RGB and YCbCr 4:4:4 (Y on Green). 001 = YCbCr 4:2:2; 16-bit, 20-bit, and 24-bit. 010 = Same as 001 with HS and VS embedded as SAV and EAV. 011 = ITU656 with separated syncs. 100 = ITU656 with embedded syncs. 101 = DDR RGB 4:4:4 or YCbCr 4:4:4. 110 = DDR YCbCr 4:2:2. 111 = undefined. Default = 000. 0x15 Read/Write [0] *****0 low_frq_video Video refresh rate. 0 = VREF > 30 Hz. 1 = VREF ≤ 30 Hz refresh rate video. Default = 0. [7:6] 00** VFE_out_fmt Video output format. This should be written along with 0x45[5:4]. 00 = RGB 4:4:4. 01 = YCbCr 4:4:4. 1x = YCbCr 4:2:2. Default = 00. [5:4] 00** VFE_422_width 4:2:2 input, could be either 8-bit, 10-bit, or 12-bit. x0 = 12 bits. 01 = 10 bits 11 = 8 bits. Default = 00. 0x16 Read/Write [3:2] 00 VFE_input_style Styles refer to the input pin assignments. See Table 23 to Table 28. x0 = Style 1. 01 = St yle 2. 11 = Style 3. OBSOLETE

Rev. 0 | Page 23 of 48 Hex Address Read/Write or Read Only Bits Default Value Register Name [1] ******0* VFE_input_edge Video data input edge. Defines the first clock edge of video w ord clocked. 0 = rising edge. 1 = falling ed ge. Default = 0 (in reference to DDR). [0] *****0 VFE_input_cs Video input color space. 0 = RGB. 1 = YCbCr. Default = 0. [7] 0***** itu_error_correct_en ITU656 error correction. This must be enabled if using ITU656 f ormat. 0 = disable. 1 = enable Default = 0. [6] *0**** itu_vsync_pol VS polarity from regenerated ITU 656 input. 0 = high pol arity. 1 = low polarity. Default = 0. [5] 0*** itu_hsync_pol HS polarity from regenerated ITU 656 input. 0 = high pol arity. 1 = low polarity. Default = 0. [4:3] *00* csc_mode Sets the fixed point position of the CSC coefficients, including the a4, b4, and c4 offsets 01 = ±2.0, (fr om −8192 to +8190.) Default = 000. [2] *0 gen_444_en 4:2:2 to 4:4:4 upconversion mode. 1 = uses interpolation. 0 = no in terpolation. Default = 0. [1] ******0* ASP_ratio Aspect ratio of input video. 0 = 4:3. 1 = 16:9. Default = 0. 0x17 Read/Write [0] *****0 deGen_en Enable DE generator. The DE generator should be enabled when a DE input is not provided. 1 = enable DE generator. D efault = 0 (see Register 0x30 to Register 0x3A). 0x18 Read/Write [4:0] *00110 CSC_A1_MSB MSB of 0x19. 0x19 Read/Write [7:0] 01100010 CSC_A1_LSB Color space converter (CSC) coefficient for equation: ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x1A Read/Write [4:0] *00100 CSC_A2_MSB MSB of 0x1B. 0x1B Read/Write [7:0] 10101000 CSC_A2_LSB CSC coefficient for equation: ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x1C Read/Write [4:0] *00000 CSC_A3_MSB MSB of 0x1D. 0x1D Read/Write [7:0] 00000000 CSC_A3_LSB CSC coefficient for equation: R OUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x1E Read/Write [4:0] ***11100 CSC_A4_MSB MSB of 0x1F. OBSOLETE

Rev. 0 | Page 24 of 48 Hex Address Read/Write or Read Only Bits Default Value Register Name 0x1F Read/Write [7:0] 10000100 CSC_A4_LSB CSC coefficient for equation: R OUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x20 Read/Write [4:0] *11100 CSC_B1_MSB MSB of 0x21. 0x21 Read/Write [7:0] 10111111 CSC_B1_LSB CSC coefficient for equation: ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x22 Read/Write [4:0] *00100 CSC_B2_MSB MSB of 0x23. 0x23 Read/Write [7:0] 10101000 CSC_B2_LSB CSC coefficient for equation: R OUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x24 Read/Write [4:0] *11110 CSC_B3_MSB MSB of 0x25. 0x25 Read/Write [7:0] 01110000 CSC_B3_LSB CSC coefficient for equation: R OUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x26 Read/Write [4:0] *00010 CSC_B4_MSB MSB of 0x27. 0x27 Read/Write [7:0] 00011110 CSC_B4_LSB CSC coefficient for equation: ROUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x28 Read/Write [4:0] *00000 CDC_C1_MSB MSB of 0x29. 0x29 Read/Write [7:0] 00000000 CSC_C1_LSB CSC coefficient for equation: R OUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x2A Read/Write [4:0] *00100 CSC_C2_MSB MSB of 0x2B. 0x2B Read/Write [7:0] 10101000 CSC_C2_LSB CSC coefficient for equation: R OUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x2C Read/Write [4:0] *01000 CSC_C3_MSB MSB of 0x2D. 0x2D Read/Write [7:0] 00010010 CSC_C3_LSB CSC coefficient for equation: R OUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x2E Read/Write [4:0] *11011 CSC_C4_MSB MSB of 0x2F. 0x2F Read/Write [7:0] 10101100 CSC_C4_LSB CSC coefficient for equation: R OUT = (a1 × RIN) + (a2 × GIN) + (a3 × BIN) + a4 GOUT = (b1 × RIN) + (b2 × GIN) + (b3 × BIN) + b4 BBOUT = (c1 × RIN) + (c2 × GIN) + (c3 × BIN) + c4 0x30 Read/Write [7:0] 00000000 VFE_hs_pla_MSB Most significant 8 bits for HSYNC placement for ITU

656 HSY

NC regeneration. [7:6] 00**** VFE_hs_pla_LSB HSYNC placement lower 2 bits (see 0x30). 0x31 Read/Write [5:0] 000000 VFE_hs_dur_MSB Most significant 6 bits for HSYNC duration. [7:4] 0000** VFE_hs_dur_LSB HSYNC duration lower 4 bits (see 0x31). 0x32 Read/Write [3:0] **0000 VFE_vs_pla_MSB Most significant 4 bits for VSYNC placement for ITU

656 VSY

NC regeneration. [7:2] 000000 VFE_vs_pla_LSB VSYNC placement lower 6 bits (see 0x32). 0x33 Read/Write [1:0] ****00 VFE_vs_dur_MSB Most significant 2 bits for VSYNC duration. 0x34 Read/Write [7:0] 00000000 VFE_vs_dur_LSB VSYNC duration lower 8 bits (see 0x33). 0x35 Read/Write [7:0] 00000000 VFE_hsDelayIn_MSB Most significant 8 bits for HSYNC delay in for ITU 656 HSY NC regeneration. OBSOLETE

Rev. 0 | Page 25 of 48 Hex Address Read/Write or Read Only Bits Default Value Register Name [7:6] 00**** VFE_hsDelayIn_LSB HSYNC delay in lower 2 bits (see 0x35). 0x36 Read/Write [5:0] 000000 VFE_vsDelayIn VSYNC delay in for DE generation. [7:5] 000*** Interlace Offset Sets the difference (in HSYNCs) in field length bet ween Field 0 and Field 1. 0x37 Read/Write [4:0] *00000 VFE_width_MSB Most significant 5 bits for frame width. 0x38 Read/Write [7:1] 0000000* VFE_width Lower 7 bits for frame width (see 0x37). 0x39 Read/Write [7:0] 00000000 VFE_height_MSB Most significant 8 bits for frame height. 0x3A Read/Write [7:4] 0000** VFE_height Lower 4 bits for frame height (see 0x39). [7] 1***** ext_audioSF_sel Audio sampling frequency select. Valid when using S/PDIF input. 0 = fS extracted from SPDIF. 1 = fS set via 0x15[7:4]. Default = 1 (only used during pix el repetition mode). [6:5] *00*** pr_mode Pixel repetition mode selection. Set to b00 unless nonstanda rd video is supported. 00 = auto mode. 01 = max mode 1x = manual mode (see 0x3B Bits [4:3]). Default = 00. [4:3] *00* ext_PLL_pr External value for PLL pixel repetition. 00 = ×1. 01 = ×2. 10 = ×4. 11 = ×4. Default = 00. [2:1] ***00* ext_target_pr User programmed pixel repetition number to send to Rx . Default = 00. 0x3B Read/Write 0 = no CSC. 1 = enable CSC. Default = 0. 0x3C Read/Write [5:0] 000000 ext_VID_to_Rx User programmed VID to send to Rx. See Table 24 for full VID formats. Default = 0x00. [7:6] 00** pr_to_Rx The actual pixel repetition sent to Rx. 0x3D Read [5:0] 000000 VID_to_Rx The actual VID sent to HDMI Rx (see Table 24). 0x3E Read [7:2] 000000 VFE_fmt_VID VID detected by video FE (see Table 24). [7:5] 000* VFE_aux_vid This register is for video input formats that are not inside the 861B table 000 = 480i not active. 001 = 240p not ac tive. 010 = 576i not active. 011 = 288p not active. 100 = 480i active. 101 = 240p active. 110 = 576i active. 111 = 288p active. Default = 000. 0x3F Read [4:3] *00*** VFE_prog_mode Information about 240p and 288p. 240p − 01 = 262 lines. 240p − 10 = 263 lines 288p − 01 = 312 lines. 288p − 10 = 313 lines. 288p − 11 = 314 lines. Default = 00. OBSOLETE

Rev. 0 | Page 26 of 48 Hex Address Read/Write or Read Only Bits Default Value Register Name [7] 0******* GC_pkt_en 1 = enable general control packet. Default = 0. [6] *0**** SPD_pkt_en 1 = enable source product descriptor packet. Default = 0. [5] 0*** MPEG_pkt_en 1 = enable MPEG packet. Default = 0. [4] *0** ACP_pkt_en 1 = enable ACP packet. Default = 0. 0x40 Read/Write [3] 0* ISRC_pkt_en 1 = enable ISRC packet. Default = 0. [6] *1**** system_PD 0 = all circuits powered up. 1 = po wer down the whole chip, except I2C, HPD interrupt and MSEN interrupt. Default = 1. [5] 0*** Test bit Must be set to 0. [4] *1** INTR_pol Interrupt polarity. 0 = low active interrupt. 1 = high ac tive interrupt. Default = 1. 0x41 Read/Write [3] 0* initiate_scan 1 = initiate scan. Default = 1. [7] 1******* PD_pol Polarity for power-down pin. 0 = low active. = high active. [6] *0**** HPD_state State of the hot plug detection. 0 = hot plug detect inactive. 1 = hot plug ac tive. 0x42 Read [5] 0*** MSEN_state State of the monitor connection. 0 = HDMI clock termination not detected. 1 = HDMI clock ter mination detected. 0x43 Read/Write [7:0] 01111110 EDID_ID The I2C address for EDID memory. Default = 0x7E. [7] 0***** spdif_en 1 = enable S/PDIF receiver. Default = 0. [6] *1**** N_CTS_pkt_en 1 = enable N_CTS packet. Default = 1. [5] 1*** audio_sample_pkt_en 1 = enable audio sample packet. Default = 1. [4] *1** aviIF_pkt_en 1 = enable avi info frame. Default = 1. 0x44 Read/Write [3] 1* audioIF_pkt_en 1 = enable audio info frame. Default = 1. [7] 0******* clear_avmute 1 = clear av mute. Default = 0. [6] *0**** set_avmute 1 = set av mute. Default = 0. [5:4] 00** Y1Y0 Output format, should be written when 0x16[7:6] is wr itten. 00 = RGB. 01 = YCbCr 4:2:2. 10 = YCbCr 4:4:4. 11 = reserved. Default = 00. I nformation Status Active format information present. 0 = no data. 1 = ac tive format information valid. Default = 0. 0x45 Read/Write [2:1] ***00* Bar Information B[1:0]. 00 = no bar information. 1 = horizontal bar information valid. 10 = vertical bar information valid. 11 = horizontal and vertical bar information valid. Default = 00. OBSOLETE

Rev. 0 | Page 27 of 48 Hex Address Read/Write or Read Only Bits Default Value Register Name [7:6] 00**** Scan Information S[1:0]. 00 = no information. 01 = oversca nned (television). 10 = underscanned (computer). 11 = undefined. Default = 00. [5:4] 00** Colorimetry C[1:0]. 00 = no data. 01 = SM PTE 170M, ITU601. 10 = ITU709. 11 = undefined. Default = 00. 0x46 Read/Write [3:2] 00 Picture Aspect Ratio M[1:0]. 00 = no data. 01 = 4:3. 10 = 16:9. 11 = undefined. Default = 00. [1:0] ****00 Nonuniform Pict ure Scaling SC[1:0]. 00 = No known nonuniform scaling. 01 = picture has been scaled horizontally. 10 = picture has been scaled vertically. 11 = picture has been scaled horizontally and vertically. Default = 00. 0x47 Read/Write [7:4] 0000 Active Format Aspect Ratio R[3:0]. 1000 = same as picture aspect ratio. 1001 = 4:3 (center). 1010 = 16:9 (center). 1011 = 14:9 (center). Default = 0x0. 0x48 Read/Write [7:0] 00000000 Active Line Start LSB 0x49 Read/Write [7:0] 00000000 Active Line Start MSB This represents the line number at the end of the top horizonta l bar. If 0, there is no horizontal bar. 0x4A Read/Write [7:0] 00000000 Active Line End LSB 0x4B Read/Write [7:0] 00000000 Active Line End MSB This represents the line number at the beginning of a l ower horizontal bar. If greater than the number of active video lines, there is no lower horizontal bar. 0x4C Read/Write [7:0] 00000000 Active Pixel Start LSB 0x4D Read/Write [7:0] 00000000 Active Pixel Start MSB This represents the last pixel in a vertical pillar bar at the left side of the pi cture. If 0, there is no left bar. 0x4E Read/Write [7:0] 00000000 Active Pixel End LSB 0x4F Read/Write [7:0] 00000000 Active Pixel End MSB This represents the first horizontal pixel in a vertical pillar bar at the right side of the picture. If greater than the maximum number of horizontal pixels, there is no vertical bar. [7:5] 000* audio_IF_CC Channel count. 000 = refer to stream header. 001 = 2 channels. 010 = 3 channels. 111 = 8 channels. Default = 000. 0 = Permitted or no information about this. 1 = Pro hibited. Default = 0. 0x50 Read/Write [3:0] **0000 Level Shift LSV[3:0]. Level Shift Values with att enuation information. 0000 = 0 dB attenuation. 0001 = 1 dB attenuation. 1111 = 15 dB attenuation. Default = 0x0. OBSOLETE

Rev. 0 | Page 28 of 48 Hex Address Read/Write or Read Only Bits Default Value Register Name 0x51 Read/Write [7:0] 00000000 Speaker Mapping CA[7:0]. Speaker mapping or placement for up to 8 channe ls (see Table 24). Default = 0x00. 0x52 Read/Write [7:0] 00000000 Source Product De scription Infoframe Byte 1. (SPD_B1) Vendor name character 1 (VN1). 0x53 Read/Write [7:0] 00000000 SPD_B2 VN2. 0x54 Read/Write [7:0] 00000000 SPD_B3 VN3. 0x55 Read/Write [7:0] 00000000 SPD_B4 VN4. 0x56 Read/Write [7:0] 00000000 SPD_B5 VN5. 0x57 Read/Write [7:0] 00000000 SPD_B6 VN6. 0x58 Read/Write [7:0] 00000000 SPD_B7 VN7. 0x59 Read/Write [7:0] 00000000 SPD_B8 VN8. 0x5A Read/Write [7:0] 00000000 SPD_B9 Product description character 1 (PD1). 0x5B Read/Write [7:0] 00000000 SPD_B10 PD2. 0x5C Read/Write [7:0] 00000000 SPD_B11 PD3. 0x5D Read/Write [7:0] 00000000 SPD_B12 PD4. 0x5E Read/Write [7:0] 00000000 SPD_B13 PD5. 0x5F Read/Write [7:0] 00000000 SPD_B14 PD6. 0x60 Read/Write [7:0] 00000000 SPD_B15 PD7. 0x61 Read/Write [7:0] 00000000 SPD_B16 PD8. 0x62 Read/Write [7:0] 00000000 SPD_B17 PD9. 0x63 Read/Write [7:0] 00000000 SPD_B18 PD10. 0x64 Read/Write [7:0] 00000000 SPD_B19 PD11. 0x65 Read/Write [7:0] 00000000 SPD_B20 PD12. 0x66 Read/Write [7:0] 00000000 SPD_B21 PD13. 0x67 Read/Write [7:0] 00000000 SPD_B22 PD14. 0x68 Read/Write [7:0] 00000000 SPD_B23 PD15. 0x69 Read/Write [7:0] 00000000 SPD_B24 PD16. 0x6A Read/Write [7:0] 00000000 SPD_B25 Source device information code. Code defines source, such as DVD or STB. Default = 0x00. 0x6B Read/Write [7:0] 00000000 MPEG_B0 0x6C Read/Write [7:0] 00000000 MPEG_B1 0x6D Read/Write [7:0] 00000000 MPEG_B2 0x6E Read/Write [7:0] 00000000 MPEG_B3 MB[0]. Lower byte of MPEG bit rate: Hz. This is the low er 8 bits of 32 bits (4 bytes) that specify the MPEG bit rate in Hz. MB[1]. MB[2]. MB[3] (upper byte). 0x6F Read/Write [7] 0******* MPEG_FR FR indicates new picture or repeat. 0 = new field or picture. 1 = r epeated field. Default = 0. 0x70 Read/Write [6:5] *00***** MPEG_MF MPEG frame indicator. MF[1:0] identifies whether frame is an I, B, or P pic ture. 00 = unknown. 01 = I pic ture. 10 = B picture. 11 = P picture. Default = 00. OBSOLETE

Rev. 0 | Page 29 of 48 Hex Address Read/Write or Read Only Bits Default Value Register Name 0x71 Read/Write [7:0] 00000000 Audio Content P rotection Packet (ACP) Type ACP type. 0 = generic audio. 1 = IEC 60958-iden tified audio. 2 = DVD audio. 3 = reserved for SACD. Default = 0x00. 0x72 Read/Write [7:0] 00000000 ACP_byte1 Audio content protection. [7:6] audio_copy_permission. [5:3] audio_c opy_number. [2:1] quality. [0] transaction. [7] 0******* ISRC1 Continued International standard recording code continued (ISRC1). Indicates an ISRC2 packet is being transmitted. 1 = the 2nd ISRC packet is needed. Default = 0. [6] *0**** ISRC1_valid 0 = ISRC1 status bits and PBs not valid. 1 = ISRC1 sta tus bits and PBs valid. Default = 0. 0x73 Read/Write [5:3] 000*** ISRC1 Status These bits indicate beginning, middle, and end of a tr ack. 001 = start. 010 = middle. 100 = end. Default = 000. 0x74 Read/Write [7:0] 00000000 ISRC1_PB0 ISRC1 Packet Byte 0. 0x75 Read/Write [7:0] 00000000 ISRC1_PB1 ISRC1 Packet Byte 1. 0x76 Read/Write [7:0] 00000000 ISRC1_PB2 ISRC1 Packet Byte 2. 0x77 Read/Write [7:0] 00000000 ISRC1_ PB3 ISRC1 Packet Byte 3. 0x78 Read/Write [7:0] 00000000 ISRC1_ PB4 ISRC1 Packet Byte 4. 0x79 Read/Write [7:0] 00000000 ISRC1_ PB5 ISRC1 Packet Byte 5. 0x7A Read/Write [7:0] 00000000 ISRC1_ PB6 ISRC1 Packet Byte 6. 0x7B Read/Write [7:0] 00000000 ISRC1_ PB7 ISRC1 Packet Byte 7. 0x7C Read/Write [7:0] 00000000 ISRC1_ PB8 ISRC1 Packet Byte 8. 0x7D Read/Write [7:0] 00000000 ISRC1_ PB9 ISRC1 Packet Byte 9. 0x7E Read/Write [7:0] 00000000 ISRC1_ PB10 ISRC1 Packet Byte 10. 0x7F Read/Write [7:0] 00000000 ISRC1_ PB11 ISRC1 Packet Byte 11. 0x80 Read/Write [7:0] 00000000 ISRC1_ PB12 ISRC1 Packet Byte 12. 0x81 Read/Write [7:0] 00000000 ISRC1_ PB13 ISRC1 Packet Byte 13. 0x82 Read/Write [7:0] 00000000 ISRC1_ PB14 ISRC1 Packet Byte 14. 0x83 Read/Write [7:0] 00000000 ISRC1_ PB15 ISRC1 Packet Byte 15. 0x84 Read/Write [7:0] 00000000 ISRC2_ PB0 ISRC2 Packet Byte 0. 0x85 Read/Write [7:0] 00000000 ISRC2_ PB1 ISRC2 Packet Byte 1. 0x86 Read/Write [7:0] 00000000 ISRC2_ PB2 ISRC2 Packet Byte 2. 0x87 Read/Write [7:0] 00000000 ISRC2_ PB3 ISRC2 Packet Byte 3. 0x88 Read/Write [7:0] 00000000 ISRC2_ PB4 ISRC2 Packet Byte 4. 0x89 Read/Write [7:0] 00000000 ISRC2_ PB5 ISRC2 Packet Byte 5. 0x8A Read/Write [7:0] 00000000 ISRC2_ PB6 ISRC2 Packet Byte 6. 0x8B Read/Write [7:0] 00000000 ISRC2_ PB7 ISRC2 Packet Byte 7. 0x8C Read/Write [7:0] 00000000 ISRC2_ PB8 ISRC2 Packet Byte 8. 0x8D Read/Write [7:0] 00000000 ISRC2_ PB9 ISRC2 Packet Byte 9. 0x8E Read/Write [7:0] 00000000 ISRC2_ PB10 ISRC2 Packet Byte 10. 0x8F Read/Write [7:0] 00000000 ISRC2_ PB11 ISRC2 Packet Byte 11. OBSOLETE

Rev. 0 | Page 30 of 48 Hex Address Read/Write or Read Only Bits Default Value Register Name 0x90 Read/Write [7:0] 00000000 ISRC2_ PB12 ISRC2 Packet Byte 12. 0x91 Read/Write [7:0] 00000000 ISRC2_ PB13 ISRC2 Packet Byte 13. 0x92 Read/Write [7:0] 00000000 ISRC2_ PB14 ISRC2 Packet Byte 14. 0x93 Read/Write [7:0] 00000000 ISRC2_ PB15 ISRC2 Packet Byte 15. 0x94 Read/Write [7:0] 11000000 mask1 Mask for Interrupt Group1 (0x96). 0x95 Read/Write [7:6] 00**** mask2 Mask for Interrupt Group 2 (0x97[7:6]. [7] f or HDCP error. [6] for BKSV flag. [7] 0***** HPD_INT Interrupt for hot plug detect (HPD). [6] *0**** MSEN_INT Interrupt for monitor connection (MSEN). [5] 0*** VS_INT Interrupt for active VS edge. [4] *0** AUD_FIFO_FULL_INT Interrupt for audio FIFO overflow. [3] 0* ITU656_ERR_INT Interrupt for ITU656 error. 0x96 Read/Write [2] ***0 EDID_RDY_INT Interrupt for EDID Ready. [7] 0******* HDCP_ERR_INT Interrupt bit from HDCP master. [6] *0**** BKSV_flag Set to 1 to instruct the MPU to read the BKSV or the EDID ME M for revocation list checking. 0x97 Read/Write [2] *0 Test bit Must be written to 1 for proper operation. [7] 0**** Must be written to 0 for proper operation. 0x98 Read/Write [3:0] 0010 Test bits Must be written to 0x2 for proper operation. 0x9C Read/Write [7:0] Test bits Must be written to 0x3A for proper operation. 0x9D Read/Write [3:0] 0* Test bit Must be wr itten to 1 for proper operation. 0xA2 Read/Write [7:0] Test bits Must be written to 0x87 for proper operation. 0xA3 Read/Write [7:0] Test bits Must be written to 0x87 for proper operation. [7] 0***** HDCP_desired HDCP encryption. 0 = input A/V content not to be encrypted. 1 = the input A/ V content should be encrypted. Default = 0. [5] 0*** Must be written to 0 for proper operation. [4] *1** frame_enc Frame encryption. 0 = the current frame should not be encrypted. 1 = the cur rent frame should be encrypted. Default = 1. [3] 0* Must be written to 0 for proper operation. 0xAF Read/Write 0 = DVI. 1 = HDMI. Default = 0. [0] *******0 Must be written to 0 for proper operation. 0xB0 Read [7:0] 00000000 An_0 Byte 0 of An. 0xB1 Read [7:0] 00000000 An_1 Byte 1 of An. 0xB2 Read [7:0] 00000000 An_2 Byte 2 of An. 0xB3 Read [7:0] 00000000 An_3 Byte 3 of An. 0xB4 Read [7:0] 00000000 An_4 Byte 4 of An. 0xB5 Read [7:0] 00000000 An_5 Byte 5 of An. 0xB6 Read [7:0] 00000000 An_6 Byte 6 of An. OBSOLETE

Rev. 0 | Page 31 of 48 Hex Address Read/Write or Read O nly Bits Default Va lue Regist er Name 0xB7 Read [7:0] 00000000 An_7 Byte 7 of An. [6] *0**** ENC_on 1 = the A/V content is being encrypted. 0 = not encr ypted. Default = 0. 1 = HDMI mode. 0 = DVI mode. [4] *0** keys_read_error 1 = HDCP key reading error. [7:5] 000* Edge select for input video clock. 011 = positive edge capture. 111 = nega tive edge capture. Default = 000. 0xBA Read/Write clk_delay Must be written to 1 for proper operation. [3] 0* Must be written to 0 for proper operation. [6] *0 Repeater HDCP repeater. 0 = HDCP receiver is not repeater capable. 1 = HDCP r eceiver is repeater capable. [5] 0* ** KSV ready KSV FIFO ready. 1 = HDCP receiver has compiled list of attached KSVs. [4] *0 ** Test bit Must be written to 0 for proper operation. [3:2] 00 Test bit Reserved. [1] ** 0* HDCP support HDCP 1.1 features support. 0 = HDCP receiver does not support version 1.1 f eatures. 1 = HDCP receiver supports 1.1 features such as enhanced encryption status signaling (EESS). 0xBE Read [0] ** *0 Fast HDCP Fast authentication. 0 = HDCP Receiver not capable of fast authentication. 1 = HDCP R eceiver capable of receiving unencrypted video during the session re-authentication. 0xBF Read [7:0] 00000000 BKSV1 0xC0 Read [7:0] 00000000 BKSV2 0xC1 Read [7:0] 00000000 BKSV3 0xC2 Read [7:0] 00000000 BKSV4 0xC3 Read [7:0] 00000000 BKSV5 BKSV read from Rx by the HDCP controller 40 bits (5 b ytes). 0xC4 Read/Write [7:0] 00000000 EDID Segment Sets the E-DDC segment used by the EDID fetch r outine. [7] 0***** Error Flag Error flag. [5] 0*** HDCP Enabled HDCP enabled. [4] *0** EDID Ready Flag EDID ready. [1] ****0* BKSV Update Flag BKSV update. 0xC5 Read [3] **0* HDCP Requested HDCP requested. [1] ******0* EEPROM Read OK EEPROM read. 0xC6 Read [0] *****0 TMDS Output Enabled TMDS output enabled. [7] 0***** BKSV Flag BKSV flag. 0xC7 Read/Write [6:0] *0000000 BKSV Count BKSV count OBSOLETE

Rev. 0 | Page 32 of 48 Hex Address Read/Write or Read O nly Bits Default Va lue Regist er Name [7:4] 0000** HDCP Controller Error HDCP controller error, see Table 28. 0xC8 Read [3:0] 0000 HDCP Controller State HDCP controller state. 0xC9 Read/Write [3:0] **0011 EDID Tries Number of times that the EDID is read if unsuccessful. Default = 0x OBSOLETE

Rev. 0 | Page 33 of 48 2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION 0x00—Bits[7:0] Chip Revision An 8-bit register that represents the silicon revision. 0x01—Bits[3:0] N[19:16] These are the most significant four bits of a 20-bit word used along with the 20-bit CTS term in the receiver to regenerate the audio clock. 0x02—Bits[7:0] N[15-8] 0x04—Bits[3:0] CTS_Int[19:16] These are the most significant four bits of a 20-bit word used along with the 20-bit N term in the receiver to regenerate the audio clock. This is the measured or internal CTS. The internal or external CTS can be selected via 0x0A Bit 7. 0x05—Bits[7:0] CTS_Int[15:8] 0x06—Bits[7:0] CTS_In[7:0] 0x07—Bits[3:0] CT_Ext[19:16]) These are the most significant four bits of a 20-bit word used along with the 20-bit N term in the receiver to regenerate the audio clock. This is the external CTS. The internal or external CTS can be selected via 0x0A Bit 7. 0x08—Bits[7:0] CTS_Ext[15:8] 0x09—Bits[7:0] CTS_Ext[7:0] 0x0A—Bits[7] CTS_Sel When internal CTS is selected, the CTS is calculated by the AD9389. 0 = internal CTS 1 = external CTS 0x0A—Bits[6:5] Avg_Mode 00 = no filter 01 = divide by 4 10 = divide by 8 11 = divide by 16 Defa ult = 10 0x0A—Bit[4] Audio_Sel 0 = I2S 1 = S/PDIF Default = 0 0x0A—Bit[3] MCLK_SP If MCLK is available for S/PDIF, it is used for bit recovery; otherwise, internal circuitry is used. 1 = MCLK active 0 = MCLK inac tive Default = 0 0x0A—Bit[2] MCLK_I2S 1 = I2S MCLK active 0 = I2S MCLK inactive Default = 0 If MCLK is available for I2S, it is used for bit recovery; otherwise, internal circuitry is used. 0x0A—Bits[1:0] MCLK_Ratio 00 = ×128 fS 01 = ×256 fS 10 = ×384 fS 11 = ×512 fS Default = 01 0x0B—Bit[6] MCLK_ Pol 0 = rising edge 1 = falling edge Default = 0 0x0B—Bit[5] Flat_Line 1 = flat line audio (audio sample not valid) 0 = normal Default = 0 0x0C—Bits[5:2] I2S enable 0001 = I2S0 0010 = I2S1 0100 = I2S2 1000 = I2S3 Default = 1111 for all 0x0C—Bits[1:0] I2S Format 00 = standard I2S mode 01 = right-justified I2S mode 10 = left-justified I2S mode 11 = raw IEC60958 mode Default = 00 0x0D—Bits[4:0] I2S bit width For right-justified audio only. Default is 11000 (24). Not valid for widths greater than 24. 0x0E—Bits[5:3] SUBPKT0_L_src Source of audio subpacket 0 (left channel) data. Default is 000. OBSOLETE

Table 23. Source of Subpacket Audio

000 Channel 0 Left

001 Channel 0 Right

010 Channel 1 Left

011 Channel 1 Right

100 Channel 2 Left

101 Channel 2 Right

110 Channel 3 Left

111 Channel 3 Right

Default is 001 (see Table 27). Default is 010 (see Table 27). Default is 011 (see Table 27). Default is 100 (see Table 27). Default is 101 (see Table 27). Default is 110 (see Table 27). Default is 111 (see Table 27). The default value for the 13-bit, a1 coefficient is 0x0662. The default value for the 13-bit a2 coefficient is 0x04A8. The default value for the 13-bit a3 is 0x0000. The default value for the 13-bit a4 is 0x1C84. The default value for the 13-bit b1 is 0x1CBF. The default value for the 13-bit b2 is 0x04A8. The default value for the 13-bit b3 is 0x1E70. The default value for the 13-bit b4 is 0x021E. The default value for the 13-bit c1 is 0x0000. The default value for the 13-bit c2 is 0x04A8. The default value for the 13-bit c3 is 0x0812. The default value for the 13-bit c4 is 0x1BAC.

Rev. 0 | Page 36 of 48 0x50—Bits[7:5] audio_IF_cc 000 = refer to stream header 001 = 2 channels 010 = 3 channels 111 = 8 channels 0x50—Bits[4] audi_IF_DM_INH 0x50—Bits[3:0] Level Shift LSV[3:0] – Level Shift Values with attenuation information. 0000 = 0 dB attenuation 0001 = 1 dB a ttenuation 1111 = 15 dB attenuation Default = 0x0 0x51—Bits[7:0] Speaker Mapping These bits define the suggested placement of speakers. Table 25. CA Channel Number Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 0 0 0 0 - - FR FL 0 0 0 0 1 - LFE FR FL 0 0 0 1 0 FC - FR FL 0 0 0 1 1 FC LFE FR FL 0 0 1 0 0 RC - - FR FL 0 0 1 0 1 RC - LFE FR FL 0 0 1 1 0 RC FC - FR FL 0 0 1 1 1 RC FC LFE FR FL 0 1 0 0 0 RR RL - - FR FL 0 1 0 0 1 RR RL - LFE FR FL 0 1 0 1 0 RR RL FC - FR FL 0 1 0 1 1 - - RR RL FC LFE FR FL 0 1 1 0 0 - RC RR RL - - FR FL 0 1 1 0 1 - RC RR RL - LFE FR FL 0 1 1 1 0 - RC RR RL FC - FR FL 0 1 1 1 1 - RC RR RL FC LFE FR FL 1 0 0 0 0 RRC RLC RR RL - - FR FL 1 0 0 0 1 RRC RLC RR RL - LFE FR FL 1 0 0 1 0 RRC RLC RR RL FC - FR FL 1 0 0 1 1 RRC RLC RR RL FC LFE FR FL 1 0 1 0 0 FRC FLC - - - - FR FL 1 0 1 0 1 FRC FLC - - - LFE FR FL 1 0 1 1 0 FRC FLC - - FC - FR FL 1 0 1 1 1 FRC FLC - - FC LFE FR FL 1 1 0 0 0 FRC FLC - RC - - FR FL 1 1 0 0 1 FRC FLC - RC - LFE FR FL 1 1 0 1 0 FRC FLC - RC FC - FR FL 1 1 0 1 1 FRC FLC - RC FC LFE FR FL 1 1 1 0 0 FRC FLC RR RL - - FR FL 1 1 1 0 1 FRC FLC RR RL - LFE FR FL 1 1 1 1 0 FRC FLC RR RL FC - FR FL 1 1 1 1 1 FRC FLC RR RL FC LFE FR FL OBSOLETE

Rev. 0 | Page 37 of 48 SOURCE PRODUCT DESCRIPTION (SPD) INFOFRAME 0x52—Bits[7:0] SPD_B1 This is the first character in eight that is the name of the company that appears on the product. The data characters are 7-bit ASCII code. 0x53—Bits[7:0] SPD_B 2 (VN2) 0x54—Bits[7:0] SPD_B 3(VN3) 0x55—Bits[7:0] SPD_B 4(VN4) 0x56—Bits[7:0] SPD_B 5(VN5) 0x57—Bits[7:0] SPD_B 6(VN6) 0x58—Bits[7:0] SPD_B 7(VN7) 0x59—Bits[7:0] SPD_B 8(VN8) 0x5A—Bits[7:0] SBD_B9 Product Description Character 1 (PD1) This is the first character of 16 that contains the model number and a short description of the product. The data characters are 7-bit ASCII code. 0x5B—Bits[7:0] SBD_B10(PD2) 0x5C—Bits[7:0] SBD_B11(PD3) 0x5D—Bits[7:0] SBD_B12(PD4) 0x5E—Bits[7:0] SBD_B13(PD5) 0x5F—Bits[7:0] SBD_B14(PD6) 0x60—Bits[7:0] SBD_B15(PD7) 0x61—Bits[7:0] SBD_B16(PD8) 0x62—Bits[7:0] SBD_B17(PD9) 0x63—Bits[7:0] SBD_B18(PD10) 0x64—Bits[7:0] SBD_B19(PD11) 0x65—Bits[7:0] SBD_B20(PD12) 0x66—Bits[7:0] SBD_B21(PD13) 0x67—Bits[7:0] SBD_B22(PD14) 0x68—Bits[7:0] SBD_B23(PD15) 0x69—Bits[7:0] SBD_B24(PD16) 0x6A—Bits[7:0] Source Device Information Code These bytes classify the source device. Table 26. SDI Code Source 0x00 Unknown 0x01 Digital STB 0x02 DVD 0x03 D-VHS 0x04 HDD V ideo 0x05 DVC 0x06 DSC 0x07 Video CD 0x08 Game 0x09 PC gener al 0x0A to 0xFF Reserved 0x6B—Bits[7:0] MPEG_B0 This is the lower 8 bits of 32 bits that specify the MPEG bit rate in Hz. 0x6C—Bits[7:0] MPEG_B1 0x6D—Bits[7:0] MPEG_B2 0x6E—Bits[7:0] MPEG_B3 0x73—Bits[7] ISRC1 Continued This bit indicates that a continuation of the 16 ISRC1 packet bytes (an ISRC2 packet) is being transmitted. 0x73—Bit[6] ISRC1 Valid This bit indicates whether ISRC1 packet bytes are valid. Table 27. ISRC1 Valid

0 ISRC1 Status bits and PBs not valid

1 ISRC1 Status bits and PBs valid

0x73—Bits[5:3] ISRC1 Status These bits define where the samples are in the ISRC track: at least two transmissions of 001 occur at the beginning of the track; continuous transmission of 010 occurs in the middle of the track, followed by at least two transmissions of 100 near the end of the track. 0x74—Bits[7:0] ISRC1_PB0 0x75—Bits[7:0] ISRC1_PB1 0x76—Bits[7:0] ISRC1_PB2 0x77—Bits[7:0] ISRC1_PB3 0x78—Bits[7:0] ISRC1_PB4 0x79—Bits[7:0] ISRC1_PB5 0x7A—Bits[7:0] ISRC1_PB6 0x7B—Bits[7:0] ISRC1_PB7 0x7C—Bits[7:0] ISRC1_PB8 0x7D—Bits[7:0] ISRC1_PB9 0x7E—Bits[7:0] ISRC1_PB10 0x7F—Bits[7:0] ISRC1_PB11 0x80—Bits[7:0] ISRC1_PB12 0x81—Bits[7:0] ISRC1_PB13 0x82—Bits[7:0] ISRC1_PB14 0x83—Bits[7:0] ISRC1_PB15 OBSOLETE

Rev. 0 | Page 38 of 48 0x84—Bits[7:0] ISRC2_PB0 This is transmitted only when the ISRC continue bit (Register 0x73 Bit 7) is set to 1. 0x85—Bits[7:0] ISRC2_PB1 0x86—Bits[7:0] ISRC2_PB2 0x87—Bits[7:0] ISRC2_PB3 0x88—Bits[7:0] ISRC2_PB4 0x89—Bits[7:0] ISRC2_PB5 0x8A—Bits[7:0] ISRC2_PB6 0x8B—Bits[7:0] ISRC2_PB7 0x8C—Bits[7:0] ISRC2_PB8 0x8D—Bits[7:0] ISRC2_PB9 0x8E—Bits[7:0] ISRC2_PB10 0x8F—Bits[7:0] ISRC2_PB11 0x90—Bits[7:0] ISRC2_PB12 0x91—Bits[7:0] ISRC2_PB13 0x92—Bits[7:0] ISRC2_PB14 0x93—Bits[7:0] ISRC2_PB15 0x94—Bits[7:0] mask1 0x95—Bits[7:6] mask2 0x96—Bit[7] HPD_INT 0x96—Bit[6] MSEN_INT 0x96—Bit[5] VS_INT 0x96—Bit[4]AUD_FIFO_FULL_INT 0x96—Bit[3] ITU656_ERR_INT 0x96—Bit[2] EDID_RDY_INT 0x97—Bit[7] HDCP_ERR_INT 0x97—Bit[6] BKSV_flag 0x97—Bit[2] 0x98—Bit[7] 0x98—Bits[3:0] 0x9C—Bits[7:0] 0x9D—Bits[3:0] 0xA2—Bits[7:0] 0xA3—Bits[7:0] 0xAF—Bit[7] HDCP_desired 0xAF—Bit[4] frame_enc 0xAF—Bit[1] ext_HDMI_MODE 0xB0—Bits[7:0] An_0 0xB1—Bits[7:0] An_1 0xB2—Bits[7:0] An_2 0xB3—Bits[7:0] An_3 0xB4—Bits[7:0] An_4 0xB5—Bits[7:0] An_5 0xB6—Bits[7:0] An_6 0xB7—Bits[7:0] An_7 0xB7—Bit[6] ENC_on 0xB7—Bit[5] int_HDMI_MODE 0xB7—Bit[4] keys_read_error 0xBA—Bits[7:5] clk_delay 0xBA—Bit[4] clk_delay 0xBE—Bit[7] BCAPS 0xBE—Bit[6] 0xBE—Bit[5] 0xBE—Bit[4] 0xBE—Bits[3:2] 0xBE—Bit[1] 0xBE—Bit[0] 0xBF—Bits[7:0] Bksv1 0xC0—Bits[7:0] Bksv Byte2 0xC1—Bits[7:0] Bksv3 0xC2—Bits[7:0] Bksv4 0xC3—Bits[7:0] Bksv5 0xC4—Bits[7:0] EDID Segment These bits support up to 256 EDID segments that can be addressed. The requested segment address is written here before initiation of the read. 0xC5—Bit[7] ErrorFlag 0xC5—Bit[6] AN Stop 0xC5—Bit[5] HDCP Enabled 0xC5—Bit[4] EDID Ready 0xC5—Bit[3] I 0xC5—Bit[2] RI 0xC5—Bit[1] BKSV Update 0xC5—Bit[0] PJ 0xC6—Bit[4] HDMI Mode 0xC6—Bit[3] HDCP Requested 0xC6—Bit[2] Rx Sense 0xC6—Bit[1] EEPROM Read 0xC7—Bit[7] BKSV Flag 0xC7—Bits[6:0] BKSV Count OBSOLETE

Rev. 0 | Page 39 of 48 0xC8—Bits[7:4] HDCP Controller Error When an error occurs in the HDCP flow, it is reported here after setting the error flag (0xC5[7]). Table 28. Error Code Error Condition

0000 No error

0001 Bad receiver BKSV

0010 Ri mismatch

0011 Pj mismatch

0100 I 2C error (usually a no acknowledge)

0101 Timed out waiting for downstream repeater

0110 Maximum cascade of repeaters exceeded

0111 SHA-1 hash check of BKSV list failed

1000 Too many devices connected to repeater tree

0xC8—Bits[3:0] HDCP Controller State This information is used in troubleshooting the HDCP controller. 0xC9—Bits[3:0] EDID Read Tries These bits define the number of times the EDID attempts to be read if unsuccessful. OBSOLETE

on SCL and SDA are pulled high by external pull-up resistors.

• St art signal
• Sla ve address byte
• B ase register address byte
• Da ta byte to read or write
• Stop signal When the serial interface is inactive (SCL and SDA are high), co mmunications are initiated by sending a start signal. The start signal is a high-to-low transition on SDA while SCL is high. This signal alerts all slave devices that a data transfer sequence is coming. The first 8 bits of data transferred after a start signal comprise a 7-b it slave address (the first 7 bits) and a single R/W bit (the eighth bit). The R/W bit indicates the direction of data transfer, read from (1) or write to (0) the slave device. If the transmitted slave address matches the address of the device, the AD9389 acknowledges by bringing SDA low on the ninth SCL pulse. If the addresses do not match, the AD9389 does not acknowledge.

Table 29. Serial Port Addresses master can generate a stop signal.

• The b ase address must be written with the R/ W bit of the slave address byte low to set up a sequential read operation.
• Re ading (the R/ W bit of the slave address byte high) begins at the previously established base address. The address of the read register auto-increments after each byte is transferred. To terminate a read/write sequence to the AD9389, a stop signal m ust be sent. A stop signal comprises a low-to-high transition of SDA while SCL is high. A repeated start signal occurs when the master device driving the s erial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the mode of communication (read/write) between the slave and master without releasing the serial interface lines. 05724-011 SDA SCL tBUFF tSTAH tDHO tDSU tDAL tDAH tSTASU tSTOSU

Figure 11. Serial Port Read/Write Timing

• St art signal
• Sla ve address byte (R/ W bit = low)
• B ase address byte
• Da ta byte to base address
• Stop signal
• W rite to four consecutive control registers
• St art signal
• Sla ve address byte (R/ W bit = low)
• B ase address byte
• Da ta byte to base address
• D ata byte to (base address + 1)
• D ata byte to (base address + 2)
• D ata byte to (base address + 3)
• Stop signal Read from one control register:
• St art signal
• Sla ve address byte (R/ W bit = low)
• B ase address byte
• St art signal
• Sla ve address byte (R/ W bit = high)
• Da ta byte from base address
• Stop signal Read from four consecutive control registers:
• St art signal
• Sla ve address byte (R/ W bit = low)
• B ase address byte
• St art signal
• Sla ve address byte (R/ W bit = high)
• Da ta byte from base address
• D ata byte from (base address + 1)
• D ata byte from (base address + 2)
• D ata byte from (base address + 3)
• Stop signal 05724-012 BIT 7 ACKBIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0SDA SCL

Figure 12. Serial Interface—Typical Byte Transfer

Rev. 0 | Page 42 of 48 PCB LAYOUT RECOMMENDATIONS The AD9389 is a high precision, high speed analog device. As such, to get the maximum performance out of the part, it is important to have a well laid out board. The following is a guide for designing a board using the AD9389. POWER SUPPLY BYPASSING It is recommended to bypass each power supply pin with a 0.1 μF capacitor. The exception is when two or more supply pins are adjacent to each other. For these groupings of powers/grounds, it is necessary to have only one bypass capacitor. The fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the AD9389, as that interposes resistive vias in the path. The bypass capacitors should be physically located between the p ower plane and the power pin. Current should flow from the power plane to the capacitor to the power pin. Do not make the power connection between the capacitor and the power pin. Placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. It is particularly important to maintain low noise and good st ability of PVDD (the clock generator supply). Abrupt changes in PVDD can result in similarly abrupt changes in sampling clock phase and frequency. This can be avoided by careful attention to regulation, filtering, and bypassing. It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (V DD and PVDD). Some graphic controllers use substantially different levels of p ower when active (during active picture time) and when idle (during horizontal and vertical sync periods). This can result in a measurable change in the voltage supplied to the analog supply regulator, which can in turn produce changes in the regulated analog supply voltage. This can be mitigated by regulating the analog supply, or at least PV DD, from a different, cleaner power source (for example, from a 12 V supply). It is also recommended to use a single ground plane for the en tire board. Experience has shown repeatedly that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. In some cases, using separate ground planes is unavoidable, t herefore, it is recommended to place a single ground plane under the AD9389. The location of the split should be at the receiver of the digital outputs. For this case, it is even more important to place components wisely because the current loops are much longer (current takes the path of least resistance). DIGITAL INPUTS The digital inputs on the AD9389 are designed to work with 1.8 V signals, but are tolerant of 3.3 V signals. Therefore, no extra components need to be added if using 3.3 V logic. Any noise that gets onto the HSYNC, VSYNC, or clock input t races can add jitter to the system. Therefore, minimize the trace lengths and do not run any digital or other high frequency traces near them. All TMDS lines must maintain a 50 Ω impedance trace and it is recommended that the trace lengths be as short as possible. To request a sample layout, send email to flatpanel_apps@analog.com. OBSOLETE

Table 30. HDTV YCbCr (0 to 255) to RGB (0 to 255) (Default Setting for AD9389) Table 31. HDTV YCbCr (16 to 235) to RGB (0 to 255) Table 32. SDTV YCbCr (0 to 255) to RGB (0 to 255) Table 33. SDTV YCbCr (16 to 235) to RGB (0 to 255)

Table 34. RGB (0 to 255) to HDTV YCbCr (0 to 255) Table 35. RGB (0 to 255) to HDTV YCbCr (16 to 235) Table 36. RGB (0 to 255) to SDTV YCbCr (0 to 255) Table 37. RGB (0 to 255) to SDTV YCbCr (16 to 235)

0.10 MAX

Figure 13. 80-Lead Low Profile Quad Flat Package [LQFP]

Rev. 0 | Page 46 of 48 Notes OBSOLETE

Rev. 0 | Page 47 of 48 NOTES OBSOLETE

Rev. 0 | Page 48 of 48 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05724-0-1/06(0) OBSOLETE