AD9371BBCZ-REEL

AD9371_V01 AD | Alldatasheet

Document overview

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Technical content

Integrated, Dual RF Transceiver with Observation Path Data Sheet AD9371 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Dual differential transmitters (Tx) Dual differential receivers (Rx) Observation receiver (ORx) with 2 inputs Sniffer receiver (SnRx) with 3 inputs Tunable range: 300 MHz to 6000 MHz Tx synthesis bandwidth (BW) to 250 MHz Rx BW: 8 MHz to 100 MHz Supports frequency division duplex (FDD) and time division duplex (TDD) operation Fully integrated independent fractional-N radio frequency (RF) synthesizers for Tx, Rx, ORx, and clock generation JESD204B digital interface

APPLICATIONS

3G/4G micro and macro base stations (BTS) 3G/4G multicarrier picocells FDD and TDD active antenna systems Microwave, nonline of sight (NLOS) backhaul systems GENERAL DESCRIPTION The AD9371 is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTS equipment in both FDD and TDD applications. The AD9371 operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms. The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, eliminating the need for these functions in the digital baseband. Several auxiliary functions such as an auxiliary analog- to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability. An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands. FUNCTIONAL BLOCK DIAGRAM OBSERVATION RxORX1+ ORX1– ORX2+ ORX2– JESD204B JESD204B JESD204BSPIDEV_CLK_IN+, DEV_CLK_IN– CTRL I/F RX_EXTLO+ RX_EXTLO– ADC LPFRX2 ADC LPF RX1RX1+ RX1– LO GENERATOR RF SYNTHESIZER RX2+ RX2– DECIMATION, pFIR, DC OFFSET QEC, TUNING, RSSI, OVERLOAD MICRO- CONTROLLER SPI PORT ADC LPF SNIFFER Rx ADC LPF TX_EXTLO+ TX_EXTLO– DAC LPFTX2 DAC LPF TX1TX1+ TX1– TX2+ TX2– pFIR, QEC, INTERPOLATION GPIO AUXADC AUXDAC CLOCK GENERATOR EXTERNAL OPTION LO GENERATOR RF SYNTHESIZER RF SYNTHESIZER LO GENERATOR EXTERNAL OPTION SNRXA+ SNRXA– SNRXB+ SNRXB– SNRXC+ SNRXC– DECIMATION, pFIR, AGC, DC OFFSET, QEC, TUNING, RSSI, OVERLOAD AD9371 14651-001 NOTES 1. FOR JESD204B PINS, SEE FIGURE 4. Figure 1. The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels. The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the transmitter, the receiver, the observation receiver, and the clock sections. Careful design and layout techniques provide the isolation demanded in high performance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. A 1.3 V supply is required to power the core of the AD9371, and a standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitter and auxiliary converter performance. The AD9371 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

Rev. B | Page 2 of 57 TABLE OF CONTENTS

REVISION HISTORY

3/2017—Rev. A to Rev. B Deleted Figure 230 through Figure 239; Renumbered 11/2016—Rev. 0 to Rev. A Changes to L3, L4 Description Column, Table 6; M3, M4 Description Column, Table 6; and M13, M14 Description Added Figure 230 to Figure 235; Renumbered Sequentially .... 55 7/2016—Revision 0: Initial Version

Rev. B | Page 3 of 57 SPECIFICATIONS Electrical characteristics at ambient temperature range, VDDA_SER = 1.3 V , VDDA_DES = 1.3 V , JESD_VTT_DES = 1.3 V , VDDA_1P31 = include printed circuit board (PCB) and matching circuit losses, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments TRANSMITTERS (Tx) Center Frequency 300 6000 MHz Tx Large Signal Bandwidth (BW) 100 MHz Tx Synthesis BW2 250 MHz Wider bandwidth for use in digital processing algorithms BW Flatness ±0.5 dB 250 MHz BW, compensated by programmable finite infinite response (FIR) filter ±0.15 dB Any 20 MHz BW span, compensated by programmable FIR filter Deviation from Linear Phase 10 Degrees 250 MHz BW Power Control Range 0 42 dB Increased calibration time, reduced QEC 3, LOL4 performance beyond 20 dB Power Control Resolution 0.05 dB ACLR5 (Four Universal Mobile Telecommunications System (UMTS) Carriers) −11.2 dBFS rms, 0 dB RF attenuation

700 MHz Local Oscillator (LO) −64 dB

2600 MHz LO −64 dB

3500 MHz LO −63 dB

5500 MHz LO −61 dB

In-Band Noise −155 dBFS6/Hz Tx to Tx Isolation

700 MHz LO 70 dB

2600 MHz LO 65 dB

3500 MHz LO 65 dB

5500 MHz LO 65 dB

Image Rejection Up to 20 dB RF attenuation, within large signal BW, QEC 3 active

700 MHz LO 65 dB

5500 MHz LO 50 dB

Maximum Output Power 0 dBFS, 1 MHz signal input, 50 Ω load, 0 dB RF attenuation

700 MHz LO 7 dBm

2600 MHz LO 7 dBm

3500 MHz LO 6 dBm

5500 MHz LO 4 dBm

Output Third-Order Intercept Point OIP3 −5 dBFS rms, 0 dB RF attenuation

700 MHz LO 27 dBm

2600 MHz LO 27 dBm

3500 MHz LO 25 dBm

5500 MHz LO 25 dBm

Rev. B | Page 4 of 57 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Carrier Leakage After calibration, LOL correction active, CW7 input signal, 3 dB RF and 3 dB digital attenuation, 40 kHz measurement BW

700 MHz LO −81 dBFS6

2600 MHz LO −81 dBFS6

3500 MHz LO −81 dBFS6

5500 MHz LO −75 dBFS6

Error Vector Magnitude (3GPP Test Signals) EVM Long-term evolution (LTE)

20 MHz downlink,

700 MHz LO −45 dB

2600 MHz LO −39 dB

3500 MHz LO −38.5 dB 5500 MHz LO −37.5 dB Output Impedance 50 Ω Differential RECEIVERS (Rx) Center Frequency 300 6000 MHz Gain Range 0 30 dB Analog Gain Step 0.5 dB BW Ripple ±0.5 dB 100 MHz BW, compensated by programmable FIR filter ±0.2 dB Any 20 MHz span, compensated by programmable FIR filter Rx Bandwidth 8 100 MHz Analog low-pass filter (LPF) BW is 20 MHz minimum, programmable FIR BW configurable over the entire range Rx Alias Band Rejection 75 dB Due to digital filters Maximum Recommended Input Power8 −14 dBm Input is a CW7 signal at a 0 dB attenuation setting; this level increases decibel for decibel with attenuation Noise Figure NF Maximum Rx gain, at Rx port, matching losses de-embedded

700 MHz LO 12 dB

2600 MHz LO 13.5 dB

3500 MHz LO 14 dB

5500 MHz LO 18 dB

Input Third-Order Intercept Point IIP3 Maximum Rx gain, third- order intermodulation (IM3)

1 MHz offset from LO

700 MHz LO 22 dBm

2600 MHz LO 22 dBm

3500 MHz LO 20 dBm

5500 MHz LO 20 dBm

Input Second-Order Intercept Point IIP2 Maximum Rx gain, second- order intermodulation (IM2)

700 MHz LO 65 dBm

2600 MHz LO 65 dBm

3500 MHz LO 65 dBm

5500 MHz LO 57 dBm

Rev. B | Page 5 of 57 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Image Rejection QEC3 active, within Rx BW

700 MHz LO 75 dB

2600 MHz LO 75 dB

3500 MHz LO 75 dB

5500 MHz LO 75 dB

Input Impedance 200 Ω Differential Tx1 to Rx1 Signal Isolation and Tx2 to Rx2 Signal Isolation

700 MHz LO 68 dB

2600 MHz LO 68 dB

3500 MHz LO 62 dB

5500 MHz LO 60 dB

Tx1 to Rx2 Signal Isolation and Tx2 to Rx1 Signal Isolation

2600 MHz LO 70 dB

Rx1 to Rx2 Signal Isolation

700 MHz LO 60 dB

2600 MHz LO 60 dB

3500 MHz LO 60 dB

Rx Band Spurs Referenced to RF Input at Maximum Gain −95 dBm No more than one spur at this level per 10 MHz of Rx BW; excludes harmonics of the reference clock Rx LO Leakage at Rx Input at Maximum Gain Leakage decreases decibel for decibel with attenuation for first 12 dB

700 MHz LO −65 dBm

2600 MHz LO −65 dBm

3500 MHz LO −62 dBm

5500 MHz LO −62 dBm

OBSERVATION RECEIVER (ORx) Center Frequency 300 6000 MHz Gain Range 0 18 dB Analog Gain Step 1 dB BW Ripple ±0.5 dB 250 MHz RF BW, compensated by programmable FIR filter Deviation from Linear Phase 10 Degrees 250 MHz RF BW ORx Bandwidth 250 MHz ORx Alias Band Rejection 60 dB Due to digital filters Maximum Recommended Input Power8 −13 dBm Input is a CW7 signal at 0 dB attenuation setting; this level increases decibel for decibel with attenuation Signal-to-Noise Ratio9 SNR Maximum gain at ORx port 5500 MHz LO 59 dB 200 MHz BW, 245.76 MSPS

Rev. B | Page 6 of 57 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Input Third-Order Intercept Point IIP3 Maximum ORx gain, IM3 1 MHz offset from LO

3500 MHz LO 18 dBm

5500 MHz LO 18 dBm

Input Second-Order Intercept Point IIP2 Maximum ORx gain, IM2

5500 MHz LO 60 dBm

Image Rejection After online tone calibration Input Impedance 200 Ω Differential Tx1 to ORx1 Signal and Tx2 to ORx2 Signal Isolation

3500 MHz LO 70 dB

5500 MHz LO 70 dB

Tx1 to ORx2 Signal and Tx2 to ORx1 Signal Isolation SNIFFER RECEIVER (SnRx) Center Frequency 300 4000 MHz Gain Range 0 52 dB Analog Gain Step 1 dB BW Ripple ±0.5 dB 20 MHz RF BW, compensated by programmable FIR filter Rx Bandwidth 20 MHz Rx Alias Band Rejection 60 dB Due to digital filters Maximum Recommended Input Power8 −26 dBm Input is a CW7 signal at 0 dB attenuation setting Noise Figure NF Maximum gain at SnRx port, matching losses de-embedded, gain control limited to the first 20 steps

700 MHz LO 5 dB

2600 MHz LO 5 dB

3500 MHz LO 7 dB

Input Third-Order Intercept Point IIP3 Maximum gain, IM3 1 MHz offset from LO, gain control limited to the first 20 steps

700 MHz LO 1 dBm

2600 MHz LO 1 dBm

3500 MHz LO 1 dBm

Rev. B | Page 7 of 57 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Input Second-Order Intercept Point IIP2 Maximum gain, IM2 1 MHz offset from LO, gain control limited to the first 20 steps

700 MHz LO 45 dBm

2600 MHz LO 45 dBm

3500 MHz LO 45 dBm

Image Rejection After online tone calibration Input Impedance 400 Ω Differential Tx1 to SnRx Signal and Tx2 to SnRx Signal Isolation Applies to each SnRx input LO Frequency Step 2.3 Hz 1.5 GHz to 3 GHz, 76.8 MHz phase frequency detector (PFD) frequency LO Spectral Purity −80 dBc Excludes integer boundary spurs 1 kHz to 100 MHz Spot Phase Noise

700 MHz LO

10 kHz −104 dBc 100 kHz −107 dBc

1 MHz −133 dBc

2600 MHz LO

10 kHz −93 dBc 100 kHz −97 dBc

1 MHz −123 dBc

3500 MHz LO

10 kHz −91 dBc 100 kHz −97 dBc

5500 MHz LO

10 kHz −98 dBc 100 kHz −100 dBc

1 MHz −110 dBc

Integrated Phase Noise Integrated from 1 kHz to

100 MHz

700 MHz LO 0.20 °rms 2600 MHz LO 0.49 °rms 3500 MHz LO 0.55 °rms 5500 MHz LO 0.75 °rms EXTERNAL LO INPUT Input Frequency fEXTLO 600 8000 MHz Input frequency must be 2× the desired LO frequency Input Signal Power 0 3 6 dBm 50 Ω matching at the source

Rev. B | Page 8 of 57 Parameter Symbol Min Typ Max Unit Test Conditions/Comments REFERENCE CLOCK (DEV_CLK_IN SIGNAL) Frequency Range 10 320 MHz Signal Level 0.3 2.0 V p-p AC-coupled, common-mode voltage (VCM) = 618 mV; for best spurious performance, use a <1 V p-p input clock AUXILIARY CONVERTERS ADC ADC Resolution 12 Bits Input Voltage Minimum 0.25 V Maximum 3.05 V DAC DAC Resolution 10 Bits Includes four offset levels Output Voltage Minimum 0.5 V Reference voltage (V REF) = 1 V Maximum 3.0 V V REF = 2.5 V Drive Capability 10 mA DIGITAL SPECIFICATIONS (CMOS), GPIO_x, RX1_ENABLE, RX2_ENABLE, TX1_ENABLE, TX2 ENABLE, SYNCINBx+, SYNCOUTB0+, GP_INTERRUPT, SDIO, SDO, SCLK, CSB, RESET Logic Inputs Input Voltage High Level VDD_IF × 0.8 VDD_IF V Low Level 0 VDD_IF × 0.2 V Input Current High Level −10 +10 μA Low Level −10 +10 μA Logic Outputs Output Voltage High Level VDD_IF × 0.8 V Low Level VDD_IF × 0.2 V Drive Capability 3 mA DIGITAL SPECIFICATIONS (LVDS), SYSREF_INx, SYNCOUTB0±, SYNCINBx PAIRS Logic Inputs Input Voltage Range 825 1675 mV Each differential input in the pair Input Differential Voltage Threshold −100 +100 mV Receiver Differential Input Impedance 100 Ω Internal termination enabled

Rev. B | Page 9 of 57 Parameter Symbol Min Typ Max Unit Test Conditions/Comments Logic Outputs Output Voltage High 1375 mV Low 1025 mV Differential 225 mV Offset 1200 mV DIGITAL SPECIFICATIONS (CMOS), GPIO_3P3_x SIGNALS Logic Inputs Input Voltage High Level VDDA_3P3 × 0.8 VDDA_3P3 V Low Level 0 VDDA_3P3 × 0.2 V Input Current High Level −10 +10 μA Low Level −10 +10 μA Logic Outputs Output Voltage High Level VDDA_3P3 × 0.8 V Low Level VDDA_3P3 × 0.2 V Drive Capability 4 mA 1 VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO, VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO. 2 Synthesis bandwidth (BW) is the extended bandwidth used by digital correction algorithms to measure conditions and generate compensation. 3 Quadrature error correction (QEC) is the system for minimizing quadrature images of a desired signal. 4 Local oscillator leakage (LOL) is a measure of the amount of the LO signal that is passed from a mixer with the desired signal. 5 Adjacent channel level reduction (ACLR) is a measure of the amount of power from the desired signal leaking into an adjacent channel. 6 dBFS represents the ratio of the actual output signal to the maximum possible output level for a continuous wave output signal at the given RF attenuation setting. 7 Continuous wave (CW) is a single frequency signal. 8 Note that the input signal power limit does not correspond to 0 dBFS at the digital output because of the nature of the continuous time Σ-Δ ADCs. Unlike the hard clipping characteristic of pipeline ADCs, these converters exhibit a soft overload behavior when the input approaches the maximum level. 9 Signal-to-noise ratio is limited by the baseband quantization noise. CURRENT AND POWER CONSUMPTION SPECIFICATIONS Table 2. Parameter Min Typ Max Unit Test Conditions / Comments SUPPLY CHARACTERISTICS VDDA_1P3 Analog Supplies1 1.267 1.3 1.33 V VDIG Supply 1.267 1.3 1.33 V VDDA_1P8 Supply 1.71 1.8 1.89 V VDDA_3P3 Supply 3.135 3.3 3.465 V VDDA_SER, VDDA_DES, JESD_VTT_DES Supplies 1.14 1.3 1.365 V POSITIVE SUPPLY CURRENT (Rx MODE) Two Rx channels enabled, Tx upconverter disabled, 100 MHz Rx BW, 122.88 MSPS data rate VDDA_1P3 Analog Supplies1 1055 mA VDIG Supply 625 mA Rx QEC 2 enabled, QEC2 engine active VDD_IF Supply (CMOS and LVDS) 8 mA VDDA_3P3 Supply 1 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA VDDA_SER, VDDA_DES, JESD_VTT_DES Supplies 375 mA Total Power Dissipation 2.70 W

Rev. B | Page 10 of 57 Parameter Min Typ Max Unit Test Conditions / Comments POSITIVE SUPPLY CURRENT (Tx MODE) Two Tx channels enabled, Rx downconverter disabled, 200 MHz Tx BW, 245.76 MSPS data rate (ORx disabled) VDDA_1P3 Analog Supplies1 1000 mA VDIG Supply 410 mA Tx QEC 2 active VDDA_1P8 Supply Full-scale CW 3 405 mA Tx RF attenuation = 0 dB, 80 mA Tx RF attenuation = 15 dB VDD_IF Supply 8 mA VDDA_3P3 Supply 1 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA VDDA_SER, VDDA_DES, JESD_VTT_DES Supplies 375 mA Total Power Dissipation Typical supply voltages, Tx QEC 2 active

3.70 W Tx RF attenuation = 0 dB

3.11 W Tx RF attenuation = 15 dB

POSITIVE SUPPLY CURRENT (FDD MODE), 2× Rx, 2× Tx, ORx ACTIVE 100 MHz Rx BW, 122.88 MSPS data rate; 200 MHz Tx BW, 245.76 MSPS data rate; 200 MHz ORx BW, 245.76 MSPS data rate VDDA_1P3 Analog Supplies1 1700 mA VDIG Supply 1080 mA Tx QEC 2 active VDDA_1P8 Supply Full-scale CW 3 405 mA Tx RF attenuation = 0 dB 80 mA Tx RF attenuation = 15 dB VDD_IF Supply 8 mA VDDA_3P3 Supply 2 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA VDDA_SER, VDDA_DES, JESD_VTT_DES Supplies 375 mA Total Power Dissipation Typical supply voltages, Tx QEC 2 active

4.86 W Tx RF attenuation = 0 dB

4.27 W Tx RF attenuation = 15 dB

MAXIMUM OPERATING JUNCTION TEMPERATURE 110 °C Device designed for 10-year lifetime when operating at maximum junction temperature 1 VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO, VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO. 2 QEC is the system for minimizing quadrature images of a desired signal. 3 Continuous wave (CW) is a single frequency signal. TIMING SPECIFICATIONS Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SERIAL PERIPHERAL INTERFACE (SPI) TIMING SCLK Period tCP 20 ns SCLK Pulse Width tMP 10 ns CSB Setup to First SCLK Rising Edge tSC 3 ns Last SCLK Falling Edge to CSB Hold tHC 0 ns SDIO Data Input Setup to SCLK tS 2 ns SDIO Data Input Hold to SCLK tH 0 ns SCLK Falling Edge to Output Data Delay (3- or 4-Wire Mode) t CO 3 8 ns Bus Turnaround Time After Baseband Processor (BBP) Drives Last Address Bit tHZM t H t CO ns Bus Turnaround Time After AD9371 Drives Last Address Bit t HZS 0 t CO ns DIGITAL TIMING TXx_ENABLE Pulse Width 10 μs RXx_ENABLE Pulse Width 10 μs

VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO. Table 5. Thermal Resistance 1 Power dissipation is 3.0 W for all test cases. 2 Per JEDEC JESD51-7 for JEDEC JESD51-5 2S2P test board. 3 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 4 Per MIL-STD 883, Method 1012.1. 5 JEDEC entries refer to the JEDEC JESD51-9 (high K thermal test board).

Figure 4. Pin Configuration Table 6. Pin Function Descriptions connect if these pins are unused.

Rev. B | Page 14 of 57 Pin No. Type1 Mnemonic Description A12, A13 I ORX1+, ORX1− Differential Input for Observation Receiver 1. Do not connect if these pins are unused. B1 I VDDA_RXRF 1.3 V Supply Input. B7, B8 I/O RX_EXTLO−, RX_EXTLO+ Differential Rx External LO Input/Output. If used for external LO, the input frequency must be 2× the desired carrier frequency. Do not connect if these pins are unused. B14 I VDDA_3P3 Supply Voltage for GPIO_3P3_x. C1, C2, C13, D1, D5, D12 to D14, E1, E14, F1, F14 I/O GPIO_3P3_0 to GPIO_3P3_11 General-Purpose Inputs and Outputs Referenced to 3.3 V Supply. See Figure 4 to match the ball location to the GPIO_3P3_x signal name. Some GPIO_3P3_x pins can also function as auxiliary DAC outputs. C3 O VSNRX_VCO_LDO Sniffer VCO LDO 1.1 V Output. Bypass this pin with a 1 μF capacitor. C4 I VDDA_SNRXVCO 1.3 V Supply Input for Sniffer VCO Low Dropout (LDO) Regulator. C6 I VDDA_RXLO 1.3 V Supply for the Rx Synthesizer LO Generator. This pin is sensitive to aggressors. C7 I VDDA_RXVCO 1.3 V Supply Input for Receiver VCO LDO Regulator. C8 O VRX_VCO_LDO Receiver VCO LDO 1.1 V Output. Bypass this pin with a 1 μF capacitor. C11 I AUXADC_1 Auxiliary ADC 1 Input Pin. C12 I AUXADC_2 Auxiliary ADC 2 Input Pin. C14 N/A RBIAS Bias Resistor Connection. This pin generates an internal current based on an external 1% resistor. Connect a 14.3 kΩ resistor between this pin and ground (VSSA). D2, E2 I SNRXC−, SNRXC+ Differential Input for Sniffer Receiver Input C. If these pins are unused, connect to VSSA with a short or with a 1 kΩ resistor. D3, E3 I SNRXB−, SNRXB+ Differential Input for Sniffer Receiver Input B. If these pins are unused, connect to VSSA with a short or with a 1 kΩ resistor. D4, E4 I SNRXA−, SNRXA+ Differential Input for Sniffer Receiver Input A. If these pins are unused, connect to VSSA with a short or with a 1 kΩ resistor. D10 I VDDA_1P8 1.8 V Tx Supply. D11 I AUXADC_3 Auxiliary ADC 3 Input Pin. E5 I VDDA_BB 1.3 V Supply Input for ADCs, DACs, and Auxiliary ADCs. E7, E8 I DEV_CLK_IN+, DEV_CLK_IN− Device Clock Differential Input. E11, E12 I/O TX_EXTLO−, TX_EXTLO+ Differential Tx External LO Input/Output. If these pins are used for the external LO, the input frequency must be 2× the desired carrier frequency. Do not connect if these pins are unused. E13 I AUXADC_0 Auxiliary ADC 0 Input Pin. F2 I VDDA_RXTX 1.3 V Supply Input for Tx/Rx Baseband Circuits, Transimpedance Amplifier (TIA), Tx Transconductance (Gm), Baseband Filters, and Auxiliary DACs. F11 I VDDA_TXVCO 1.3 V Supply Input for Transmitter VCO LDO Regulator. F12 I VDDA_TXLO 1.3 V Supply for the Tx Synthesizer LO Generator. This pin is sensitive to aggressors. F13 O VTX_VCO_LDO Transmitter VCO LDO 1.1 V Output. Bypass this pin with a 1 μF capacitor. G4 I VDDA_CALPLL 1.3 V Supply Input for Calibration PLL Circuits. Use a separate trace on the PCB back to a common supply point. G6 I VDDA_CLKSYNTH 1.3 V Clock Synthesizer Supply Input. This pin is sensitive to aggressors. G7 I VDDA_SNRXSYNTH 1.3 V Sniffer Rx Synthesizer Supply Input. This pin is sensitive to aggressors. G8 I VDDA_TXSYNTH 1.3 V Tx Synthesizer Supply Input. This pin is sensitive to aggressors. G9 I VDDA_RXSYNTH 1.3 V Rx Synthesizer Supply Input. This pin is sensitive to aggressors.

Rev. B | Page 15 of 57 Pin No. Type1 Mnemonic Description H1, J1 O TX2−, TX2+ Differential Output for Transmitter 2. H11, H12, J3, J7, J8, J11, J12, K5 to K8, K11, K12, L5, L6, L11, L12, M10, M11 I/O GPIO_0 to GPIO_18 General-Purpose Inputs and Outputs Referenced to VDD_IF. See Figure 4 to match the ball location to the GPIO_x signal name. H14, J14 O TX1+, TX1− Differential Output for Transmitter 1. J4 I RESET Active Low Chip Reset. J5 O GP_INTERRUPT General-Purpose Interrupt Signal. J6 I TEST Test Pin Used for JTAG Boundary Scan. Ground this pin if unused. J9 I/O SDIO Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire Mode. J10 O SDO Serial Data Output. K3, K4 I SYSREF_IN+, SYSREF_IN− LVDS SYSREF Clock Inputs for the JESD204B Interface. K9 I SCLK Serial Data Bus Clock. K10 I CSB Serial Data Bus Chip Select. Active low. L3, L4 I SYNCINB1−, SYNCINB1+ LVDS Sync Signal Associated with ORx/Sniffer Channel Data on the JESD204B Interface. Alternatively, these pins can be set to a CMOS input using SYNCINB1+ as the input and connecting SYNCINB1− with a 1 kΩ resistor to GND. L7, L10 I VSSD Digital Ground. L8, L9 I VDIG 1.3 V Digital Core Supply. Use a separate trace on the PCB back to a common supply point. M1 O VCLK_VCO_LDO Clock VCO LDO 1.1 V Output. Bypass this pin with a 1 μF capacitor. M3, M4 I SYNCINB0−, SYNCINB0+ LVDS Sync Signal Associated with Rx Channel Data on the JESD204B Interface. Alternatively, these pins can be set to a CMOS input using SYNCINB0+ as the input and connecting SYNCINB0− with a 1 kΩ resistor to GND. M5 I RX1_ENABLE Enables Rx Channel 1 Signal Path. M6 I TX1_ENABLE Enables Tx Channel 1 Signal Path. M7 I RX2_ENABLE Enables Rx Channel 2 Signal Path. M8 I TX2_ENABLE Enables Tx Channel 2 Signal Path. M12 I VDD_IF CMOS/LVDS Interface Supply. M13, M14 O SYNCOUTB0+, SYNCOUTB0− LVDS Sync Signal Associated with Transmitter Channel Data on the JESD Interface. Alternatively, these pins can be set to a CMOS output using SYNCOUTB0+ as the output while leaving SYNCOUTB0− floating. N1 I VDDA_CLK 1.3 V Clock Supply Input. N3, N4 O SERDOUT3−, SERDOUT3+ RF Current Mode Logic (CML) Differential Output 3. This JESD204B lane can be used by the receiver data or by the sniffer/observation receiver data. N5, N6 O SERDOUT2−, SERDOUT2+ RF CML Differential Output 2. This JESD204B lane can be used by the receiver data or by the sniffer/observation receiver data. N8, P8 I VDDA_SER JESD204B 1.3 V Serializer Supply Input. N9 I VDDA_DES JESD204B 1.3 V Deserializer Supply Input. N10, N11 I SERDIN2−, SERDIN2+ RF CML Differential Input 2. N12, N13 I SERDIN3−, SERDIN3+ RF CML Differential Input 3. P4, P5 O SERDOUT1−, SERDOUT1+ RF CML Differential Output 1. This JESD204B lane can be used by receiver data or by sniffer/observation receiver data. P6, P7 O SERDOUT0−, SERDOUT0+ RF CML Differential Output 0. This JESD204B lane can be used by receiver data or by sniffer/observation receiver data. P9 I JESD_VTT_DES JESD204B Deserializer Termination Supply Input. P11, P12 I SERDIN0−, SERDIN0+ RF CML Differential Input 0. P13, P14 I SERDIN1−, SERDIN1+ RF CML Differential Input 1. 1 I is input, O is output, I/O is input/output, and N/A is not applicable.

700 MHz BAND

Temperature settings refer to the die temperature. The die temperature is 40°C for single trace plots. Figure 5. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency, Figure 6. Receiver Noise Figure vs. Receiver Attenuation, 700 MHz LO, Figure 7. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver Figure 8. Receiver IIP2 vs. f1 Offset Frequency, 900 MHz LO, 0 dB Attenuation, Figure 9. Receiver IIP2 vs. Intermodulation Frequency, 900 MHz LO, Figure 10. Receiver IIP3 vs. F1 Offset Frequency, 900 MHz LO,

30.72 MSPS Sample Rate

Figure 11. Receiver IIP3 vs. Intermodulation Frequency, 900 MHz LO, Figure 12. Receiver Image vs. Receiver Attenuation, 800 MHz LO, Continuous Figure 13. Receiver Gain vs. Receiver Attenuation, 800 MHz LO, CW Signal Figure 14. Receiver DC Offset vs. Receiver Attenuation, 800 MHz LO, Figure 15. Receiver HD2 vs. Receiver Attenuation, 800 MHz LO, CW Signal

3 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel for

Figure 16. Receiver HD3 vs. Receiver Attenuation, 800 MHz LO, CW Signal

Figure 17. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power,

900 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,

Figure 18. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency,

100 MHz RF Bandwidth, CW Tone 3 MHz Offset from LO

Figure 19. Receiver Noise Figure vs. Close-In Interferer Signal Power,

703 MHz LO, 709 MHz CW Interferer, NF Integrated over 7 MHz to 10 MHz,

20 MHz RF Bandwidth

Figure 20. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power,

703 MHz LO, 901 MHz CW Interferer, NF Integrated Over 7 MHz to 10 MHz,

Figure 21. Transmitter Image vs. RF Attenuation, 20 MHz RF Bandwidth,

900 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run with

Figure 22. Transmitter Image vs. Desired Offset Frequency,

20 MHz RF Bandwidth, 900 MHz LO, 0 dB RF Attenuation, Transmitter

Figure 23. Tx Output Power, Transmitter QEC, and External LO Leakage

122.88 MSPS Sample Rate

Figure 24. Transmitter LO Leakage vs. RF Attenuation, 900 MHz LO, Transmitter Figure 25. Transmitter LO Leakage vs. Offset Frequency, Figure 26. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,

20 MHz Receiver RF Bandwidth, 20 MHz Transmitter RF Bandwidth,

Figure 27. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency, 20 MHz Receiver RF Figure 28. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,

20 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO

Figure 29. Transmitter Noise vs. RF Attenuation, 800 MHz LO,

20 MHz Offset Frequency

Figure 30. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation, 900 MHz LO,

20 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal, Transmitter

Figure 31. Tx Alternate Channel Leakage Ratio vs. RF Attenuation,

900 MHz LO, 20 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,

Figure 32. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,

710 MHz LO

Figure 33. Tx Integrated Phase Noise vs. Transmitter LO Frequency,

20 MHz RF Bandwidth, CW 20 MHz Offset from LO, 3 dB Digital Backoff

Figure 34. Transmitter OIP3 vs. RF Attenuation, 800 MHz LO,

20 MHz RF Bandwidth, f1 = 10 MHz, f2 = 11 MHz, 3 dB Digital Backoff,

Figure 35. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff,

20 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,

122.88 MSPS Sample Rate, Test Equipment Noise Floor De-Embedded

Figure 36. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff, Figure 37. Transmitter EVM vs. RF Attenuation, 900 MHz LO, Figure 38. Transmitter HD2 vs. RF Attenuation, 800 MHz LO,

810 MHz CW Desired Signal, 20 MHz RF Bandwidth,

Figure 39. Transmitter HD3 vs. RF Attenuation, 800 MHz LO, Figure 40. Transmitter Output Power vs. RF Attenuation, 800 MHz LO,

Figure 41. Tx Attenuation Step Error vs. RF Attenuation, 800 MHz LO, Figure 42. Transmitter Frequency Response Deviation from Flatness vs. Figure 43. Observation Receiver LO Leakage vs. Observation Receiver LO Figure 44. Observation Receiver Noise Figure vs. Observation Receiver LO

122.88 MSPS Sample Rate, 100 MHz Integration Bandwidth

Figure 45. Observation Receiver IIP2 vs. f1 Offset Frequency, 900 MHz LO, Figure 46. Observation Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),

900 MHz LO, 0 dB Attenuation, 100 MHz RF Bandwidth,

Figure 47. Observation Receiver IIP3 vs. f1 Offset Frequency, 900 MHz LO, Figure 48. Observation Receiver IIP3 vs. Intermodulation Frequency (2f2 − f1), Figure 49. Observation Receiver Image vs. Observation Receiver Attenuation,

800 MHz LO, CW Signal 16 MHz Offset, 100 MHz RF Bandwidth, BTC Active,

Figure 50. Observation Receiver Gain vs. Observation Receiver Attenuation,

800 MHz LO, CW Signal 16 MHz Offset, 100 MHz RF Bandwidth,

Figure 51. Observation Receiver DC Offset vs. Observation Receiver Figure 52. Observation Receiver HD2 vs. Observation Receiver Attenuation,

800 MHz LO, CW Signal 16 MHz Offset, −20 dBm at 0 dB Attenuation,

Figure 53. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 54. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency, Figure 55. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency,

20 MHz Integration Bandwidth

Figure 56. Sniffer Receiver IIP2 vs. Intermodulation Frequency (f2 − f1), Figure 57. Sniffer Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), 600 MHz Figure 58. Sniffer Receiver Image vs. Sniffer Receiver Attenuation,

600 MHz LO, CW Signal 3 MHz Offset, 20 MHz RF Bandwidth,

Figure 59. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation,

600 MHz LO, CS Signal 3 MHz Offset, −35 dBm at 0 dB Attenuation,

Figure 60. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, 600 MHz LO, Figure 61. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 600 MHz LO, Figure 62. Sniffer Receiver EVM vs. Sniffer Receiver Input Power, 600 MHz LO,

20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC, BTC Active,

Figure 63. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,

2.6 GHz BAND

Figure 64. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency, Figure 65. Receiver Noise Figure vs. Receiver Attenuation, 2600 MHz LO, Figure 66. Receiver Noise Figure vs. Receiver LO Frequency, Figure 67. Receiver IIP2 vs. f1 Offset Frequency, 2600 MHz LO, Figure 68. Receiver IIP2 vs. Intermodulation Frequency, 2600 MHz LO, Figure 69. Receiver IIP3 vs. f1 Offset Frequency, 2600 MHz LO,

Figure 76. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power,

2600 MHz LO, 40 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,

Figure 77. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, 40 MHz Figure 78. Receiver Noise Figure vs. Close-In Interferer Signal Power,

2614 MHz LO, 2625 MHz CW Interferer, Noise Figure Integrated over

7 MHz to 10 MHz, 40 MHz RF Bandwidth

Figure 79. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power,

2614 MHz LO, 2435 MHz CW Interferer, Noise Figure Integrated over

7 MHz to 10 MHz

Figure 80. Transmitter Image vs. RF Attenuation, 40 MHz RF Bandwidth,

2600 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run

Figure 81. Transmitter Image vs. Desired Offset Frequency, 40 MHz RF

Figure 82. Tx Output Power, Transmitter QEC, and External LO Leakage Active,

5 MHz CW Offset Signal, 1 MHz Resolution Bandwidth,

245.76 MSPS Sample Rate

Figure 83. Transmitter LO Leakage vs. RF Attenuation, 2300 MHz LO, Figure 84. Transmitter LO Leakage vs. Offset Frequency, External Transmitter

1 MHz Measurement Bandwidth

Figure 85. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,

40 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,

Figure 86. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency, Figure 87. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,

40 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO

Figure 88. Transmitter Noise vs. RF Attenuation, 2600 MHz LO,

10 MHz Offset Frequency

Figure 89. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation,

2600 MHz LO, 40 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,

Figure 90. Tx Alternate Channel Leakage Ratio vs. RF Attenuation, Figure 91. LO Phase Noise vs. Offset Frequency, Figure 92. Tx Integrated Phase Noise vs. Transmitter LO Frequency,

40 MHz RF Bandwidth, Continuous Wave 20 MHz Offset from LO,

Figure 93. Transmitter OIP3 vs. RF Attenuation, 2600 MHz LO,

40 MHz RF Bandwidth, f1 = 20 MHz, f2 = 21 MHz, 3 dB Digital Backoff,

Figure 94. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff, 40 MHz Figure 95. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff,

40 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active,

Figure 96. Transmitter EVM vs. RF Attenuation, 2550 MHz LO, Transmitter LO Figure 97. Transmitter HD2 vs. RF Attenuation, 2600 MHz LO,

2605 MHz CW Desired Signal, 40 MHz RF Bandwidth,

Figure 98. Transmitter HD3 vs. RF Attenuation, 2600 MHz LO, Figure 99. Transmitter Output Power vs. RF Attenuation, 2600 MHz LO,

Figure 100. Tx Attenuation Step Error vs. RF Attenuation, 2600 MHz LO,

2610 MHz CW Desired Signal, 40 MHz RF Bandwidth,

Figure 101. Transmitter Frequency Response Deviation from Flatness vs. Figure 102. Observation Receiver LO Leakage vs. Observation Receiver Figure 103. Observation Receiver Noise Figure vs. Observation Receiver

245.76 MSPS Sample Rate, 100 MHz Integration Bandwidth

Figure 104. Observation Receiver IIP2 vs. f1 Offset Frequency, 2600 MHz LO, Figure 105. Observation Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),

2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,

Figure 106. Observation Receiver IIP3 vs. f1 Offset Frequency, Figure 107. Observation Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), Figure 108. Observation Receiver Image vs. Observation Receiver Attenuation,

2600 MHz LO, CW Signal 25 MHz Offset, 200 MHz RF Bandwidth, BTC Active,

Figure 109. Observation Receiver Gain vs. Observation Receiver Attenuation,

2600 MHz LO, CW Signal 25 MHz Offset,

Figure 110. Observation Receiver DC Offset vs. Observation Receiver Figure 111. Observation Receiver HD2 vs. Observation Receiver Attenuation,

2600 MHz LO, CW Signal 25 MHz Offset, −20 dBm at 0 dB Attenuation,

Figure 112. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 113. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency, Figure 114. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency, Figure 115. Sniffer Receiver IIP2 vs. Intermodulation Frequency (f2 − f1), Figure 116. Sniffer Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), 2600 MHz Figure 117. Sniffer Receiver Image vs. Sniffer Receiver Attenuation, 2600 MHz

Figure 118. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation,

2600 MHz LO, CW Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation,

Figure 119. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, Figure 120. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 2600 MHz LO, Figure 121. Sniffer Receiver EVM vs. Sniffer Receiver Input Power,

2600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,

Figure 122. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,

2600 MHz LO, CW Signal 1 MHz Offset, 20 MHz RF Bandwidth,

3.5 GHz BAND

Figure 123. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency, Figure 124. Receiver Noise Figure vs. Receiver Attenuation, 3500 MHz LO, Figure 125. Receiver Noise Figure vs. Receiver LO Frequency,

50 MHz Integration Bandwidth (Includes 1 dB Matching Circuit Loss)

Figure 126. Receiver IIP2 vs. f1 Offset Frequency, 3500 MHz LO,

153.6 MSPS Sample Rate

Figure 127. Receiver IIP2 vs. Intermodulation Frequency, 3500 MHz LO, Figure 128. Receiver IIP3 vs. f1 Offset Frequency, 3500 MHz LO,

Figure 129. Receiver IIP3 vs. Intermodulation Frequency, 3500 MHz LO, Figure 130. Receiver Image vs. Receiver Attenuation, 3500 MHz LO, Figure 131. Receiver Gain vs. Receiver Attenuation, 3500 MHz LO, CW Signal

17 MHz Offset, 100 MHz RF Bandwidth, De-Embedded to Receiver Port,

Figure 132. Receiver DC Offset vs. Receiver Attenuation, 3500 MHz LO, Figure 133. Receiver HD2 vs. Receiver Attenuation, 3500 MHz LO, CW Signal

17 MHz Offset, −14 dBm at 0 dB Attenuation, Input Power Increasing Decibel for

Figure 134. Receiver HD3 vs. Receiver Attenuation, 3500 MHz LO, CW Signal

17 MHz Offset, −14 dBm at 0 dB Attenuation, Input Power Increasing Decibel

Figure 135. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power,

3600 MHz LO, 100 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,

Figure 136. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, Figure 137. Receiver Noise Figure vs. Close-In Interferer Signal Power,

3614 MHz LO, 3625 MHz CW Interferer, Noise Figure Integrated over

7 MHz to 10 MHz, 100 MHz RF Bandwidth

Figure 138. Receiver Noise Figure vs. Out of Band Interferer Signal Power,

3614 MHz LO, 3665 MHz CW Interferer, Noise Figure Integrated over

Figure 139. Transmitter Image vs. RF Attenuation, 100 MHz RF Bandwidth,

3550 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run

Figure 140. Transmitter Image vs. Desired Offset Frequency, 100 MHz RF

Figure 141. Tx Output Power, Transmitter QEC and Figure 142. Transmitter LO Leakage vs. RF Attenuation, 3550 MHz LO, Figure 143. Transmitter LO Leakage vs. Offset Frequency, Figure 144. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,

100 MHz Receiver RF Bandwidth, 100 MHz Transmitter RF Bandwidth,

Figure 145. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency, Figure 146. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,

100 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO

Figure 147. Transmitter Noise vs. RF Attenuation, 3500 MHz LO,

100 MHz Offset Frequency, Zeros Input Data

Figure 148. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation,

3500 MHz LO, 100 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,

Figure 149. Tx Alternate Channel Leakage Ratio vs. RF Attenuation, Figure 150. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff, Figure 151. Tx Integrated Phase Noise vs. Transmitter LO Frequency,

100 MHz RF Bandwidth, CW 20 MHz Offset from LO, 3 dB Digital Backoff

Figure 152. Transmitter OIP3 vs. RF Attenuation, 3500 MHz LO,

100 MHz RF Bandwidth, f1 = 20 MHz, f2 = 21 MHz, 3 dB Digital Backoff,

307.2 MSPS Sample Rate

Figure 153. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff,

100 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active,

Figure 154. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff,

307.2 MSPS Sample Rate (Noise Floor Includes Test Equipment Response)

Figure 155. Transmitter EVM vs. RF Attenuation, 3500 MHz LO, Figure 156. Transmitter HD2 vs. RF Attenuation, 3500 MHz LO,

3505 MHz CW Desired Signal, 100 MHz RF Bandwidth,

Figure 157. Transmitter HD3 vs. RF Attenuation, 3500 MHz LO, Figure 158. Transmitter Output Power vs. RF Attenuation, 3500 MHz LO,

Figure 159. Tx Attenuation Step Error vs. RF Attenuation, 3500 MHz LO,

3510 MHz CW Desired Signal, 100 MHz RF Bandwidth,

Figure 160. Transmitter Frequency Response Deviation from Flatness vs. Figure 161. Observation Receiver LO Leakage vs. Observation Receiver Figure 162. Observation Receiver Noise Figure vs. Observation Receiver LO

307.2 MSPS Sample Rate, 120 MHz Integration Bandwidth

Figure 163. Observation Receiver IIP2 vs. f1 Offset Frequency, 3600 MHz LO, Figure 164. Observation Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),

3500 MHz LO, 0 dB Attenuation, 240 MHz RF Bandwidth,

Figure 165. Observation Receiver IIP3 vs. f1 Offset Frequency, 3600 MHz LO, Figure 166. Observation Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), Figure 167. Observation Receiver Image vs. Observation Receiver Attenuation,

3500 MHz LO, CW Signal 25 MHz Offset, 240 MHz RF Bandwidth, BTC Active,

Figure 168. Observation Receiver Gain vs. Observation Receiver Attenuation,

3500 MHz LO, CW Signal 25 MHz Offset, 240 MHz RF Bandwidth,

Figure 169. Observation Receiver DC Offset vs. Observation Receiver Figure 170. Observation Receiver HD2 vs. Observation Receiver Attenuation,

3500 MHz LO, CW Signal 25 MHz Offset, −20 dBm at 0 dB Attenuation,

Figure 171. Observation Receiver HD3 vs. Observation Receiver Attenuation, Figure 172. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency, Figure 173. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency,

10 MHz Integration Bandwidth

Figure 174. Sniffer Receiver IIP2 vs. Intermodulation Frequency (f2 − f1), Figure 175. Sniffer Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), Figure 176. Sniffer Receiver Image vs. Sniffer Receiver Attenuation,

3500 MHz LO, CW Signal 5 MHz Offset, 20 MHz RF Bandwidth,

38.4 MSPS Sample Rate

Figure 177. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation,

3500 MHz LO, CW Signal 5 MHz Offset, −35 dBm at 0 dB Attenuation,

Figure 178. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, Figure 179. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, Figure 180. Sniffer Receiver EVM vs. Sniffer Receiver Input Power,

3600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,

Figure 181. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,

3600 MHz LO, CW Signal 5 MHz Offset, 20 MHz RF Bandwidth,

5.5 GHz BAND

Figure 182. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency, Figure 183. Receiver Noise Figure vs. Receiver Attenuation, 5600 MHz LO, Figure 184. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver Figure 185. Receiver IIP2 vs. f1 Offset Frequency, 5600 MHz LO, Figure 186. Receiver IIP2 vs. Intermodulation Frequency, 5600 MHz LO, Figure 187. Receiver IIP3 vs. f1 Offset Frequency, 5600 MHz LO, 0 dB Attenuation,

Figure 188. Receiver IIP3 vs. Intermodulation Frequency, 5600 MHz LO, Figure 189. Receiver Image vs. Receiver Attenuation, 5600 MHz LO, Figure 190. Receiver Gain vs. Receiver Attenuation, 5600 MHz LO, Figure 191. Receiver DC Offset vs. Receiver Attenuation, 5850 MHz LO, Figure 192. Receiver HD2 vs. Receiver Attenuation, 5600 MHz LO, Figure 193. Receiver HD3 vs. Receiver Attenuation, 5600 MHz LO,

Figure 194. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power,

5600 MHz LO, 100 MHz RF Bandwidth LTE, 20 MHz Uplink Centered at DC,

Figure 195. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, Figure 196. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power,

5400 MHz LO, 5600 MHz CW Interferer, NF Integrated over 7 MHz to 10 MHz

Figure 197. Transmitter Image vs. RF Attenuation, 75 MHz RF Bandwidth,

5600 MHz LO, 0 dB RF Attenuation, Transmitter Quadrature Error Correction

Figure 198. Transmitter Image vs. Desired Offset Frequency, 75 MHz RF Figure 199. Tx Output Power, Transmitter QEC, and External LO Leakage

Figure 200. Transmitter LO Leakage vs. RF Attenuation, 5600 MHz LO,

10 MHz Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Bandwidth

Figure 201. Transmitter LO Leakage vs. Offset Frequency, Figure 202. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency, 100 MHz Receiver RF Figure 203. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency,

100 MHz Receiver RF Bandwidth, 75 MHz Transmitter RF Bandwidth,

Figure 204. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,

75 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO

Figure 205. Transmitter Noise vs. RF Attenuation, 5600 MHz LO,

1 MHz Offset Frequency

Figure 206. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation,

5600 MHz LO, 75 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,

Figure 207. Tx Alternate Channel Leakage Ratio vs. RF Attenuation, Figure 208. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,

5850 MHz LO

Figure 209. Tx Integrated Phase Noise vs. Transmitter LO Frequency,

75 MHz RF Bandwidth, CW 10 MHz Offset from LO, 3 dB Digital Backoff

Figure 210. Transmitter OIP3 vs. RF Attenuation, 5600 MHz LO,

75 MHz RF Bandwidth, f1 = 20 MHz, f2 = 21 MHz, 3 dB Digital Backoff,

Figure 211. Tx Output Power Spectrum, 3 dB Digital and 1 dB RF Backoff,

40 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,

Figure 212. Tx Output Power Spectrum, 3 dB Digital and 1 dB RF Backoff, Figure 213. Transmitter EVM vs. RF Attenuation, 5600 MHz LO, Transmitter Figure 214. Transmitter HD2 vs. RF Attenuation, 5850 MHz LO, 5855 MHz Figure 215. Transmitter HD3 vs. RF Attenuation, 5850 MHz LO,

5855 MHz CW Desired Signal, 75 MHz RF Bandwidth,

Figure 216. Transmitter Output Power vs. RF Attenuation, 5850 MHz LO, Figure 217. Tx Attenuation Step Error vs. RF Attenuation, 5850 MHz LO,

Figure 218. Transmitter Frequency Response Deviation from Flatness vs. Figure 219. Observation Receiver LO Leakage vs. Observation Receiver Figure 220. Observation Receiver Noise Figure vs. Observation Receiver Figure 221. Observation Receiver IIP2 vs. f1 Offset Frequency, 5600 MHz LO, Figure 222. Observation Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),

5600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,

Figure 223. Observation Receiver IIP3 vs. f1 Offset Frequency, 5600 MHz LO,

Figure 224. Observation Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), Figure 225. Observation Receiver Image vs. Observation Receiver Figure 226. Observation Receiver Gain vs. Observation Receiver Attenuation,

5600 MHz LO, CW Signal 30 MHz Offset,

Figure 227. Observation Receiver DC Offset vs. Observation Receiver Figure 228. Observation Receiver HD2 vs. Observation Receiver Attenuation,

5600 MHz LO, CW Signal 30 MHz Offset, −15 dBm Input, Input Power

Figure 229. Observation Receiver HD3 vs. Observation Receiver Attenuation,

Rev. B | Page 54 of 57 THEORY OF OPERATION The AD9371 is a highly integrated RF transceiver that can be configured for a wide range of applications. The device integrates all the RF, mixed-signal, and digital blocks necessary to provide transmit and receive functions in a single device. Programmability allows the two receiver channels and two transmitter channels to be used in TDD and FDD systems for 3G and 4G cellular standards. The observation receiver channel has two inputs for use in monitoring the transmitter outputs. This channel has a wide channel bandwidth that receives the entire transmit band and feeds it back to the digital section for error correction purposes. In addition, three sniffer receiver inputs can monitor different radio frequency bands (one at a time). These channels share the baseband ADC and digital processing with the two ORx inputs. The AD9371 contains four high speed serial interface links for the transmit chain and four high speed serial interface links shared by the Rx, ORx, and SnRx channels (JESD204B, Subclass 1 compliant), providing a low pin count and reliable data interface to a field-programmable gate array (FPGA) or other custom integrated baseband solutions. The AD9371 also provides self calibration for dc offset, LO leakage, and quadrature error correction using an integrated microcontroller core to maintain a high performance level under varying temperatures and input signal conditions. Firmware is supplied with the device to schedule all calibrations with no user interaction. The device includes test modes that allows system designers to debug designs during prototyping and optimize radio configurations. TRANSMITTER (Tx) The AD9371 employs a direct conversion transmitter architecture consisting of two identical and independently controlled channels that provide all the digital processing, mixed signal, and RF blocks necessary to implement a direct conversion system. Both channels share a common frequency synthesizer. The digital data from the JESD204B lanes pass through a fully programmable 96-tap FIR filter with optional interpolation. The FIR output is sent to a series of conversion filters that provide additional filtering and data rate interpolation prior to reaching the DAC. Each DAC has an adjustable sample rate and is linear up to full scale. When converted to baseband analog signals, the in-phase (I) and quadrature (Q) signals are filtered to remove sampling artifacts, and then the signals are fed to the upconversion mixers. At the mixer stage, the I and Q signals are recombined and modulated onto the carrier frequency for transmission to the output stage. Each transmit chain provides a wide attenuation adjustment range with fine granularity to help designers optimize SNR. RECEIVER (Rx) The AD9371 contains dual receiver channels. Each Rx channel is a direct conversion system that contains a programmable attenuator stage, followed by matched I and Q mixers that downconvert received signals to baseband for digitization. To achieve gain control, a programmed gain index map is implemented. This gain map distributes attenuation among the various Rx blocks for optimal performance at each power level. In addition, support is available for both automatic and manual gain control modes. The receiver includes Σ-Δ ADCs and adjustable sample rates that produce data streams from the received signals. The signals can be conditioned further by a series of decimation filters and a fully programmable 72-tap FIR filter with additional decimation settings. The sample rate of each digital filter block is adjustable by changing the decimation factors to produce the desired output data rate. OBSERVATION RECEIVER (ORx) The ORx operates in a similar manner to the main receivers. Each input is differential and uses a dedicated mixer. The ORx inputs share a baseband ADC and baseband section; therefore, only one can be active at any time. The mixed-signal and digital section is identical in design and operation to the main receiver channels. This channel can monitor the Tx channels and implement error correction functions. It can also be used as a general-purpose receiver. SNIFFER RECEIVER (SnRx) The sniffer receiver provides three differential inputs that can monitor different frequency bands. Each input has a low noise amplifier (LNA) that is multiplexed to feed a single mixer. The output of this mixer stage is multiplexed with the ORx receiver mixers to feed the same baseband section. The SnRx bandwidth is limited to 20 MHz. This receiver can also be used as a general- purpose receiver if the bandwidth and RF performance are acceptable for a given application. The sniffer channel has limited operation from 400 MHz to 4000 MHz. Performance cannot be guaranteed for LO settings above 4000 MHz. These receiver inputs also provide an LNA bypass mode that removes the gain of the LNA when large signals are present. Note that no requirements for the LNA bypass mode are included in Table 1; performance specifications are only relative to the scenario in which the LNA is enabled. CLOCK INPUT The AD9371 requires a differential clock connected to the DEV_CLK_IN+/DEV_CLK_IN− pins. The frequency of the clock input must be between 10 MHz and 320 MHz, and it must have very low phase noise because this signal generates the RF local oscillator and internal sampling clocks.

bypass capacitor for each supply. the external LO option is limited to a maximum of 4000 MHz. the dedicated internal observation channel PLL. control parameters using a simple address data serial bus protocol. transferred to the specific register address. 4-wire mode or on the SDIO pin in 3-wire mode. to the VDD_IF supply can be configured for numerous functions. setting the receiver gain in real time. section that typically use a higher reference voltage. monitor system voltages without adding additional components. value latched at the ADC output. to VDDA_3P3 − 0.3 V and have a current drive of 10 mA. Table 7. AUXDAC Input Pin Assignments and Figure 231, respectively.

Table 8. Example Rx/Tx Interface Rates (Two Rx/Two Tx Channels, Maximum JESD Lane Rates) Figure 230. Example Tx Data Path Filter Implementation Figure 231. Data Rx Data Path Filter Implementation must then power up after the VDIG and VDDA_1P3 supplies. the power-up sequence to power-down. VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO. The AD9371 provides support for a JTAG boundary scan. Table 9. Dual-Function Boundary Scan Test Pins Table 10. JTAG Modes

0 XXXX 1 Normal operation

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

0.80 REF

0.44 REF

7.755 REF

8.165 REF

Figure 232. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] registered trademarks are the prop erty of their respective owners.