AD9300

AD9300 AD | Alldatasheet

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 4 × 1 Wideband Video Multiplexer AD9300 FUNCTIONAL BLOCK DIAGRAM (Based on Cerdip)

FEATURES

34 MHz Full Power Bandwidth

60.1 dB Gain Flatness to 8 MHz 72 dB Crosstalk Rejection @ 10 MHz 0.038/0.01% Differential Phase/Gain Cascadable for Switch Matrices MIL-STD-883 Compliant Versions Available

APPLICATIONS

The AD9300 is a monolithic high speed video signal multiplexer usable in a wide variety of applications. Its four channels of video input signals can be randomly switched at megahertz rates to the single output. In addition, multiple devices can be configured in either parallel or cascade arrangements to form switch matrices. This flexibility in using the AD9300 is possible because the output of the device is in a high-impedance state when the chip is not enabled; when the chip is enabled, the unit acts as a buffer with a high input im- pedance and low output impedance. An advanced bipolar process provides fast, wideband switching capabilities while maintaining crosstalk rejection of 72 dB at 10 MHz. Full power bandwidth is a minimum 27 MHz. The device can be operated from ± 10 V to ± 15 V power supplies. PIN DESIGNATIONS DIP LCC and PLCC The AD9300K is available in a 16-pin ceramic DIP and a 20-pin PLCC and is designed to operate over the commercial temperature range of 0 °C to +70°C. The AD9300TQ is a hermetic 16-pin ceramic DIP for military temperature range (–55°C to +125°C) applications. This part is also available pro- cessed to MIL-STD-883. The AD9300 is available in a 20-pin LCC as the model AD9300TE, which operates over a tempera- ture range of –55°C to +125°C. The AD9300 Video Multiplexer is available in versions compli- ant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9300/883B data sheet for de- tailed specifications. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996

Parameter (Conditions) Temp Level Min Typ Max Units INPUT CHARACTERISTICS Input Offset Voltage +25 °CI 3 1 0 m V Input Offset Voltage Full VI 14 mV Input Offset Voltage Drift 2 Full V 75 µV/°C Input Bias Current +25 °C I 15 37 µA Input Bias Current Full VI 55 µA Input Resistance +25 °C V 3.0 M Ω Input Capacitance +25 °CV 2 p F Input Noise Voltage (dc to 8 MHz) +25 °CV 1 6 µV rms TRANSFER CHARACTERISTICS Voltage Gain3 +25°C I 0.990 0.994 V/V Voltage Gain3 Full VI 0.985 V/V DC Linearity4 +25°C V 0.01 % Gain Tolerance (V IN = ± 1 V) dc to 5 MHz +25 °C I 0.05 0.1 dB 5 MHz to 8 MHz +25 °C I 0.1 0.3 dB Small-Signal Bandwidth +25 °C V 350 MHz (VIN = 100 mV p-p) Full Power Bandwidth 5 +25°C I 27 34 MHz (VIN = 2 V p-p) Output Swing Full VI ± 2V Output Current (Sinking @ = +25 °C) +25 °CV 5 m A Output Resistance +25 °C IV, V 9 15 Ω DYNAMIC CHARACTERISTICS Slew Rate6 +25°C I 170 215 V/ µs Settling Time (to 0.1% on ± 2 V Output) +25 °C IV 70 100 ns Overshoot To T-Step7 +25°C V <0.1 % To Pulse8 +25°C V <10 % Differential Phase 9 +25°C IV 0.03 0.1 ° Differential Gain 9 +25°C IV 0.01 0.1 % Crosstalk Rejection Three Channels 10 +25°CI V 6 8 7 2 d B One Channel11 +25°CI V 7 0 7 6 d B SWITCHING CHARACTERISTICS 12 AX Input to Channel HIGH Time 13 (tHIGH) +25 °C I 40 50 ns AX Input to Channel LOW Time 14 (tLOW) +25 °C I 35 45 ns Enable to Channel ON Time 15 (tON) +25 °C I 35 45 ns Enable to Channel OFF Time 16 (tOFF) +25 °C I 35 45 ns Switching Transient 17 +25°CV 6 0 m V DIGITAL INPUTS Logic “1” Voltage Full VI 2 V Logic “0” Voltage Full VI 0.8 V Logic “1” Current Full VI 5 µA Logic “0” Current Full VI 1 µA POWER SUPPLY Positive Supply Current (+12 V) +25 °C I 13 16 mA Positive Supply Current (+12 V) Full VI 13 16 mA Negative Supply Current (–12 V) +25 °C I 12.5 15 mA Negative Supply Current (–12 V) Full VI 12.5 16 mA Power Supply Rejection Ratio Full VI 67 75 dB Power Dissipation ( ± 12 V)l8 +25°C V 306 mW REV. A–2– AD9300–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (6VS = 612 V 6 5%; CL = 10 pF; RL = 2 kV, unless otherwise noted)

11Permanent damage may occur if any one absolute maximum rating is exceeded. Functional operation is not implied, and device reli ability may be impaired by exposure to higher-than-recommended voltages for extended periods of time. 12Measured at extremes of temperature range. 13Measured as slope of V OUT versus VIN with VIN = ± 1 V. 14Measured as worst deviation from endpoint fit with V IN = ± 1 V. 15Full Power Bandwidth (FPBW) based on Slew Rate (SR). FPBW = SR/2 π VPEAK 16Measured between 20% and 80% transition points of ± 1 V output. 17T-Step = Sin 2 × Step, when Step between 0 V and +700 mV points has 10% to 90% risetime = 125 ns. 18Measured with a pulse input having slew rate >250 V/ µs. 10This specification is critically dependent on circuit layout. Value shown is measured with selected channel grounded and 10 MHz 2 V p-p signal applied to remaining three channels. If selected channel is grounded through 75 Ω , value is approximately 6 dB higher. 11This specification is critically dependent on circuit layout. Value shown is measured with selected channel grounded and 10 MHz 2 V p-p signal applied to one other channel. If selected channel is grounded through 75 Ω , value is approximately 6 dB higher. Minimum specification in ( ) applies to DIPs. 12Consult system timing diagram. 13Measured from address change to 90% point of –2 V to +2 V output LOW-to-HIGH transition. 14Measured from address change to 90% point of +2 V to –2 V output HIGH-to-LOW transition. 15Measured from 50% transition point of ENABLE input to 90% transition of 0 V to –2 V and 0 V to +2 V output. 16Measured from 50% transition point of ENABLE input to 10% transition of +2 V to 0 V and –2 V to 0 V output. 17Measured while switching between two grounded channels. 18Maximum power dissipation is a package-dependent parameter related to the following typical thermal impedances: 16-Pin Ceramic θJA = 87°C/W; θJC = 25°C/W 20-Pin LCC θJA = 74°C/W; θJC = 10°C/W 20-Pin PLCC θJA = 71°C/W; θJC = 26°C/W Specifications subject to change without notice. REV. A –3– ABSOLUTE MAXIMUM RATINGS l Analog Input Voltage Each Input Differential Voltage Between Any Two Output Current Operating Temperature Range EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. Test Level II – 100% production tested at +25 °C, and sample tested at specified temperatures. Test Level III – Sample tested only. Test Level IV – Parameter is guaranteed by design and characterization testing. Test Level V – Parameter is a typical value only. Test Level VI – All devices are 100% production tested at +25°C. 100% production tested at tempera- ture extremes for military temperature de- vices; sample tested at temperature extremes for commercial/industrial devices. AD9300 ORDERlNG GUlDE Temperature Package Device Range Description Option 1 AD9300KQ 0 °C to +70°C 16-Pin Cerdip, Commercial Q-16 AD9300TE/883B2 –55°C to +125°C 20-Pin LCC, Military Temperature E-20A AD9300TQ/883B2 –55°C to +125°C 16-Pin Cerdip, Military Temperature Q-16 AD9300KP 0 °C to +70°C 20-Pin PLCC, Commercial P-20A NOTES 1E = Ceramic Leadless Chip Carrier; P = Plastic Leaded Chip Carrier; Q = Cerdip. 2For specifications, refer to Analog Devices Military Products Databook . WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9300 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. A SUGGESTED LAYOUT OF AD9300 PC BOARD AD9300 BURN-IN DIAGRAM AD9300 Timing Diagram METALIZATION PHOTOGRAPH MECHANICAL INFORMATION S or 1 mil, Gold; Gold Ball Bonding LOGIC TRUTH TABLE ENABLE A 1 A0 OUTPUT

0 X X High Z

IN1–IN4 Four analog input channels. GROUND Analog input shielding grounds, not internally con- nected. Connect each to external low-impedance ground as close to device as possible. A0 One of two TTL decode control lines required for channel selection. See Logic Truth Table. A1 One of two TTL decode control lines required for channel selection. See Logic Truth Table. ENABLE TTL-compatible chip enable. In enabled mode (logic HIGH), output signal tracks selected input channel; in disabled mode (logic LOW), output is high impedance and no signal appears at output. –VS Negative supply voltage; normally –10 V dc to –15 V dc. +VS Positive supply voltage; normally +10 V dc to +15 V dc. OUTPUT Analog output. Tracks selected input channel when enabled. BYPASS Bypass terminal for internal bias line; must be decoupled externally to ground through 0.1 µF capacitor. GROUND Analog signal and power supply ground return. RETURN

Refer to the functional block diagram of the AD9300. the DIP packaging of the models AD9300KQ and AD9300TQ. the theory of operation remains the same. device and to switch between channels at megahertz rates. complish channel selection are shown in the Logic Truth Table. Figure 1. Input and Output Equivalent Circuits greater dynamic range and/or precision than those in video. Channel 1 transistor and into the Channel 2 input transistor. log input applied to that channel is passed to the output stage. carry current and pass the selected analog input. AD9300 Analog Multiplexers together to form switch matrices.

–8– REV. A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C1184a–21–11/90PRINTED IN U.S.A. 20-Pin LCC (E) Package 16-Pin Cerdip (Q) Package 20-Pin PLCC (P) Package