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10-Bit, 65/80/105 MSPS,
3 V A/D Converter
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no re- sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Single 3 V supply operation (2.7 V to 3.3 V) SNR = 58 dBc (to Nyquist) SFDR = 77 dBc (to Nyquist) Low power ADC core: 96 mW at 65 MSPS, 104 mW @ 80 MSPS, 120 mW at 105 MSPS Differential input with 300 MHz bandwidth On-chip reference and sample-and-hold amplifier DNL = ±0.25 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer
APPLICATIONS
IF sampling in communications receivers Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes FUNCTIONAL BLOCK DIAGRAM SHA VIN+ VIN– REFT REFB DRVDD CLK PDWN MODE CLOCK DUTY CYCLE STABLIZER MODE SELECT DGND OR D9 (MSB) 02874-A-001 AVDD CORRECTION LOGIC OUTPUT BUFFERS REF SELECT AGND 0.5V VREF SENSE AD9215 PIPELINE ADC CORE Figure 1. PRODUCT DESCRIPTION The AD9215 is a family of monolithic, single 3 V supply, 10-bit, 65/80/105 MSPS analog-to-digital converters (ADC). This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9215 uses a multistage differential pipelined architecture with output error correction logic to pro- vide 10-bit accuracy at 105 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential sample-and-hold ampli- fier (SHA) allows for a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with pow- er and cost savings over previously available ADCs, the AD9215 is suitable for applications in communications, imaging, and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer compensates for wide variations in the clock duty cycle while maintaining excellent performance. The digital output data is presented in straight binary or twos complement for- mats. An out-of-range signal indicates an overflow condition, which can be used with the MSB to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9215 is avail- able in both a 28-lead surface-mount plastic package and a 32-lead chip scale package and is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. The AD9215 operates from a single 3 V power supply and features a separate digital output driver supply to accom- modate 2.5 V and 3.3 V logic families. 2. Operating at 105 MSPS, the AD9215 core ADC consumes a low 120 mW; at 80 MSPS, the power dissipation is 104 mW; and at 65 MSPS, the power dissipation is 96 mW . 3. The patented SHA input maintains excellent performance for input frequencies up to 200 MHz and can be config- ured for single-ended or differential operation. 4. The AD9215 is part of several pin compatible 10-, 12-, and 14-bit low power ADCs. This allows a simplified upgrade from 10 bits to 12 bits for systems up to 80 MSPS. 5. The clock duty cycle stabilizer maintains converter per- formance over a wide range of clock pulse widths. 6. The out of range (OR) output bit indicates when the signal is beyond the selected input range.
Rev. B | Page 2 of 36 TABLE OF CONTENTS
REVISION HISTORY
2/13—Data Sheet Changed from a REV . A to a REV . B Changes to Figure 4 and Added EPAD Note to Pin Configura- 2/04—Data Sheet Changed from a REV . 0 to a REV . A 5/03—Revision 0: Initial Version
Table 1. DC Specifications 1 With a 1.0 V internal reference. 2 Measured at fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure. 4 Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
AIN = −0.5 dBFS, MODE = AVDD/3 (duty cycle stabilizer [DCS] enabled), unless otherwise noted. Table 2. AC Specifications
Table 3. Digital Specifications 1 Output voltage levels measured with a 5 pF load on each output. Table 4. Switching Specifications Figure 2. Timing Diagram 1 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 2 Wake-up time is dependent on the value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Rev. B | Page 6 of 36 ABSOLUTE MAXIMUM RATINGS1 Table 5. Mnemonic With Respect to Min Max Unit ELECTRICAL AVDD AGND −0.3 +3.9 V DRVDD DRGND −0.3 +3.9 V AGND DRGND −0.3 +0.3 V AVDD DRVDD −3.9 +3.9 V Digital Outputs DRGND −0.3 DRVDD + 0.3 V CLK, MODE AGND −0.3 AVDD + 0.3 V VIN+, VIN− AGND −0.3 AVDD + 0.3 V VREF AGND −0.3 AVDD + 0.3 V SENSE AGND −0.3 AVDD + 0.3 V REFB, REFT AGND −0.3 AVDD + 0.3 V PDWN AGND −0.3 AVDD + 0.3 V ENVIRONMENTAL2 Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature −40 +85 °C 150 °C 300 °C −65 +150 °C NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Typical thermal impedances 28-lead TSSOP: θJA = 67.7°C/W, 32-lead LFCSP: θJA = 32.7°C/W; heat sink soldered down to ground plane. EXPLANATION OF TEST LEVELS Test Level I 100% production tested. II 100% production tested at 25°C and sample tested at spec- ified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for mili- tary devices. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 9 of 36 with the supply at its maximum limit. Signal-to-Noise and Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the measured input sig- nal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. Temperature Drift The temperature drift for zero error and gain error specifies the maximum change from the initial (25°C) value to the value at T MIN or TMAX. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It may be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
Figure 15. AD9215-80 SNR/SFDR vs.
2 SFDR dBc
Figure 16. AD9215-105 SNR/SFDR vs. Figure 17. AD9215-65 SNR/SFDR vs. Figure 18. AD9215-105 SNR/SFDR vs. Figure 19. AD9215-80 SNR/SFDR vs. Figure 20. AD9215-65 SNR/SFDR vs.
Figure 21. Two-Tone 32k FFT with fIN1 = 70.1 MHz, Figure 22. Two-Tone 32k FFT with fIN1 = 100.3 MHz, Figure 23. AD9215-105 Two-Tone SFDR vs. AIN, Figure 24. AD9215-80 Two-Tone SFDR vs. AIN, fIN1 = 100.3 MHz, and fIN2 =
101.3 MHz, fSAMPLE = 105 MSPS
Figure 25. SINAD, SFDR vs. Figure 26. SINAD, SFDR vs. Temperature,
Table 7. Reference Configuration Summary Table 8. Digital Output Coding
2 V p-p (V)
1 V p-p (V)
analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. encode rate and the characteristics of the analog input signal. ure 35 was taken with a 5 pF load on each output driver. Figure 35. Supply Current vs. fSAMPLE for fIN = 10.3 MHz
5 TO 1: TWOS COMPLEMENT/DCS OFF
5 TO 2: TWOS COMPLEMENT/DCS ON
5 TO 3: OFFSET BINARY/DCS ON
5 TO 4: OFFSET BINARY/DCS OFF
Figure 41. LFCSP Evaluation Board Schematic, Analog Inputs and DUT
6 COMM
7 OPLO
8 OPHI
9 VPOS
10 VOCM
Figure 42. LFCSP Evaluation Board, Digital Path
SCHEMATIC SHOWS TWO-GATE DELAY SETUP. Figure 43. LFCSP Evaluation Board Schematic, Clock Input
Table 10. LFCSP Evaluation Board Bill of Materials (BOM)
8 C6, C18, C27, C17,
2 C46, C24,
2 C21, C23
2 E1, E45
6 R37, R22, R42, R16, R17, R27
1 R19
19 1 U4 AD9215BCP ADC (DUT) CSP-32 Analog Devices, Inc. 21 1 PCB AD9XXBCP/PCB PCB Analog Devices, Inc. 22 1 U3 AD8351 Op Amp MSOP-8 Analog Devices, Inc. 1 These items are included in the PCB design but are omitted at assembly.
- R6, R34 FOR DIFFERENTIAL OPERATION
- C1, C33 FOR OP AMP OPERATION
- R7, R46, R5, C9, C23 FOR SINGLE-ENDED OPERATION
Figure 50. TSSOPP Evaluation Board Schematic, Analog Inputs and DUT
Figure 51. TSSOP Evaluation Board, Digital Path
Figure 52. TSSOP Evaluation Board Schematic, Clock Input
Table 11. TSSOP Evaluation Board Bill of Materials (BOM)
1 C31
2 R48, R49
8 R5, R35, R17 to R18,
1 R14
Rev. B | Page 32 of 36 Item Qty. Omit Reference Designator Device Package Value Recommended Vendor/Part No. 24 1 L1 Chip Inductor 0603 10 nH Coilcraft/0603CS- 10NXGBU 25 1 T1 1:1 RF Transformer CD542 Mini-Circuits AWT1-1T 26 1 U1 ADC 28TSSOP Analog Devices, Inc. AD9215 27 1 U2 Right Angle 40-Pin Header Samtec TSW-120-08-T-D-RA 28 2 U3, U4 Octal D-Type Flip-Flop Fairchild 74LVT57MSA 29 1 U5 Quad XOR Gate SO14 Fairchild 74VCX86M 30 1 U6 High Speed Amplifier SOMB10 Analog Devices, Inc. AD8351ARM 31 2 J1, J3 SMB Connecter SMBP 1 J4 32 2 P1, P2 Power Connector PTMICRO4 Weiland Z5.531.3425.0 Posts
25.602.5453.0 Top
33 26 E1/E5, E2/E3, E4/E8, E9/E11, E6/E7, E16/E17, E19/E22, E18/E23, E21/20, E35/E51, E36/E50, E43/E53, E44/E52 Headers/Jumper Blocks TSW-120-07-G-S SMT-100-BK-G 34 12 E24/E27, E25/E26, E28/E29, E13/E14/E30, E12/E32/E45 Wirehole
1.20 MAX
6.40 BSC
Figure 59. 28-Lead Thin Shrink Small Outline Package [TSSOP] COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
Figure 60. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Rev. B | Page 34 of 36 ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9215BRUZ-65 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BRUZ-80 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BRUZ-105 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BRUZRL7-65 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BRUZRL7-80 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BRUZRL7-105 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BCPZ-65 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 AD9215BCPZ-80 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 AD9215BCPZ-105 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 1 Z = RoHS Compliant Part.
Rev. B | Page 35 of 36 NOTES
Rev. B | Page 36 of 36 NOTES ©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02874-0-2/13(B)