AD9214BRS-105

AD9214 AD | Alldatasheet

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REV.D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9214 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 10-Bit, 65/80/105 MSPS

3 V A/D Converter

D 9–D0 DGND ENCODE AIN AIN DFS/GAIN REFSENSEREF PIPELINE ADC CORE T/HBUFFER OUTPUT REGISTER

FEATURES

SNR = 57 dB @ 39 MHz Analog Input (–0.5 dBFS) Low Power 190 mW at 65 MSPS 285 mW at 105 MSPS 30 mW Power-Down Mode

300 MHz Analog Bandwidth

On-Chip Reference and Track/Hold

1 V p-p or 2 V p-p Analog Input Range Option

Single 3.3 V Supply Operation (2.7 V–3.6 V) Two’s Complement or Offset Binary Data Format Option

APPLICATIONS

Battery-Powered Instruments Hand-Held Scopemeters Low-Cost Digital Oscilloscopes Ultrasound Equipment Cable Reverse Path Broadband Wireless Residential Power Line Networks PRODUCT DESCRIPTION The AD9214 is a 10-bit monolithic sampling analog-to- digital converter (ADC) with an on-chip track-and-hold circuit, and is optimized for low cost, low power, small size, and ease of use. The product operates up to 105 MSPS conversion rate with outstanding dynamic performance over its full operating range. The ADC requires only a single 3.3 V (2.7 V to 3.6 V) power supply and an encode clock for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS com patible and a separate output power supply pin supports in terfacing with 3.3 V or 2.5 V logic. The clock input is TTL/CMOS compatible. In the power-down state, the power is reduced to 30 mW. A gain option allows support for either 1 V p-p or 2 V p-p analog signal input swing. Fabricated on an advanced CMOS process, the AD9214 is available in a 28-lead surface-mount plastic package (28-SSOP) specified over the industrial temperature range (–40°C to +85°C). PRODUCT HIGHLIGHTS High Performance—Outstanding ac performance from 65 MSPS to 105 MSPS. SNR greater than 55 dB typical and as high as 58 dB. Low Power—The AD9214 at 285 mW consumes a fraction of the power available in existing high-speed monolithic solutions. In sleep mode, power is reduced to 30 mW. Single Supply—The AD9214 uses a single 3 V supply, simplify- ing system power supply design. It also features a separate digital output driver supply line to accommodate 2.5 V logic families. Small Package—The AD9214 is packaged in a small 28-lead surface-mount plastic package (28-SSOP).

REV. D–2– AD9214–SPECIFICATIONS DC SPECIFICATIONS Test AD9214-65 AD9214-80 AD9214-105 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 10 10 10 Bits ACCURACY No Missing Codes 25 °C VI Guaranteed Guaranteed Guaranteed Full VI Guaranteed Guaranteed Offset Error Full VI –18 0 +18 –18 0 +18 –18 0 +18 LSB Gain Error TEMPERATURE DRIFT Offset Error Full V 16 16 16 ppm/ °C Gain Error1 Full V 150 150 150 ppm/ °C Reference Voltage Full V 80 80 80 ppm/ °C REFERENCE (REF) Output Current 3 Full V 200 200 200 µA Input Current 4 Full V 123 123 123 µA Input Resistance Full V 10 10 10 k Ω ANALOG INPUTS (A IN, AIN) Differential Input Range Full V 1 or 2 1 or 2 1 or 2 V p-p Common-Mode Voltage Full V AV DD/3 AV DD/3 AV DD/3 V Differential Input Resistance 5 Full V 20 20 20 k Ω Differential Input Capacitance Full V 5 5 5 pF POWER SUPPLY Supply Voltages Supply Current IAVDD (AVDD = 3.0 V)6 Full VI 64 75 90 105 95 110 mA Power-Down Current 7 IAVDD (AVDD = 3.0 V) Full VI 10 15 10 15 10 15 mA Power Consumption 8 Full VI 190 220 250 300 285 325 mW PSRR 25 °CI ± 0.5 ± 1 ± 1 LSB/V Full V ± 2 ± 2 ± 2 mV/V NOTES 1Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference). 2Measured with 1 V A IN range for AD9214-80 and AD9214-105. Measured with 2 V A IN range for AD9214-65. 3REFSENSE externally connected to AGND, REF is configured as an output for the internal reference voltage. 4REFSENSE externally connected to AV DD, REF is configured as an input for an external reference voltage. 510 kΩ to AVDD/3 on each input. 6IAVDD is measured with an analog input of 10.3 MHz, 0.5 dBFS, sine wave, rated encode rate, and PWRDN = 0. See Typical Performance C haracteristics and Applications section for I DrVDD. 7Power-down supply currents measured with PWRDN = 1; rated encode rate, A IN = full-scale dc input. 8Power consumption measured with A IN = full-scale dc input. Specifications subject to change without notice. (AVDD = 3 V, DrVDD = 3 V; TMIN = –40 /H11543C, TMAX = +85/H11543C; external 1.25 V voltage reference and rated encode frequency used, unless otherwise noted.)

REV. D –3– AD9214 DIGITAL SPECIFICATIONS Test AD9214-65 AD9214-80 AD9214-105 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit DIGITAL INPUTS 1 Logic “1” Voltage Full IV 2.0 2.0 2.0 V Logic “0” Voltage Full IV 0.8 0.8 0.8 V Input Capacitance Full V 2.0 2.0 2.0 pF DIGITAL OUTPUTS 2 Logic Compatibility CMOS/TTL CMOS/TTL CMOS/TTL V Logic “1” Voltage Full VI DrV DD – 50 mV DrV DD – 50 mV DrV DD – 50 mV V Logic “0” Voltage Full VI 50 50 50 mV NOTES 1Digital Inputs include ENCODE and PWRDN. 2Digital Outputs include D0–D9 and OR. Specifications subject to change without notice. AC SPECIFICATIONS1 Test AD9214-65 AD9214-80 AD9214-105 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit SNR 51 MHz 25 °C V 55.0 53.0 dB 70 MHz 25 °C V 54.0 52.6 dB SINAD 51 MHz 25 °C V 54.5 52.0 dB 70 MHz 25 °C V 52.0 dB EFFECTIVE NUMBER OF BITS 51 MHz 25 °C V 8.8 8.4 Bit 70 MHz 25 °C V 8.5 8.4 Bit SECOND HARMONIC DISTORTION Analog Input 10 MHz 25 °C I –66 –79 –64 –74 –62 –68 dBc @ –0.5 dBFS 39 MHz 25 °C I –75 –63 –76 –62 –71 dBc

51 MHz 25 °C V –72 –64 dBc

70 MHz 25 °C V –65 –62 dBc

Analog Input 10 MHz 25 °C I –63.5 –71 –63 –72 –59 –64 dBc @ –0.5 dBFS 39 MHz 25 °C I –70 –63 –74 –59 –67 dBc

51 MHz 25 °C V –78 –71 dBc

70 MHz 25 °C V –65 dBc

Analog Input 10 MHz 25 °C I 63.5 71 63 71 57 62 dBc @ –0.5 dBFS 39 MHz 25 °C I 70 63 71 57 62 dBc

51 MHz 25 °C V 67 62 dBc

70 MHz 25 °C V 64 62 dBc

TWO-TONE INTERMOD DISTORTION2 Analog Input @ –0.5 dBFS 25 °C V 76 74 72 dBFS ANALOG INPUT BANDWIDTH 25 °C V 300 300 300 MHz NOTES 1AC specifications based on a 1.0 V p-p full-scale input range for the AD9214-80 and AD9214-105, and a 2.0 V p-p full-scale inpu t range for the AD9214-65. An external reference is used. 2F1 = 29.3 MHz, F2 = 30.3 MHz. Specifications subject to change without notice. (AVDD = 3 V, DrVDD = 3 V; ENCODE = Maximum Conversion Rate; T MIN = –40 /H11543C, TMAX = +85 /H11543C; external 1.25 V voltage reference used, unless otherwise noted.) (AVDD = 3 V, DrVDD = 3 V; TMIN = –40 /H11543C, TMAX = +85/H11543C)

an ac load of 5 pF or a dc current of ± 40 µA. Specifications subject to change without notice. Figure 1. Timing Diagram

REV. D AD9214 –5– ABSOLUTE MAXIMUM RATINGS 1 Electrical DD + 0.5 V Environmental2 Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) . . . –65 °C to +150°C NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not n ecessarily implied. Exposure to absolute maximum rating condi- tions for an extended period of time may affect device reliability. 2Typical thermal impedances (package = 28 SSOP); θJA = 49 °C/W. These measurements were taken on a 6-layer board in still air with a solid ground plane. EXPLANATION OF TEST LEVELS I 100% production tested. II 100% production tested at 25 °C and guaranteed by design and characterization at specified temperatures. III Sample Tested Only IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25 °C and guaranteed by design and characterization for industrial temperature range. ORDERING GUIDE Model Temperature Range Package Description Package Option AD9214BRS-65 –40 °C to +85°C (Ambient) 28-Lead Shrink Small Outline Package RS-28 AD9214BRS-80 –40 °C to +85°C (Ambient) 28-Lead Shrink Small Outline Package RS-28 AD9214BRS-105 –40 °C to +85°C (Ambient) 28-Lead Shrink Small Outline Package RS-28 AD9214-65PCB 25 °C Evaluation Board with AD9214-65 AD9214-105PCB 25 °C Evaluation Board with AD9214-105 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9214 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

REV. D AD9214 –6– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 OR CMOS Output; Out-of-Range Indicator. Logic HIGH indicates the analog input voltage was outside the converter’s range for the current output data. 2 DFS/GAIN Data Format Select and Gain Mode Select. Connect externally to AV DD for two’s complement data format and 1 V p-p analog input range. Connect externally to AGND for Offset Binary data format and 1 V p-p analog input range. Connect externally to REF (Pin 4) for two’s complement data format and 2 V p-p analog input range. Floating this pin will configure the device for Offset Binary data format and a 2 V p-p analog input range. 3 REFSENSE Reference Mode Select Pin for the ADC. This pin is normally connected externally to AGND, which enables the internal 1.25 V reference, and configures REF (Pin 4) as an analog reference output pin. Connecting REFSENSE externally to AV DD disables the internal reference, and config- ures REF (Pin 4) as an external reference input. In this case, the user must drive REF with a clean and accurate 1.25 V (±5%) reference input. 4 REF Reference input or output as configured by REFSENSE (Pin 3). When configured as an output (REFSENSE = AGND), the internal reference (nominally 1.25 V) is enabled and is available to the user on this pin. When configured as an input (REFSENSE = AV DD), the user must drive REF with a clean and accurate 1.25 V ( ± 5%) reference. This pin should be bypassed to AGND with an external 0.1 µF capacitor, whether it is configured as an input or output. 5, 8, 11 AGND Analog Ground 6, 7, 12 AV DD Analog Power Supply, Nominally 3 V 9A IN Positive terminal of the differential analog input for the ADC. 10 AIN Negative terminal of the differential analog input for the ADC. This pin can be left open if operating in single-ended mode, but it is preferable to match the impedance seen at the positive terminal (see Driving the Analog Inputs). 13 ENCODE Encode Clock for the ADC. The AD9214 samples the analog signal on the rising edge of ENCODE.

14 PWRDN CMOS-compatible power-down mode select, Logic LOW for normal operation; Logic HIGH

for power-down mode (digital outputs in high impedance state). PWRDN has an internal 10 kΩ pull-down resistor to ground. 15, 23 DGND Digital Output Ground 16, 24 DrV DD Digital Output Driver Power Supply. Nominally 2.5 V to 3.6 V. 17–22, 25–28 D0 (LSB)–D5, CMOS Digital Outputs of ADC D6–D9 (MSB) PIN CONFIGURATION 28-Lead Shrink Small Outline Package TOP VIEW (Not to Scale) AD9214 PWRDN ENCODE AVDD AGND AIN AIN AGND OR DFS/GAIN REFSENSE REF AVDD AVDD AGND DGND DrVDD D0 (LSB) D9 (MSB) DGND DrV DD

REV. D AD9214 –7– TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Analog Input Resistance, Differential Analog Input Capacitance and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capaci- tance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differen- tial voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. Then the difference is computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits The effective number of bits (ENOB) is calculated from the measured SNR based on the equation: ENOB SINAD dB Full Scale Actual MEASURED +  – . log 17 6 2 0 60 2 Encode Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic “1” state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these specs define an acceptable Encode duty cycle. Full-Scale Input Power Expressed in dBm. Computed using the following equation: Power V Z FULL SCALE FULL SCALE rms INPUT= 10 0 001 log . Gain Error Gain error is the difference between the measured and ideal full scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line ” determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Noise (for any range within the ADC) VZ FS SNR Signal NOISE dBm dBc dBFS=× × −−0 001 10 10. Where Z is the input impedance, FS is the full-scale of the device for the frequency in question, SNR is the value for the particular input level and Signal is the signal level within the ADC reported in dB below full-scale. This value includes both thermal and quantization noise. Power Supply Rejection Ratio (PSRR) The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 0.5 dB below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 0.5 dB below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo- nent may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an intermodulation distortion product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc.

REV. D AD9214 –9– FREQUENCY – MHz dB 52.5 –100 –50 –90 –80 –70 –60 –40 –30 –20 –10 ENCODE: 105MSPS AIN: 50.3MHz @ –0.5dBFS SNR: 53.0dB ENOB: 8.5 BITS SFDR: 64dBFS TPC 1. FFT: fS = 105 MSPS, fIN = ~50.3 MHz; AIN = –0.5 dBFS Differential, 1 V p-p Analog Input Range 0 40 –100 –50 –90 –80 –70 –60 –40 –30 –20 –10 ENCODE: 80MSPS AIN: 70.3MHz @ –0.5dBFS SNR: 54.0dB ENOB: 8.5 BITS SFDR: 64dBFS FREQUENCY – MHz dB TPC 2. FFT: fS = 80 MSPS, fIN = 70 MHz; AIN = –0.5 dBFS,

1 V p-p Analog Input Range

FREQUENCY– MHz dB 52.5 –100 –50 –90 –80 –70 –60 –40 –30 –20 –10 ENCODE: 105MSPS AIN: 70.3MHz @ –0.5dBFS SNR: 52.6dB ENOB: 8.4 BITS SFDR: 62.6dBFS TPC 3. FFT: fS = 105 MSPS; fIN = 70 MHz (1 V p-p) Typical Performance Characteristics– FREQUENCY– MHz dB 52.5 –100 –50 –90 –80 –70 –60 –40 –30 –20 –10 ENCODE: 65MSPS AIN: 15.3MHz @ –0.5dBFS SNR: 56.9dB ENOB: 9.2 BITS SFDR: 70dB TPC 4. FFT: fS = 65 MSPS, fIN = 15.3 MHz (2 V p-p) with AD8138 Driving AIN AIN FREQUENCY – MHz dB 100 605040302010 3RD SFDR 2ND TPC 5. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency (1 V p-p, fS = 105 MSPS) AIN FREQUENCY – MHz dB 755025 2ND SFDR 3RD TPC 6. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency (1 V p-p, fS = 80 MSPS)

REV. D AD9214 –10– FREQUENCY – MHz dB70 100 604020 3RD SFDR 2ND TPC 7. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency (1 V p-p and 2 V p-p, fS = 65 MSPS) dB –100 –50 –90 –80 –70 –60 –40 –30 –20 –10 ENCODE: 80MSPS AIN: 29.3MHz @ –6dBFS 30.3MHz @ –6dBFS SFDR: 74dBFS FREQUENCY – MHz 0 40 TPC 8. Two-Tone Intermodulation Distortion (29.3 MHz,

30.3 MHz; 1 V p-p, fS = 80 MSPS)

–100 –50 –90 –80 –70 –60 –40 –30 –20 –10 FREQUENCY – MHz 0 52.5 ENCODE: 105MSPS AIN: 30MHz @ –6dBFS 31MHz @ –6dBFS SFDR: 73dBFS TPC 9. Two-Tone Intermodulation Distortion (30 MHz and

31 MHz; 1 V p-p, fS = 105 MSPS)

ENCODE RATE – MSPS SIGNAL LEVEL – dB 604020 SINAD – 2V p–p SINAD – 1V p–p SFDR – 2V p–p SFDR – 1V p–p 100 120 TPC 10. SINAD and SFDR vs. Encode Rate (fIN = 10.3 MHz;

1 V p-p and 2 V p-p)

SIGNAL LEVEL – dB PULSEWIDTH HIGH – ns 2468 1 0 SINAD – 105MSPS SINAD – 80MSPS SFDR – 105MSPS SFDR – 80MSPS TPC 11. SINAD and SFDR vs. Encode Pulsewidth High (1 V p-p) IAVDD – mA 120 100 ENCODE RATE – MSPS 0 20 120 IAVDD IDrVDD – mA 40 60 80 100 IDrVDD TPC 12. IAVDD and IDrVDD vs. Encode Rate (fAIN = 10.3 MHz, –0.5 dBFS, and –3 dBFS) CLOAD on Digital Outputs ~7 pF

REV. D AD9214 –11– TEMPERATURE – /H11543C –40 SIGNAL LEVEL – dB 80400 SINAD 10.3MHz/105MSPS SNR 10.3MHz/105MSPS TPC 13. SINAD/SNR vs. Temperature (fAIN = 10.3 MHz, fENCODE = 105 MSPS, 1 V p-p) TEMPERATURE – /H11543C –40 % FULL SCALE 0.5 4.0 0.0 1.0 1.5 2.0 2.5 80400 3.0 3.5 TPC 14. ADC Gain vs. Temperature (with External 1.25 V Reference) TEMPERATURE – /H11543C –40 REFERENCE VOLTAGE – V 1.240 1.220 1.225 1.230 80400 1.235 TPC 15. ADC Reference vs. Temperature (with 200 µA Load) IREF – /H9262A –500 VREF – V 1.40 1.10 1.15 1.25 1.35 1.30 1.20 –400 –300 –200 –100 0 100 200 300 400 500 TPC 16. ADC Reference vs. Current Load CODE INL – LSB 1.00 –1.00 –0.75 0.00 0.75 0.25 –0.25 128 256 384 512 640 768 896 1024 0.50 –0.50 TPC 17. INL @ 80 MSPS CODE DNL – LSB 1.00 –1.00 –0.75 0.00 0.75 0.25 –0.25 128 256 384 512 640 768 896 1024 0.50 –0.50 TPC 18. DNL @ 80 MSPS

controlled TTL/CMOS oscillator. ac coupling such a source to the ENCODE input. Figure 7. AC-Coupled Encode Circuit the internal reference voltage.

1 V p-p or 2 V p-p as determined by DFS/Gain) will track the

occurs when an external reference is adjusted ±5%. age range) of the ADC. The table below describes its operation. performance, impedances at A IN and AIN should match. Figure 8. Single-Ended-to-Differential Conversion Using dation in performance (see DFS/GAIN pin description a bove).

Figure 9. DC-Coupled Analog Input Circuit and the internal timing and digital error correction circuits. the Typical Performance Characteristics section. for a 10.3 MHz sine wave driving the analog input. ground (AGND and DGND) connections. series resistor (e.g., 100 Ω) followed by a gate like the 74LCX821. appreciably add to the dynamic switching currents of the AD9214. timing is guaranteed with 10 pF loads. side for isolation purposes. only one gate should be used for all AD9214 digital outputs. must be isolated from the digital outputs and the analog inputs. layout, and Bill of Materials.

1 LVC 3 V

7 VCC 3 V

9 VDD 3 V

11 DAC 5 V

only required if the user adds differential op amp Z1 to the board.

REV. D AD9214 –14– Reference Circuit The evaluation board is configured at assembly to use the AD9214’s on-board reference. To supply an external reference, the user must connect the REFSENSE pin to VCC by removing the jumper block connecting E25 to E26, and placing it between E19 and E24. In this configuration, an external 1.25 V reference must be connected to jumper connection E23. Jumper connections E19–E21, E24, and resistors R13–R14 are omitted at assembly, and not used in the evaluation of the AD9214. Gain/Data Format The evaluation board is assembled with the DFS/GAIN pin connected to ground; this configures the AD9214 for a 1 V p-p analog input range, and offset binary data format. The user may remove this jumper and replace it to make one of the connections described in the table below to configure the AD9214 for different gain and output data format options. Table III. Data Format and Gain Configuration for Evaluation Board DFS/GAIN Jumper DFS/GAIN Differential Output Data Placement Connection A IN Range Format E18 to E12 AGND 1 V p-p Offset Binary E16 to E11 AV DD 1 V p-p Two ’s Complement E15 to E14 REF 2 V p-p Two ’s Complement E17 to E13 Floating 2 V p-p Offset Binary Power-Down The evaluation board is configured at assembly so that the PWRDN input floats low for normal operating condition. The user may add a jumper between option holes E5 and E6 to connect PWRDN to AVCC, configuring the AD9214 for power- down mode. Encode Signal and Distribution The encode input signal should drive SMB connector J5, which has an on-board 50 Ω termination. A standard CMOS compatible pulse source is recommended. Alternatively, the user can adjust the dc level of an ac-coupled clock source by adding resistor R11, normally omitted. J5 drives the AD9214 ENCODE input and one gate of U12, which buffers and distributes the clock signal to the on-board latch (U3), the reconstruction DAC (U11), and the output data connector (U2). The board comes assembled with timing options optimized for the DAC and latch; the user may invert the DR signal at Pin 37 of edge connector U2 by removing the jumper block between E34 and E35, and reinstalling it between E35 and E36. Analog Input The analog input signal is connected to the evaluation board by SMB connector J1. As configured at assembly, the signal is ac coupled by capacitor C10 to transformer T1. This 1:1 transformer provides a 50 Ω termination for connector J1 via 25 Ω resistors R1 and R4. T1 also converts the signal at J1 into a differential signal for the analog inputs of the AD9214. Resistor R3, normally omitted, can be used to terminate J1 if the transformer is removed. The user can reconfigure the board to drive the AD9214 single- endedly by removing the jumper block between E1 and E3, and replacing it between E3 and E2. In this configuration, capacitor C2 stabilizes the self-bias of AIN, and resistor R2 provides a matched impedance for a 50 Ω source at J1. Transformer T1 can be bypassed by moving the jumper normally between E40 and E38 to connect E40 to E37, and moving the jumper normally between E39 and E10 to connect E7 to E10. In this configuration, the analog input of the AD9214 is driven single ended, directly from J1; and R3 (normally omitted) should be installed to terminate any cable connected to J1. Using the AD8138 An optional driver circuit for the analog input, based on the AD8138 differential amplifier, is included in the layout of the AD9214 evaluation board. This portion of the evaluation circuit is not populated when the board is manufactured, but can be easily be added by the user. Resistors R5, R16, R18, and R25 are the feedback network that sets the gain of the AD8138. Resistors R23 and R24 set the common-mode voltage at the output of the op amp. Resistors R27 and R28, and capacitor C15, form a low-pass filter at the output of the AD8138, limiting its noise contribution into the AD9214. Once the drive circuit is populated, the user should remove the jumper block normally between E40 and E38, and place it between E40 and E41. This will ac-couple the analog input signal from SMB connector J1 to the AD8138 drive circuit. The user will also need to remove the jumper blocks that normally connect E39 to E10 and E1 to E3 to remove transformer T1 from the circuit. DAC Reconstruction Circuit The data available at output connector U2 is also reconstructed by DAC U11, the AD9752. This 12-bit, high-speed digital-to-analog converter is included as a tool in setting up and debugging the evaluation board. It should not be used to measure the per- formance of the AD9214, as its performance will not accurately reflect the performance of the ADC. The DAC’s output, available at J2, will drive 50 Ω. The user can add a jumper block between E8 and E9 to activate the SLEEP function of the DAC.

REV. D AD9214 –15– AD9214/PCB Bill of Material # Quantity Reference Designator Device Package Value 1 1 N/A PCB 21 9 C 1 –C3, C5–C14, C16–C20, C25–C28 Capacitor 603 0.1 µF 3 4 C21 –C24 Capacitor CAPTAJD 10 µF 4 1 C4 Capacitor 603 0.01 µF 5 4 R1, R2, R4, R8 Resistor 1206 25 Ω 6 4 R7, R10, R12, R17 Resistor 1206 50 Ω

74 U 5 –U8 Resistor RPAK_742 100 Ω

8 1 R21 Resistor 1206 0 Ω 9 2 R6, R9 Resistor 1206 2000 Ω 10 37 E1 –E6, E8–E9, E11–E27, E29, E31–E41 Test Points TSW-120-07-G-S Jumper Connections SMT-100-BK-G 11 3 J1, J2, J5 Connector SMB 51-52-220 12 1 U12 Clock Chip SOIC SN74LVC86 13 1 U11 DAC SOIC AD9752 14 1 U3 Latch SOIC 74LCX821 15 1 U1 ADC/DUT SOIC AD9214 16 1 U2 40-Pin Header Samtec TSW-120-07-G-D 17 1 T1 Transformer Mini Circuits ADT1-1WT 18 3 U4, U9, U10 Power Strip Newark 95F5966 Power Connector 25.602.5453.0 The following items are included in the PCB design, but are omitted at assembly. 19 3 C1, C20, C28 Capacitor 603 0.1 µF 20 2 C30, C29 Capacitor CAPTAJD 10 µF 21 1 C15 Capacitor 603 15 pF 22 4 R5, R18, R25, R26 Resistor 1206 500 Ω 23 1 R23 Resistor 1206 1 k Ω 24 1 R24 Resistor 1206 4 k Ω 25 3 R11, R15, R16 Resistor 1206 User Select 26 2 R13, R14 Resistor 1206 N/A 27 3 R27, R28, R3 Resistor 1206 50 Ω 28 1 R19 Resistor 1206 0 Ω 29 1 Z1 Op Amp SOIC AD8138

Figure 10. PCB Schematic

REV. D AD9214 –18– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (RS-28) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 0°0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) SEATING PLANE 0.0256 (0.65) BSC 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 28 15 141 0.407 (10.34) 0.397 (10.08) PIN 1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

REV. D AD9214 –19–

Revision History

Data Sheet changed from REV. C to REV. D. 07/01—Data Sheet changed from REV. B to REV. C. 05/01—Data Sheet changed from REV. A to REV. B. 01/01—Data Sheet changed from REV. 0 to REV. A.

–20– C01693–0–2/02(D) PRINTED IN U.S.A.